Commit | Line | Data |
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ec9be0de FE |
1 | /* |
2 | * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. | |
3 | * | |
4 | * Author: Fabio Estevam <fabio.estevam@freescale.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
ec9be0de FE |
15 | */ |
16 | ||
8fdca37a UKK |
17 | /* |
18 | * This machine is known as: | |
19 | * - i.MX27 3-Stack Development System | |
20 | * - i.MX27 Platform Development Kit (i.MX27 PDK) | |
21 | */ | |
22 | ||
ec9be0de FE |
23 | #include <linux/platform_device.h> |
24 | #include <linux/gpio.h> | |
b5ec73eb | 25 | #include <linux/irq.h> |
96cf4239 FE |
26 | #include <linux/usb/otg.h> |
27 | #include <linux/usb/ulpi.h> | |
28 | #include <linux/delay.h> | |
c67a3e09 FE |
29 | #include <linux/mfd/mc13783.h> |
30 | #include <linux/spi/spi.h> | |
31 | #include <linux/regulator/machine.h> | |
1abcb4cc | 32 | #include <linux/spi/l4f00242t03.h> |
96cf4239 | 33 | |
4c11c286 FE |
34 | #include <media/soc_camera.h> |
35 | ||
ec9be0de FE |
36 | #include <asm/mach-types.h> |
37 | #include <asm/mach/arch.h> | |
38 | #include <asm/mach/time.h> | |
39 | #include <mach/hardware.h> | |
40 | #include <mach/common.h> | |
e835d88e | 41 | #include <mach/iomux-mx27.h> |
96cf4239 | 42 | #include <mach/ulpi.h> |
92cb33f1 FE |
43 | #include <mach/irqs.h> |
44 | #include <mach/3ds_debugboard.h> | |
ec9be0de | 45 | |
d5dac4a6 | 46 | #include "devices-imx27.h" |
ec9be0de | 47 | |
98618cfe FE |
48 | #define SD1_EN_GPIO IMX_GPIO_NR(2, 25) |
49 | #define OTG_PHY_RESET_GPIO IMX_GPIO_NR(2, 23) | |
50 | #define SPI2_SS0 IMX_GPIO_NR(4, 21) | |
51 | #define EXPIO_PARENT_INT gpio_to_irq(IMX_GPIO_NR(3, 28)) | |
aec250dc | 52 | #define PMIC_INT IMX_GPIO_NR(3, 14) |
1abcb4cc | 53 | #define SPI1_SS0 IMX_GPIO_NR(4, 28) |
c084473d | 54 | #define SD1_CD IMX_GPIO_NR(2, 26) |
1abcb4cc FE |
55 | #define LCD_RESET IMX_GPIO_NR(1, 3) |
56 | #define LCD_ENABLE IMX_GPIO_NR(1, 31) | |
4c11c286 FE |
57 | #define CSI_PWRDWN IMX_GPIO_NR(4, 19) |
58 | #define CSI_RESET IMX_GPIO_NR(3, 6) | |
b5ec73eb | 59 | |
6c80ee51 | 60 | static const int mx27pdk_pins[] __initconst = { |
ec9be0de FE |
61 | /* UART1 */ |
62 | PE12_PF_UART1_TXD, | |
63 | PE13_PF_UART1_RXD, | |
64 | PE14_PF_UART1_CTS, | |
65 | PE15_PF_UART1_RTS, | |
66 | /* FEC */ | |
67 | PD0_AIN_FEC_TXD0, | |
68 | PD1_AIN_FEC_TXD1, | |
69 | PD2_AIN_FEC_TXD2, | |
70 | PD3_AIN_FEC_TXD3, | |
71 | PD4_AOUT_FEC_RX_ER, | |
72 | PD5_AOUT_FEC_RXD1, | |
73 | PD6_AOUT_FEC_RXD2, | |
74 | PD7_AOUT_FEC_RXD3, | |
75 | PD8_AF_FEC_MDIO, | |
76 | PD9_AIN_FEC_MDC, | |
77 | PD10_AOUT_FEC_CRS, | |
78 | PD11_AOUT_FEC_TX_CLK, | |
79 | PD12_AOUT_FEC_RXD0, | |
80 | PD13_AOUT_FEC_RX_DV, | |
81 | PD14_AOUT_FEC_RX_CLK, | |
82 | PD15_AOUT_FEC_COL, | |
83 | PD16_AIN_FEC_TX_ER, | |
84 | PF23_AIN_FEC_TX_EN, | |
b5ec73eb RP |
85 | /* SDHC1 */ |
86 | PE18_PF_SD1_D0, | |
87 | PE19_PF_SD1_D1, | |
88 | PE20_PF_SD1_D2, | |
89 | PE21_PF_SD1_D3, | |
90 | PE22_PF_SD1_CMD, | |
91 | PE23_PF_SD1_CLK, | |
92 | SD1_EN_GPIO | GPIO_GPIO | GPIO_OUT, | |
96cf4239 FE |
93 | /* OTG */ |
94 | OTG_PHY_RESET_GPIO | GPIO_GPIO | GPIO_OUT, | |
95 | PC7_PF_USBOTG_DATA5, | |
96 | PC8_PF_USBOTG_DATA6, | |
97 | PC9_PF_USBOTG_DATA0, | |
98 | PC10_PF_USBOTG_DATA2, | |
99 | PC11_PF_USBOTG_DATA1, | |
100 | PC12_PF_USBOTG_DATA4, | |
101 | PC13_PF_USBOTG_DATA3, | |
102 | PE0_PF_USBOTG_NXT, | |
103 | PE1_PF_USBOTG_STP, | |
104 | PE2_PF_USBOTG_DIR, | |
105 | PE24_PF_USBOTG_CLK, | |
106 | PE25_PF_USBOTG_DATA7, | |
1abcb4cc FE |
107 | /* CSPI1 */ |
108 | PD31_PF_CSPI1_MOSI, | |
109 | PD30_PF_CSPI1_MISO, | |
110 | PD29_PF_CSPI1_SCLK, | |
111 | PD25_PF_CSPI1_RDY, | |
112 | SPI1_SS0 | GPIO_GPIO | GPIO_OUT, | |
c67a3e09 FE |
113 | /* CSPI2 */ |
114 | PD22_PF_CSPI2_SCLK, | |
115 | PD23_PF_CSPI2_MISO, | |
116 | PD24_PF_CSPI2_MOSI, | |
aec250dc | 117 | SPI2_SS0 | GPIO_GPIO | GPIO_OUT, |
5885f036 FE |
118 | /* I2C1 */ |
119 | PD17_PF_I2C_DATA, | |
120 | PD18_PF_I2C_CLK, | |
aec250dc FE |
121 | /* PMIC INT */ |
122 | PMIC_INT | GPIO_GPIO | GPIO_IN, | |
1abcb4cc FE |
123 | /* LCD */ |
124 | PA5_PF_LSCLK, | |
125 | PA6_PF_LD0, | |
126 | PA7_PF_LD1, | |
127 | PA8_PF_LD2, | |
128 | PA9_PF_LD3, | |
129 | PA10_PF_LD4, | |
130 | PA11_PF_LD5, | |
131 | PA12_PF_LD6, | |
132 | PA13_PF_LD7, | |
133 | PA14_PF_LD8, | |
134 | PA15_PF_LD9, | |
135 | PA16_PF_LD10, | |
136 | PA17_PF_LD11, | |
137 | PA18_PF_LD12, | |
138 | PA19_PF_LD13, | |
139 | PA20_PF_LD14, | |
140 | PA21_PF_LD15, | |
141 | PA22_PF_LD16, | |
142 | PA23_PF_LD17, | |
143 | PA28_PF_HSYNC, | |
144 | PA29_PF_VSYNC, | |
145 | PA30_PF_CONTRAST, | |
146 | LCD_ENABLE | GPIO_GPIO | GPIO_OUT, | |
147 | LCD_RESET | GPIO_GPIO | GPIO_OUT, | |
4c11c286 FE |
148 | /* CSI */ |
149 | PB10_PF_CSI_D0, | |
150 | PB11_PF_CSI_D1, | |
151 | PB12_PF_CSI_D2, | |
152 | PB13_PF_CSI_D3, | |
153 | PB14_PF_CSI_D4, | |
154 | PB15_PF_CSI_MCLK, | |
155 | PB16_PF_CSI_PIXCLK, | |
156 | PB17_PF_CSI_D5, | |
157 | PB18_PF_CSI_D6, | |
158 | PB19_PF_CSI_D7, | |
159 | PB20_PF_CSI_VSYNC, | |
160 | PB21_PF_CSI_HSYNC, | |
161 | CSI_PWRDWN | GPIO_GPIO | GPIO_OUT, | |
162 | CSI_RESET | GPIO_GPIO | GPIO_OUT, | |
163 | }; | |
164 | ||
165 | static struct gpio mx27_3ds_camera_gpios[] = { | |
166 | { CSI_PWRDWN, GPIOF_OUT_INIT_HIGH, "camera-power" }, | |
167 | { CSI_RESET, GPIOF_OUT_INIT_HIGH, "camera-reset" }, | |
ec9be0de FE |
168 | }; |
169 | ||
d5dac4a6 | 170 | static const struct imxuart_platform_data uart_pdata __initconst = { |
ec9be0de FE |
171 | .flags = IMXUART_HAVE_RTSCTS, |
172 | }; | |
173 | ||
3fac6cf3 RP |
174 | /* |
175 | * Matrix keyboard | |
176 | */ | |
177 | ||
178 | static const uint32_t mx27_3ds_keymap[] = { | |
179 | KEY(0, 0, KEY_UP), | |
180 | KEY(0, 1, KEY_DOWN), | |
181 | KEY(1, 0, KEY_RIGHT), | |
182 | KEY(1, 1, KEY_LEFT), | |
183 | KEY(1, 2, KEY_ENTER), | |
184 | KEY(2, 0, KEY_F6), | |
185 | KEY(2, 1, KEY_F8), | |
186 | KEY(2, 2, KEY_F9), | |
187 | KEY(2, 3, KEY_F10), | |
188 | }; | |
189 | ||
3f880141 | 190 | static const struct matrix_keymap_data mx27_3ds_keymap_data __initconst = { |
3fac6cf3 RP |
191 | .keymap = mx27_3ds_keymap, |
192 | .keymap_size = ARRAY_SIZE(mx27_3ds_keymap), | |
193 | }; | |
194 | ||
b5ec73eb RP |
195 | static int mx27_3ds_sdhc1_init(struct device *dev, irq_handler_t detect_irq, |
196 | void *data) | |
197 | { | |
c084473d FE |
198 | return request_irq(gpio_to_irq(SD1_CD), detect_irq, |
199 | IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, "sdhc1-card-detect", data); | |
b5ec73eb RP |
200 | } |
201 | ||
202 | static void mx27_3ds_sdhc1_exit(struct device *dev, void *data) | |
203 | { | |
c084473d | 204 | free_irq(gpio_to_irq(SD1_CD), data); |
b5ec73eb RP |
205 | } |
206 | ||
9d3d945a | 207 | static const struct imxmmc_platform_data sdhc1_pdata __initconst = { |
b5ec73eb RP |
208 | .init = mx27_3ds_sdhc1_init, |
209 | .exit = mx27_3ds_sdhc1_exit, | |
210 | }; | |
211 | ||
212 | static void mx27_3ds_sdhc1_enable_level_translator(void) | |
213 | { | |
214 | /* Turn on TXB0108 OE pin */ | |
215 | gpio_request(SD1_EN_GPIO, "sd1_enable"); | |
216 | gpio_direction_output(SD1_EN_GPIO, 1); | |
217 | } | |
218 | ||
96cf4239 FE |
219 | |
220 | static int otg_phy_init(void) | |
221 | { | |
222 | gpio_request(OTG_PHY_RESET_GPIO, "usb-otg-reset"); | |
223 | gpio_direction_output(OTG_PHY_RESET_GPIO, 0); | |
224 | mdelay(1); | |
225 | gpio_set_value(OTG_PHY_RESET_GPIO, 1); | |
226 | return 0; | |
227 | } | |
228 | ||
4bd597b6 SH |
229 | static int mx27_3ds_otg_init(struct platform_device *pdev) |
230 | { | |
231 | return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI); | |
232 | } | |
96cf4239 FE |
233 | |
234 | static struct mxc_usbh_platform_data otg_pdata __initdata = { | |
4bd597b6 | 235 | .init = mx27_3ds_otg_init, |
96cf4239 | 236 | .portsc = MXC_EHCI_MODE_ULPI, |
96cf4239 | 237 | }; |
96cf4239 FE |
238 | |
239 | static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { | |
240 | .operating_mode = FSL_USB2_DR_DEVICE, | |
241 | .phy_mode = FSL_USB2_PHY_ULPI, | |
242 | }; | |
243 | ||
33a264dd | 244 | static bool otg_mode_host __initdata; |
96cf4239 FE |
245 | |
246 | static int __init mx27_3ds_otg_mode(char *options) | |
247 | { | |
248 | if (!strcmp(options, "host")) | |
33a264dd | 249 | otg_mode_host = true; |
96cf4239 | 250 | else if (!strcmp(options, "device")) |
33a264dd | 251 | otg_mode_host = false; |
96cf4239 FE |
252 | else |
253 | pr_info("otg_mode neither \"host\" nor \"device\". " | |
254 | "Defaulting to device\n"); | |
33a264dd | 255 | return 1; |
96cf4239 FE |
256 | } |
257 | __setup("otg_mode=", mx27_3ds_otg_mode); | |
258 | ||
c67a3e09 | 259 | /* Regulators */ |
aec250dc FE |
260 | static struct regulator_init_data gpo_init = { |
261 | .constraints = { | |
262 | .boot_on = 1, | |
263 | .always_on = 1, | |
264 | } | |
265 | }; | |
266 | ||
c67a3e09 | 267 | static struct regulator_consumer_supply vmmc1_consumers[] = { |
0556dc34 | 268 | REGULATOR_SUPPLY("vcore", "spi0.0"), |
4c11c286 | 269 | REGULATOR_SUPPLY("cmos_2v8", "soc-camera-pdrv.0"), |
c67a3e09 FE |
270 | }; |
271 | ||
272 | static struct regulator_init_data vmmc1_init = { | |
273 | .constraints = { | |
274 | .min_uV = 2800000, | |
275 | .max_uV = 2800000, | |
aec250dc FE |
276 | .apply_uV = 1, |
277 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | | |
278 | REGULATOR_CHANGE_STATUS, | |
c67a3e09 FE |
279 | }, |
280 | .num_consumer_supplies = ARRAY_SIZE(vmmc1_consumers), | |
281 | .consumer_supplies = vmmc1_consumers, | |
282 | }; | |
283 | ||
284 | static struct regulator_consumer_supply vgen_consumers[] = { | |
0556dc34 | 285 | REGULATOR_SUPPLY("vdd", "spi0.0"), |
c67a3e09 FE |
286 | }; |
287 | ||
288 | static struct regulator_init_data vgen_init = { | |
289 | .constraints = { | |
290 | .min_uV = 1800000, | |
291 | .max_uV = 1800000, | |
292 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, | |
293 | }, | |
294 | .num_consumer_supplies = ARRAY_SIZE(vgen_consumers), | |
295 | .consumer_supplies = vgen_consumers, | |
296 | }; | |
297 | ||
4c11c286 FE |
298 | static struct regulator_consumer_supply vvib_consumers[] = { |
299 | REGULATOR_SUPPLY("cmos_vcore", "soc-camera-pdrv.0"), | |
300 | }; | |
301 | ||
302 | static struct regulator_init_data vvib_init = { | |
303 | .constraints = { | |
304 | .min_uV = 1300000, | |
305 | .max_uV = 1300000, | |
306 | .apply_uV = 1, | |
307 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | | |
308 | REGULATOR_CHANGE_STATUS, | |
309 | }, | |
310 | .num_consumer_supplies = ARRAY_SIZE(vvib_consumers), | |
311 | .consumer_supplies = vvib_consumers, | |
312 | }; | |
313 | ||
5836372e | 314 | static struct mc13xxx_regulator_init_data mx27_3ds_regulators[] = { |
c67a3e09 | 315 | { |
074cee92 | 316 | .id = MC13783_REG_VMMC1, |
c67a3e09 FE |
317 | .init_data = &vmmc1_init, |
318 | }, { | |
074cee92 | 319 | .id = MC13783_REG_VGEN, |
c67a3e09 | 320 | .init_data = &vgen_init, |
aec250dc FE |
321 | }, { |
322 | .id = MC13783_REG_GPO1, /* Turn on 1.8V */ | |
323 | .init_data = &gpo_init, | |
324 | }, { | |
325 | .id = MC13783_REG_GPO3, /* Turn on 3.3V */ | |
326 | .init_data = &gpo_init, | |
4c11c286 FE |
327 | }, { |
328 | .id = MC13783_REG_VVIB, /* Power OV2640 */ | |
329 | .init_data = &vvib_init, | |
c67a3e09 FE |
330 | }, |
331 | }; | |
332 | ||
333 | /* MC13783 */ | |
4ec1b54c AS |
334 | static struct mc13xxx_platform_data mc13783_pdata = { |
335 | .regulators = { | |
336 | .regulators = mx27_3ds_regulators, | |
337 | .num_regulators = ARRAY_SIZE(mx27_3ds_regulators), | |
338 | ||
339 | }, | |
46621ebb | 340 | .flags = MC13XXX_USE_TOUCHSCREEN | MC13XXX_USE_RTC, |
c67a3e09 FE |
341 | }; |
342 | ||
343 | /* SPI */ | |
1abcb4cc FE |
344 | static int spi1_chipselect[] = {SPI1_SS0}; |
345 | ||
346 | static const struct spi_imx_master spi1_pdata __initconst = { | |
347 | .chipselect = spi1_chipselect, | |
348 | .num_chipselect = ARRAY_SIZE(spi1_chipselect), | |
349 | }; | |
350 | ||
6d2385ab | 351 | static int spi2_chipselect[] = {SPI2_SS0}; |
c67a3e09 FE |
352 | |
353 | static const struct spi_imx_master spi2_pdata __initconst = { | |
6d2385ab FE |
354 | .chipselect = spi2_chipselect, |
355 | .num_chipselect = ARRAY_SIZE(spi2_chipselect), | |
c67a3e09 FE |
356 | }; |
357 | ||
4c11c286 FE |
358 | static int mx27_3ds_camera_power(struct device *dev, int on) |
359 | { | |
360 | /* enable or disable the camera */ | |
361 | pr_debug("%s: %s the camera\n", __func__, on ? "ENABLE" : "DISABLE"); | |
362 | gpio_set_value(CSI_PWRDWN, on ? 0 : 1); | |
363 | ||
364 | if (!on) | |
365 | goto out; | |
366 | ||
367 | /* If enabled, give a reset impulse */ | |
368 | gpio_set_value(CSI_RESET, 0); | |
369 | msleep(20); | |
370 | gpio_set_value(CSI_RESET, 1); | |
371 | msleep(100); | |
372 | ||
373 | out: | |
374 | return 0; | |
375 | } | |
376 | ||
377 | static struct i2c_board_info mx27_3ds_i2c_camera = { | |
378 | I2C_BOARD_INFO("ov2640", 0x30), | |
379 | }; | |
380 | ||
381 | static struct regulator_bulk_data mx27_3ds_camera_regs[] = { | |
382 | { .supply = "cmos_vcore" }, | |
383 | { .supply = "cmos_2v8" }, | |
384 | }; | |
385 | ||
386 | static struct soc_camera_link iclink_ov2640 = { | |
387 | .bus_id = 0, | |
388 | .board_info = &mx27_3ds_i2c_camera, | |
389 | .i2c_adapter_id = 0, | |
390 | .power = mx27_3ds_camera_power, | |
391 | .regulators = mx27_3ds_camera_regs, | |
392 | .num_regulators = ARRAY_SIZE(mx27_3ds_camera_regs), | |
393 | }; | |
394 | ||
395 | static struct platform_device mx27_3ds_ov2640 = { | |
396 | .name = "soc-camera-pdrv", | |
397 | .id = 0, | |
398 | .dev = { | |
399 | .platform_data = &iclink_ov2640, | |
400 | }, | |
401 | }; | |
402 | ||
1abcb4cc FE |
403 | static struct imx_fb_videomode mx27_3ds_modes[] = { |
404 | { /* 480x640 @ 60 Hz */ | |
405 | .mode = { | |
406 | .name = "Epson-VGA", | |
407 | .refresh = 60, | |
408 | .xres = 480, | |
409 | .yres = 640, | |
410 | .pixclock = 41701, | |
411 | .left_margin = 20, | |
412 | .right_margin = 41, | |
413 | .upper_margin = 10, | |
414 | .lower_margin = 5, | |
415 | .hsync_len = 20, | |
416 | .vsync_len = 10, | |
417 | .sync = FB_SYNC_OE_ACT_HIGH | | |
418 | FB_SYNC_CLK_INVERT, | |
419 | .vmode = FB_VMODE_NONINTERLACED, | |
420 | .flag = 0, | |
421 | }, | |
422 | .bpp = 16, | |
423 | .pcr = 0xFAC08B82, | |
424 | }, | |
425 | }; | |
426 | ||
427 | static const struct imx_fb_platform_data mx27_3ds_fb_data __initconst = { | |
428 | .mode = mx27_3ds_modes, | |
429 | .num_modes = ARRAY_SIZE(mx27_3ds_modes), | |
430 | .pwmr = 0x00A903FF, | |
431 | .lscr1 = 0x00120300, | |
432 | .dmacr = 0x00020010, | |
433 | }; | |
434 | ||
435 | /* LCD */ | |
436 | static struct l4f00242t03_pdata mx27_3ds_lcd_pdata = { | |
437 | .reset_gpio = LCD_RESET, | |
438 | .data_enable_gpio = LCD_ENABLE, | |
1abcb4cc FE |
439 | }; |
440 | ||
c67a3e09 FE |
441 | static struct spi_board_info mx27_3ds_spi_devs[] __initdata = { |
442 | { | |
443 | .modalias = "mc13783", | |
444 | .max_speed_hz = 1000000, | |
445 | .bus_num = 1, | |
446 | .chip_select = 0, /* SS0 */ | |
447 | .platform_data = &mc13783_pdata, | |
e309fb18 | 448 | .irq = IMX_GPIO_TO_IRQ(PMIC_INT), |
c67a3e09 | 449 | .mode = SPI_CS_HIGH, |
1abcb4cc FE |
450 | }, { |
451 | .modalias = "l4f00242t03", | |
452 | .max_speed_hz = 5000000, | |
453 | .bus_num = 0, | |
454 | .chip_select = 0, /* SS0 */ | |
455 | .platform_data = &mx27_3ds_lcd_pdata, | |
c67a3e09 FE |
456 | }, |
457 | }; | |
458 | ||
4c11c286 FE |
459 | static struct platform_device *devices[] __initdata = { |
460 | &mx27_3ds_ov2640, | |
461 | }; | |
462 | ||
463 | static const struct mx2_camera_platform_data mx27_3ds_cam_pdata __initconst = { | |
464 | .clk = 26000000, | |
465 | }; | |
466 | ||
5885f036 FE |
467 | static const struct imxi2c_platform_data mx27_3ds_i2c0_data __initconst = { |
468 | .bitrate = 100000, | |
469 | }; | |
96cf4239 | 470 | |
ec9be0de FE |
471 | static void __init mx27pdk_init(void) |
472 | { | |
4c11c286 | 473 | int ret; |
b78d8e59 SG |
474 | imx27_soc_init(); |
475 | ||
ec9be0de FE |
476 | mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins), |
477 | "mx27pdk"); | |
b5ec73eb | 478 | mx27_3ds_sdhc1_enable_level_translator(); |
d5dac4a6 | 479 | imx27_add_imx_uart0(&uart_pdata); |
6bd96f3c | 480 | imx27_add_fec(NULL); |
3f880141 | 481 | imx27_add_imx_keypad(&mx27_3ds_keymap_data); |
9d3d945a | 482 | imx27_add_mxc_mmc(0, &sdhc1_pdata); |
8be9252f | 483 | imx27_add_imx2_wdt(NULL); |
96cf4239 | 484 | otg_phy_init(); |
48f6b099 | 485 | |
96cf4239 | 486 | if (otg_mode_host) { |
48f6b099 SH |
487 | otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | |
488 | ULPI_OTG_DRVVBUS_EXT); | |
96cf4239 | 489 | |
48f6b099 SH |
490 | if (otg_pdata.otg) |
491 | imx27_add_mxc_ehci_otg(&otg_pdata); | |
96cf4239 | 492 | } |
48f6b099 | 493 | |
96cf4239 FE |
494 | if (!otg_mode_host) |
495 | imx27_add_fsl_usb2_udc(&otg_device_pdata); | |
496 | ||
c67a3e09 | 497 | imx27_add_spi_imx1(&spi2_pdata); |
1abcb4cc | 498 | imx27_add_spi_imx0(&spi1_pdata); |
c67a3e09 FE |
499 | spi_register_board_info(mx27_3ds_spi_devs, |
500 | ARRAY_SIZE(mx27_3ds_spi_devs)); | |
92cb33f1 FE |
501 | |
502 | if (mxc_expio_init(MX27_CS5_BASE_ADDR, EXPIO_PARENT_INT)) | |
503 | pr_warn("Init of the debugboard failed, all devices on the debugboard are unusable.\n"); | |
5885f036 | 504 | imx27_add_imx_i2c(0, &mx27_3ds_i2c0_data); |
4c11c286 | 505 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
1abcb4cc | 506 | imx27_add_imx_fb(&mx27_3ds_fb_data); |
4c11c286 FE |
507 | |
508 | ret = gpio_request_array(mx27_3ds_camera_gpios, | |
509 | ARRAY_SIZE(mx27_3ds_camera_gpios)); | |
510 | if (ret) { | |
511 | pr_err("Failed to request camera gpios"); | |
512 | iclink_ov2640.power = NULL; | |
513 | } | |
514 | ||
515 | imx27_add_mx2_camera(&mx27_3ds_cam_pdata); | |
ec9be0de FE |
516 | } |
517 | ||
518 | static void __init mx27pdk_timer_init(void) | |
519 | { | |
520 | mx27_clocks_init(26000000); | |
521 | } | |
522 | ||
523 | static struct sys_timer mx27pdk_timer = { | |
524 | .init = mx27pdk_timer_init, | |
525 | }; | |
526 | ||
527 | MACHINE_START(MX27_3DS, "Freescale MX27PDK") | |
528 | /* maintainer: Freescale Semiconductor, Inc. */ | |
dc8f1907 | 529 | .atag_offset = 0x100, |
3dac2196 UKK |
530 | .map_io = mx27_map_io, |
531 | .init_early = imx27_init_early, | |
532 | .init_irq = mx27_init_irq, | |
ffa2ea3f | 533 | .handle_irq = imx27_handle_irq, |
3dac2196 UKK |
534 | .timer = &mx27pdk_timer, |
535 | .init_machine = mx27pdk_init, | |
65ea7884 | 536 | .restart = mxc_restart, |
ec9be0de | 537 | MACHINE_END |