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ec9be0de FE |
1 | /* |
2 | * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. | |
3 | * | |
4 | * Author: Fabio Estevam <fabio.estevam@freescale.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
ec9be0de FE |
15 | */ |
16 | ||
8fdca37a UKK |
17 | /* |
18 | * This machine is known as: | |
19 | * - i.MX27 3-Stack Development System | |
20 | * - i.MX27 Platform Development Kit (i.MX27 PDK) | |
21 | */ | |
22 | ||
ec9be0de FE |
23 | #include <linux/platform_device.h> |
24 | #include <linux/gpio.h> | |
b5ec73eb | 25 | #include <linux/irq.h> |
96cf4239 FE |
26 | #include <linux/usb/otg.h> |
27 | #include <linux/usb/ulpi.h> | |
28 | #include <linux/delay.h> | |
c67a3e09 FE |
29 | #include <linux/mfd/mc13783.h> |
30 | #include <linux/spi/spi.h> | |
31 | #include <linux/regulator/machine.h> | |
96cf4239 | 32 | |
ec9be0de FE |
33 | #include <asm/mach-types.h> |
34 | #include <asm/mach/arch.h> | |
35 | #include <asm/mach/time.h> | |
36 | #include <mach/hardware.h> | |
37 | #include <mach/common.h> | |
e835d88e | 38 | #include <mach/iomux-mx27.h> |
96cf4239 | 39 | #include <mach/ulpi.h> |
92cb33f1 FE |
40 | #include <mach/irqs.h> |
41 | #include <mach/3ds_debugboard.h> | |
ec9be0de | 42 | |
d5dac4a6 | 43 | #include "devices-imx27.h" |
ec9be0de | 44 | |
98618cfe FE |
45 | #define SD1_EN_GPIO IMX_GPIO_NR(2, 25) |
46 | #define OTG_PHY_RESET_GPIO IMX_GPIO_NR(2, 23) | |
47 | #define SPI2_SS0 IMX_GPIO_NR(4, 21) | |
48 | #define EXPIO_PARENT_INT gpio_to_irq(IMX_GPIO_NR(3, 28)) | |
aec250dc | 49 | #define PMIC_INT IMX_GPIO_NR(3, 14) |
c084473d | 50 | #define SD1_CD IMX_GPIO_NR(2, 26) |
b5ec73eb | 51 | |
6c80ee51 | 52 | static const int mx27pdk_pins[] __initconst = { |
ec9be0de FE |
53 | /* UART1 */ |
54 | PE12_PF_UART1_TXD, | |
55 | PE13_PF_UART1_RXD, | |
56 | PE14_PF_UART1_CTS, | |
57 | PE15_PF_UART1_RTS, | |
58 | /* FEC */ | |
59 | PD0_AIN_FEC_TXD0, | |
60 | PD1_AIN_FEC_TXD1, | |
61 | PD2_AIN_FEC_TXD2, | |
62 | PD3_AIN_FEC_TXD3, | |
63 | PD4_AOUT_FEC_RX_ER, | |
64 | PD5_AOUT_FEC_RXD1, | |
65 | PD6_AOUT_FEC_RXD2, | |
66 | PD7_AOUT_FEC_RXD3, | |
67 | PD8_AF_FEC_MDIO, | |
68 | PD9_AIN_FEC_MDC, | |
69 | PD10_AOUT_FEC_CRS, | |
70 | PD11_AOUT_FEC_TX_CLK, | |
71 | PD12_AOUT_FEC_RXD0, | |
72 | PD13_AOUT_FEC_RX_DV, | |
73 | PD14_AOUT_FEC_RX_CLK, | |
74 | PD15_AOUT_FEC_COL, | |
75 | PD16_AIN_FEC_TX_ER, | |
76 | PF23_AIN_FEC_TX_EN, | |
b5ec73eb RP |
77 | /* SDHC1 */ |
78 | PE18_PF_SD1_D0, | |
79 | PE19_PF_SD1_D1, | |
80 | PE20_PF_SD1_D2, | |
81 | PE21_PF_SD1_D3, | |
82 | PE22_PF_SD1_CMD, | |
83 | PE23_PF_SD1_CLK, | |
84 | SD1_EN_GPIO | GPIO_GPIO | GPIO_OUT, | |
96cf4239 FE |
85 | /* OTG */ |
86 | OTG_PHY_RESET_GPIO | GPIO_GPIO | GPIO_OUT, | |
87 | PC7_PF_USBOTG_DATA5, | |
88 | PC8_PF_USBOTG_DATA6, | |
89 | PC9_PF_USBOTG_DATA0, | |
90 | PC10_PF_USBOTG_DATA2, | |
91 | PC11_PF_USBOTG_DATA1, | |
92 | PC12_PF_USBOTG_DATA4, | |
93 | PC13_PF_USBOTG_DATA3, | |
94 | PE0_PF_USBOTG_NXT, | |
95 | PE1_PF_USBOTG_STP, | |
96 | PE2_PF_USBOTG_DIR, | |
97 | PE24_PF_USBOTG_CLK, | |
98 | PE25_PF_USBOTG_DATA7, | |
c67a3e09 FE |
99 | /* CSPI2 */ |
100 | PD22_PF_CSPI2_SCLK, | |
101 | PD23_PF_CSPI2_MISO, | |
102 | PD24_PF_CSPI2_MOSI, | |
aec250dc | 103 | SPI2_SS0 | GPIO_GPIO | GPIO_OUT, |
5885f036 FE |
104 | /* I2C1 */ |
105 | PD17_PF_I2C_DATA, | |
106 | PD18_PF_I2C_CLK, | |
aec250dc FE |
107 | /* PMIC INT */ |
108 | PMIC_INT | GPIO_GPIO | GPIO_IN, | |
ec9be0de FE |
109 | }; |
110 | ||
d5dac4a6 | 111 | static const struct imxuart_platform_data uart_pdata __initconst = { |
ec9be0de FE |
112 | .flags = IMXUART_HAVE_RTSCTS, |
113 | }; | |
114 | ||
3fac6cf3 RP |
115 | /* |
116 | * Matrix keyboard | |
117 | */ | |
118 | ||
119 | static const uint32_t mx27_3ds_keymap[] = { | |
120 | KEY(0, 0, KEY_UP), | |
121 | KEY(0, 1, KEY_DOWN), | |
122 | KEY(1, 0, KEY_RIGHT), | |
123 | KEY(1, 1, KEY_LEFT), | |
124 | KEY(1, 2, KEY_ENTER), | |
125 | KEY(2, 0, KEY_F6), | |
126 | KEY(2, 1, KEY_F8), | |
127 | KEY(2, 2, KEY_F9), | |
128 | KEY(2, 3, KEY_F10), | |
129 | }; | |
130 | ||
3f880141 | 131 | static const struct matrix_keymap_data mx27_3ds_keymap_data __initconst = { |
3fac6cf3 RP |
132 | .keymap = mx27_3ds_keymap, |
133 | .keymap_size = ARRAY_SIZE(mx27_3ds_keymap), | |
134 | }; | |
135 | ||
b5ec73eb RP |
136 | static int mx27_3ds_sdhc1_init(struct device *dev, irq_handler_t detect_irq, |
137 | void *data) | |
138 | { | |
c084473d FE |
139 | return request_irq(gpio_to_irq(SD1_CD), detect_irq, |
140 | IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, "sdhc1-card-detect", data); | |
b5ec73eb RP |
141 | } |
142 | ||
143 | static void mx27_3ds_sdhc1_exit(struct device *dev, void *data) | |
144 | { | |
c084473d | 145 | free_irq(gpio_to_irq(SD1_CD), data); |
b5ec73eb RP |
146 | } |
147 | ||
9d3d945a | 148 | static const struct imxmmc_platform_data sdhc1_pdata __initconst = { |
b5ec73eb RP |
149 | .init = mx27_3ds_sdhc1_init, |
150 | .exit = mx27_3ds_sdhc1_exit, | |
151 | }; | |
152 | ||
153 | static void mx27_3ds_sdhc1_enable_level_translator(void) | |
154 | { | |
155 | /* Turn on TXB0108 OE pin */ | |
156 | gpio_request(SD1_EN_GPIO, "sd1_enable"); | |
157 | gpio_direction_output(SD1_EN_GPIO, 1); | |
158 | } | |
159 | ||
96cf4239 FE |
160 | |
161 | static int otg_phy_init(void) | |
162 | { | |
163 | gpio_request(OTG_PHY_RESET_GPIO, "usb-otg-reset"); | |
164 | gpio_direction_output(OTG_PHY_RESET_GPIO, 0); | |
165 | mdelay(1); | |
166 | gpio_set_value(OTG_PHY_RESET_GPIO, 1); | |
167 | return 0; | |
168 | } | |
169 | ||
4bd597b6 SH |
170 | static int mx27_3ds_otg_init(struct platform_device *pdev) |
171 | { | |
172 | return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI); | |
173 | } | |
96cf4239 FE |
174 | |
175 | static struct mxc_usbh_platform_data otg_pdata __initdata = { | |
4bd597b6 | 176 | .init = mx27_3ds_otg_init, |
96cf4239 | 177 | .portsc = MXC_EHCI_MODE_ULPI, |
96cf4239 | 178 | }; |
96cf4239 FE |
179 | |
180 | static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { | |
181 | .operating_mode = FSL_USB2_DR_DEVICE, | |
182 | .phy_mode = FSL_USB2_PHY_ULPI, | |
183 | }; | |
184 | ||
185 | static int otg_mode_host; | |
186 | ||
187 | static int __init mx27_3ds_otg_mode(char *options) | |
188 | { | |
189 | if (!strcmp(options, "host")) | |
190 | otg_mode_host = 1; | |
191 | else if (!strcmp(options, "device")) | |
192 | otg_mode_host = 0; | |
193 | else | |
194 | pr_info("otg_mode neither \"host\" nor \"device\". " | |
195 | "Defaulting to device\n"); | |
196 | return 0; | |
197 | } | |
198 | __setup("otg_mode=", mx27_3ds_otg_mode); | |
199 | ||
c67a3e09 | 200 | /* Regulators */ |
aec250dc FE |
201 | static struct regulator_init_data gpo_init = { |
202 | .constraints = { | |
203 | .boot_on = 1, | |
204 | .always_on = 1, | |
205 | } | |
206 | }; | |
207 | ||
c67a3e09 FE |
208 | static struct regulator_consumer_supply vmmc1_consumers[] = { |
209 | REGULATOR_SUPPLY("lcd_2v8", NULL), | |
210 | }; | |
211 | ||
212 | static struct regulator_init_data vmmc1_init = { | |
213 | .constraints = { | |
214 | .min_uV = 2800000, | |
215 | .max_uV = 2800000, | |
aec250dc FE |
216 | .apply_uV = 1, |
217 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | | |
218 | REGULATOR_CHANGE_STATUS, | |
c67a3e09 FE |
219 | }, |
220 | .num_consumer_supplies = ARRAY_SIZE(vmmc1_consumers), | |
221 | .consumer_supplies = vmmc1_consumers, | |
222 | }; | |
223 | ||
224 | static struct regulator_consumer_supply vgen_consumers[] = { | |
225 | REGULATOR_SUPPLY("vdd_lcdio", NULL), | |
226 | }; | |
227 | ||
228 | static struct regulator_init_data vgen_init = { | |
229 | .constraints = { | |
230 | .min_uV = 1800000, | |
231 | .max_uV = 1800000, | |
232 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, | |
233 | }, | |
234 | .num_consumer_supplies = ARRAY_SIZE(vgen_consumers), | |
235 | .consumer_supplies = vgen_consumers, | |
236 | }; | |
237 | ||
5836372e | 238 | static struct mc13xxx_regulator_init_data mx27_3ds_regulators[] = { |
c67a3e09 | 239 | { |
074cee92 | 240 | .id = MC13783_REG_VMMC1, |
c67a3e09 FE |
241 | .init_data = &vmmc1_init, |
242 | }, { | |
074cee92 | 243 | .id = MC13783_REG_VGEN, |
c67a3e09 | 244 | .init_data = &vgen_init, |
aec250dc FE |
245 | }, { |
246 | .id = MC13783_REG_GPO1, /* Turn on 1.8V */ | |
247 | .init_data = &gpo_init, | |
248 | }, { | |
249 | .id = MC13783_REG_GPO3, /* Turn on 3.3V */ | |
250 | .init_data = &gpo_init, | |
c67a3e09 FE |
251 | }, |
252 | }; | |
253 | ||
254 | /* MC13783 */ | |
4ec1b54c AS |
255 | static struct mc13xxx_platform_data mc13783_pdata = { |
256 | .regulators = { | |
257 | .regulators = mx27_3ds_regulators, | |
258 | .num_regulators = ARRAY_SIZE(mx27_3ds_regulators), | |
259 | ||
260 | }, | |
261 | .flags = MC13783_USE_REGULATOR, | |
c67a3e09 FE |
262 | }; |
263 | ||
264 | /* SPI */ | |
6d2385ab | 265 | static int spi2_chipselect[] = {SPI2_SS0}; |
c67a3e09 FE |
266 | |
267 | static const struct spi_imx_master spi2_pdata __initconst = { | |
6d2385ab FE |
268 | .chipselect = spi2_chipselect, |
269 | .num_chipselect = ARRAY_SIZE(spi2_chipselect), | |
c67a3e09 FE |
270 | }; |
271 | ||
272 | static struct spi_board_info mx27_3ds_spi_devs[] __initdata = { | |
273 | { | |
274 | .modalias = "mc13783", | |
275 | .max_speed_hz = 1000000, | |
276 | .bus_num = 1, | |
277 | .chip_select = 0, /* SS0 */ | |
278 | .platform_data = &mc13783_pdata, | |
c084473d | 279 | .irq = gpio_to_irq(PMIC_INT), |
c67a3e09 FE |
280 | .mode = SPI_CS_HIGH, |
281 | }, | |
282 | }; | |
283 | ||
5885f036 FE |
284 | static const struct imxi2c_platform_data mx27_3ds_i2c0_data __initconst = { |
285 | .bitrate = 100000, | |
286 | }; | |
96cf4239 | 287 | |
ec9be0de FE |
288 | static void __init mx27pdk_init(void) |
289 | { | |
b78d8e59 SG |
290 | imx27_soc_init(); |
291 | ||
ec9be0de FE |
292 | mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins), |
293 | "mx27pdk"); | |
b5ec73eb | 294 | mx27_3ds_sdhc1_enable_level_translator(); |
d5dac4a6 | 295 | imx27_add_imx_uart0(&uart_pdata); |
6bd96f3c | 296 | imx27_add_fec(NULL); |
3f880141 | 297 | imx27_add_imx_keypad(&mx27_3ds_keymap_data); |
9d3d945a | 298 | imx27_add_mxc_mmc(0, &sdhc1_pdata); |
8be9252f | 299 | imx27_add_imx2_wdt(NULL); |
96cf4239 | 300 | otg_phy_init(); |
48f6b099 | 301 | |
96cf4239 | 302 | if (otg_mode_host) { |
48f6b099 SH |
303 | otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | |
304 | ULPI_OTG_DRVVBUS_EXT); | |
96cf4239 | 305 | |
48f6b099 SH |
306 | if (otg_pdata.otg) |
307 | imx27_add_mxc_ehci_otg(&otg_pdata); | |
96cf4239 | 308 | } |
48f6b099 | 309 | |
96cf4239 FE |
310 | if (!otg_mode_host) |
311 | imx27_add_fsl_usb2_udc(&otg_device_pdata); | |
312 | ||
c67a3e09 FE |
313 | imx27_add_spi_imx1(&spi2_pdata); |
314 | spi_register_board_info(mx27_3ds_spi_devs, | |
315 | ARRAY_SIZE(mx27_3ds_spi_devs)); | |
92cb33f1 FE |
316 | |
317 | if (mxc_expio_init(MX27_CS5_BASE_ADDR, EXPIO_PARENT_INT)) | |
318 | pr_warn("Init of the debugboard failed, all devices on the debugboard are unusable.\n"); | |
5885f036 | 319 | imx27_add_imx_i2c(0, &mx27_3ds_i2c0_data); |
ec9be0de FE |
320 | } |
321 | ||
322 | static void __init mx27pdk_timer_init(void) | |
323 | { | |
324 | mx27_clocks_init(26000000); | |
325 | } | |
326 | ||
327 | static struct sys_timer mx27pdk_timer = { | |
328 | .init = mx27pdk_timer_init, | |
329 | }; | |
330 | ||
331 | MACHINE_START(MX27_3DS, "Freescale MX27PDK") | |
332 | /* maintainer: Freescale Semiconductor, Inc. */ | |
3dac2196 UKK |
333 | .boot_params = MX27_PHYS_OFFSET + 0x100, |
334 | .map_io = mx27_map_io, | |
335 | .init_early = imx27_init_early, | |
336 | .init_irq = mx27_init_irq, | |
337 | .timer = &mx27pdk_timer, | |
338 | .init_machine = mx27pdk_init, | |
ec9be0de | 339 | MACHINE_END |