[deliverable/linux.git] / arch / arm / mach-imx / mach-mx27ads.c

/*
 *  Copyright (C) 2000 Deep Blue Solutions Ltd
 *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
 *  Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/map.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
#include <linux/i2c.h>
#include <linux/irq.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>
#include <mach/gpio.h>
#include <mach/imx-uart.h>
#include <mach/iomux-mx27.h>
#include <mach/mxc_nand.h>
#include <mach/i2c.h>
#include <mach/imxfb.h>
#include <mach/mmc.h>

#include "devices-imx27.h"
#include "devices.h"

/*
 * Base address of PBC controller, CS4
 */
#define PBC_BASE_ADDRESS        0xf4300000
#define PBC_REG_ADDR(offset)    (void __force __iomem *) \
		(PBC_BASE_ADDRESS + (offset))

/* When the PBC address connection is fixed in h/w, defined as 1 */
#define PBC_ADDR_SH             0

/* Offsets for the PBC Controller register */
/*
 * PBC Board version register offset
 */
#define PBC_VERSION_REG         PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH)
/*
 * PBC Board control register 1 set address.
 */
#define PBC_BCTRL1_SET_REG      PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH)
/*
 * PBC Board control register 1 clear address.
 */
#define PBC_BCTRL1_CLEAR_REG    PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH)

/* PBC Board Control Register 1 bit definitions */
#define PBC_BCTRL1_LCDON        0x0800	/* Enable the LCD */

/* to determine the correct external crystal reference */
#define CKIH_27MHZ_BIT_SET      (1 << 3)

static unsigned int mx27ads_pins[] = {
	/* UART0 */
	PE12_PF_UART1_TXD,
	PE13_PF_UART1_RXD,
	PE14_PF_UART1_CTS,
	PE15_PF_UART1_RTS,
	/* UART1 */
	PE3_PF_UART2_CTS,
	PE4_PF_UART2_RTS,
	PE6_PF_UART2_TXD,
	PE7_PF_UART2_RXD,
	/* UART2 */
	PE8_PF_UART3_TXD,
	PE9_PF_UART3_RXD,
	PE10_PF_UART3_CTS,
	PE11_PF_UART3_RTS,
	/* UART3 */
	PB26_AF_UART4_RTS,
	PB28_AF_UART4_TXD,
	PB29_AF_UART4_CTS,
	PB31_AF_UART4_RXD,
	/* UART4 */
	PB18_AF_UART5_TXD,
	PB19_AF_UART5_RXD,
	PB20_AF_UART5_CTS,
	PB21_AF_UART5_RTS,
	/* UART5 */
	PB10_AF_UART6_TXD,
	PB12_AF_UART6_CTS,
	PB11_AF_UART6_RXD,
	PB13_AF_UART6_RTS,
	/* FEC */
	PD0_AIN_FEC_TXD0,
	PD1_AIN_FEC_TXD1,
	PD2_AIN_FEC_TXD2,
	PD3_AIN_FEC_TXD3,
	PD4_AOUT_FEC_RX_ER,
	PD5_AOUT_FEC_RXD1,
	PD6_AOUT_FEC_RXD2,
	PD7_AOUT_FEC_RXD3,
	PD8_AF_FEC_MDIO,
	PD9_AIN_FEC_MDC,
	PD10_AOUT_FEC_CRS,
	PD11_AOUT_FEC_TX_CLK,
	PD12_AOUT_FEC_RXD0,
	PD13_AOUT_FEC_RX_DV,
	PD14_AOUT_FEC_RX_CLK,
	PD15_AOUT_FEC_COL,
	PD16_AIN_FEC_TX_ER,
	PF23_AIN_FEC_TX_EN,
	/* I2C2 */
	PC5_PF_I2C2_SDA,
	PC6_PF_I2C2_SCL,
	/* FB */
	PA5_PF_LSCLK,
	PA6_PF_LD0,
	PA7_PF_LD1,
	PA8_PF_LD2,
	PA9_PF_LD3,
	PA10_PF_LD4,
	PA11_PF_LD5,
	PA12_PF_LD6,
	PA13_PF_LD7,
	PA14_PF_LD8,
	PA15_PF_LD9,
	PA16_PF_LD10,
	PA17_PF_LD11,
	PA18_PF_LD12,
	PA19_PF_LD13,
	PA20_PF_LD14,
	PA21_PF_LD15,
	PA22_PF_LD16,
	PA23_PF_LD17,
	PA24_PF_REV,
	PA25_PF_CLS,
	PA26_PF_PS,
	PA27_PF_SPL_SPR,
	PA28_PF_HSYNC,
	PA29_PF_VSYNC,
	PA30_PF_CONTRAST,
	PA31_PF_OE_ACD,
	/* OWIRE */
	PE16_AF_OWIRE,
	/* SDHC1*/
	PE18_PF_SD1_D0,
	PE19_PF_SD1_D1,
	PE20_PF_SD1_D2,
	PE21_PF_SD1_D3,
	PE22_PF_SD1_CMD,
	PE23_PF_SD1_CLK,
	/* SDHC2*/
	PB4_PF_SD2_D0,
	PB5_PF_SD2_D1,
	PB6_PF_SD2_D2,
	PB7_PF_SD2_D3,
	PB8_PF_SD2_CMD,
	PB9_PF_SD2_CLK,
};

static const struct mxc_nand_platform_data
mx27ads_nand_board_info __initconst = {
	.width = 1,
	.hw_ecc = 1,
};

/* ADS's NOR flash */
static struct physmap_flash_data mx27ads_flash_data = {
	.width = 2,
};

static struct resource mx27ads_flash_resource = {
	.start = 0xc0000000,
	.end = 0xc0000000 + 0x02000000 - 1,
	.flags = IORESOURCE_MEM,

};

static struct platform_device mx27ads_nor_mtd_device = {
	.name = "physmap-flash",
	.id = 0,
	.dev = {
		.platform_data = &mx27ads_flash_data,
	},
	.num_resources = 1,
	.resource = &mx27ads_flash_resource,
};

static struct imxi2c_platform_data mx27ads_i2c_data = {
	.bitrate = 100000,
};

static struct i2c_board_info mx27ads_i2c_devices[] = {
};

void lcd_power(int on)
{
	if (on)
		__raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_SET_REG);
	else
		__raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_CLEAR_REG);
}

static struct imx_fb_videomode mx27ads_modes[] = {
	{
		.mode = {
			.name		= "Sharp-LQ035Q7",
			.refresh	= 60,
			.xres		= 240,
			.yres		= 320,
			.pixclock	= 188679, /* in ps (5.3MHz) */
			.hsync_len	= 1,
			.left_margin	= 9,
			.right_margin	= 16,
			.vsync_len	= 1,
			.upper_margin	= 7,
			.lower_margin	= 9,
		},
		.bpp		= 16,
		.pcr		= 0xFB008BC0,
	},
};

static struct imx_fb_platform_data mx27ads_fb_data = {
	.mode = mx27ads_modes,
	.num_modes = ARRAY_SIZE(mx27ads_modes),

	/*
	 * - HSYNC active high
	 * - VSYNC active high
	 * - clk notenabled while idle
	 * - clock inverted
	 * - data not inverted
	 * - data enable low active
	 * - enable sharp mode
	 */
	.pwmr		= 0x00A903FF,
	.lscr1		= 0x00120300,
	.dmacr		= 0x00020010,

	.lcd_power	= lcd_power,
};

static int mx27ads_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
			      void *data)
{
	return request_irq(IRQ_GPIOE(21), detect_irq, IRQF_TRIGGER_RISING,
			   "sdhc1-card-detect", data);
}

static int mx27ads_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
			      void *data)
{
	return request_irq(IRQ_GPIOB(7), detect_irq, IRQF_TRIGGER_RISING,
			   "sdhc2-card-detect", data);
}

static void mx27ads_sdhc1_exit(struct device *dev, void *data)
{
	free_irq(IRQ_GPIOE(21), data);
}

static void mx27ads_sdhc2_exit(struct device *dev, void *data)
{
	free_irq(IRQ_GPIOB(7), data);
}

static struct imxmmc_platform_data sdhc1_pdata = {
	.init = mx27ads_sdhc1_init,
	.exit = mx27ads_sdhc1_exit,
};

static struct imxmmc_platform_data sdhc2_pdata = {
	.init = mx27ads_sdhc2_init,
	.exit = mx27ads_sdhc2_exit,
};

static struct platform_device *platform_devices[] __initdata = {
	&mx27ads_nor_mtd_device,
	&mxc_fec_device,
	&mxc_w1_master_device,
};

static struct imxuart_platform_data uart_pdata[] = {
	{
		.flags = IMXUART_HAVE_RTSCTS,
	}, {
		.flags = IMXUART_HAVE_RTSCTS,
	}, {
		.flags = IMXUART_HAVE_RTSCTS,
	}, {
		.flags = IMXUART_HAVE_RTSCTS,
	}, {
		.flags = IMXUART_HAVE_RTSCTS,
	}, {
		.flags = IMXUART_HAVE_RTSCTS,
	},
};

static void __init mx27ads_board_init(void)
{
	mxc_gpio_setup_multiple_pins(mx27ads_pins, ARRAY_SIZE(mx27ads_pins),
			"mx27ads");

	mxc_register_device(&imx2x_uart_device0, &uart_pdata[0]);
	mxc_register_device(&imx2x_uart_device1, &uart_pdata[1]);
	mxc_register_device(&imx2x_uart_device2, &uart_pdata[2]);
	mxc_register_device(&imx2x_uart_device3, &uart_pdata[3]);
	mxc_register_device(&imx2x_uart_device4, &uart_pdata[4]);
	mxc_register_device(&imx2x_uart_device5, &uart_pdata[5]);
	imx27_add_mxc_nand(&mx27ads_nand_board_info);

	/* only the i2c master 1 is used on this CPU card */
	i2c_register_board_info(1, mx27ads_i2c_devices,
				ARRAY_SIZE(mx27ads_i2c_devices));
	mxc_register_device(&mxc_i2c_device1, &mx27ads_i2c_data);
	mxc_register_device(&mxc_fb_device, &mx27ads_fb_data);
	mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata);
	mxc_register_device(&mxc_sdhc_device1, &sdhc2_pdata);

	platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
}

static void __init mx27ads_timer_init(void)
{
	unsigned long fref = 26000000;

	if ((__raw_readw(PBC_VERSION_REG) & CKIH_27MHZ_BIT_SET) == 0)
		fref = 27000000;

	mx27_clocks_init(fref);
}

static struct sys_timer mx27ads_timer = {
	.init	= mx27ads_timer_init,
};

static struct map_desc mx27ads_io_desc[] __initdata = {
	{
		.virtual = PBC_BASE_ADDRESS,
		.pfn = __phys_to_pfn(MX27_CS4_BASE_ADDR),
		.length = SZ_1M,
		.type = MT_DEVICE,
	},
};

static void __init mx27ads_map_io(void)
{
	mx27_map_io();
	iotable_init(mx27ads_io_desc, ARRAY_SIZE(mx27ads_io_desc));
}

MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
	/* maintainer: Freescale Semiconductor, Inc. */
	.phys_io        = MX27_AIPI_BASE_ADDR,
	.io_pg_offst    = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
	.boot_params    = MX27_PHYS_OFFSET + 0x100,
	.map_io         = mx27ads_map_io,
	.init_irq       = mx27_init_irq,
	.init_machine   = mx27ads_board_init,
	.timer          = &mx27ads_timer,
MACHINE_END
Commit	Line	Data
80eedae6 JB	1	/*
	2	* Copyright (C) 2000 Deep Blue Solutions Ltd
	3	* Copyright (C) 2002 Shane Nay (shane@minirl.com)
	4	* Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
80eedae6 JB	15	*/
	16
	17	#include <linux/platform_device.h>
	18	#include <linux/mtd/mtd.h>
	19	#include <linux/mtd/map.h>
	20	#include <linux/mtd/partitions.h>
	21	#include <linux/mtd/physmap.h>
c981214a	22	#include <linux/i2c.h>
60c24dc7	23	#include <linux/irq.h>
a09e64fb RK	24	#include <mach/common.h>
a09e64fb RK	25	#include <mach/hardware.h>
80eedae6 JB	26	#include <asm/mach-types.h>
	27	#include <asm/mach/arch.h>
	28	#include <asm/mach/time.h>
	29	#include <asm/mach/map.h>
a09e64fb RK	30	#include <mach/gpio.h>
a09e64fb RK	31	#include <mach/imx-uart.h>
e835d88e	32	#include <mach/iomux-mx27.h>
8d4fd258	33	#include <mach/mxc_nand.h>
c981214a	34	#include <mach/i2c.h>
11cda13d	35	#include <mach/imxfb.h>
60c24dc7	36	#include <mach/mmc.h>
80eedae6	37
0e7a29a8	38	#include "devices-imx27.h"
7e90534a SH	39	#include "devices.h"
7e90534a SH	40
1faeaab2 UKK	41	/*
	42	* Base address of PBC controller, CS4
	43	*/
	44	#define PBC_BASE_ADDRESS 0xf4300000
	45	#define PBC_REG_ADDR(offset) (void __force __iomem *) \
	46	(PBC_BASE_ADDRESS + (offset))
	47
	48	/* When the PBC address connection is fixed in h/w, defined as 1 */
	49	#define PBC_ADDR_SH 0
	50
	51	/* Offsets for the PBC Controller register */
	52	/*
	53	* PBC Board version register offset
	54	*/
	55	#define PBC_VERSION_REG PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH)
	56	/*
	57	* PBC Board control register 1 set address.
	58	*/
	59	#define PBC_BCTRL1_SET_REG PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH)
	60	/*
	61	* PBC Board control register 1 clear address.
	62	*/
	63	#define PBC_BCTRL1_CLEAR_REG PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH)
	64
	65	/* PBC Board Control Register 1 bit definitions */
	66	#define PBC_BCTRL1_LCDON 0x0800 /* Enable the LCD */
	67
	68	/* to determine the correct external crystal reference */
	69	#define CKIH_27MHZ_BIT_SET (1 << 3)
	70
c1a6f123 VB	71	static unsigned int mx27ads_pins[] = {
c1a6f123 VB	72	/* UART0 */
80eedae6 JB	73	PE12_PF_UART1_TXD,
	74	PE13_PF_UART1_RXD,
	75	PE14_PF_UART1_CTS,
c1a6f123 VB	76	PE15_PF_UART1_RTS,
c1a6f123 VB	77	/* UART1 */
80eedae6 JB	78	PE3_PF_UART2_CTS,
	79	PE4_PF_UART2_RTS,
	80	PE6_PF_UART2_TXD,
c1a6f123 VB	81	PE7_PF_UART2_RXD,
c1a6f123 VB	82	/* UART2 */
80eedae6 JB	83	PE8_PF_UART3_TXD,
	84	PE9_PF_UART3_RXD,
	85	PE10_PF_UART3_CTS,
c1a6f123 VB	86	PE11_PF_UART3_RTS,
c1a6f123 VB	87	/* UART3 */
80eedae6 JB	88	PB26_AF_UART4_RTS,
	89	PB28_AF_UART4_TXD,
	90	PB29_AF_UART4_CTS,
c1a6f123 VB	91	PB31_AF_UART4_RXD,
c1a6f123 VB	92	/* UART4 */
80eedae6 JB	93	PB18_AF_UART5_TXD,
	94	PB19_AF_UART5_RXD,
	95	PB20_AF_UART5_CTS,
c1a6f123 VB	96	PB21_AF_UART5_RTS,
c1a6f123 VB	97	/* UART5 */
80eedae6 JB	98	PB10_AF_UART6_TXD,
	99	PB12_AF_UART6_CTS,
	100	PB11_AF_UART6_RXD,
c1a6f123 VB	101	PB13_AF_UART6_RTS,
c1a6f123 VB	102	/* FEC */
80eedae6 JB	103	PD0_AIN_FEC_TXD0,
	104	PD1_AIN_FEC_TXD1,
	105	PD2_AIN_FEC_TXD2,
	106	PD3_AIN_FEC_TXD3,
	107	PD4_AOUT_FEC_RX_ER,
	108	PD5_AOUT_FEC_RXD1,
	109	PD6_AOUT_FEC_RXD2,
	110	PD7_AOUT_FEC_RXD3,
	111	PD8_AF_FEC_MDIO,
	112	PD9_AIN_FEC_MDC,
	113	PD10_AOUT_FEC_CRS,
	114	PD11_AOUT_FEC_TX_CLK,
	115	PD12_AOUT_FEC_RXD0,
	116	PD13_AOUT_FEC_RX_DV,
ccfe30a7	117	PD14_AOUT_FEC_RX_CLK,
80eedae6 JB	118	PD15_AOUT_FEC_COL,
80eedae6 JB	119	PD16_AIN_FEC_TX_ER,
c1a6f123	120	PF23_AIN_FEC_TX_EN,
c981214a VB	121	/* I2C2 */
	122	PC5_PF_I2C2_SDA,
	123	PC6_PF_I2C2_SCL,
11cda13d VB	124	/* FB */
	125	PA5_PF_LSCLK,
	126	PA6_PF_LD0,
	127	PA7_PF_LD1,
	128	PA8_PF_LD2,
	129	PA9_PF_LD3,
	130	PA10_PF_LD4,
	131	PA11_PF_LD5,
	132	PA12_PF_LD6,
	133	PA13_PF_LD7,
	134	PA14_PF_LD8,
	135	PA15_PF_LD9,
	136	PA16_PF_LD10,
	137	PA17_PF_LD11,
	138	PA18_PF_LD12,
	139	PA19_PF_LD13,
	140	PA20_PF_LD14,
	141	PA21_PF_LD15,
	142	PA22_PF_LD16,
	143	PA23_PF_LD17,
	144	PA24_PF_REV,
	145	PA25_PF_CLS,
	146	PA26_PF_PS,
	147	PA27_PF_SPL_SPR,
	148	PA28_PF_HSYNC,
	149	PA29_PF_VSYNC,
	150	PA30_PF_CONTRAST,
	151	PA31_PF_OE_ACD,
9366d8f6 VB	152	/* OWIRE */
9366d8f6 VB	153	PE16_AF_OWIRE,
60c24dc7 VB	154	/* SDHC1*/
	155	PE18_PF_SD1_D0,
	156	PE19_PF_SD1_D1,
	157	PE20_PF_SD1_D2,
	158	PE21_PF_SD1_D3,
	159	PE22_PF_SD1_CMD,
	160	PE23_PF_SD1_CLK,
	161	/* SDHC2*/
	162	PB4_PF_SD2_D0,
	163	PB5_PF_SD2_D1,
	164	PB6_PF_SD2_D2,
	165	PB7_PF_SD2_D3,
	166	PB8_PF_SD2_CMD,
	167	PB9_PF_SD2_CLK,
80eedae6 JB	168	};
80eedae6 JB	169
0e7a29a8 UKK	170	static const struct mxc_nand_platform_data
0e7a29a8 UKK	171	mx27ads_nand_board_info __initconst = {
8d4fd258 VB	172	.width = 1,
	173	.hw_ecc = 1,
	174	};
	175
c1a6f123 VB	176	/* ADS's NOR flash */
	177	static struct physmap_flash_data mx27ads_flash_data = {
	178	.width = 2,
	179	};
	180
	181	static struct resource mx27ads_flash_resource = {
	182	.start = 0xc0000000,
	183	.end = 0xc0000000 + 0x02000000 - 1,
	184	.flags = IORESOURCE_MEM,
	185
	186	};
	187
	188	static struct platform_device mx27ads_nor_mtd_device = {
	189	.name = "physmap-flash",
	190	.id = 0,
	191	.dev = {
	192	.platform_data = &mx27ads_flash_data,
	193	},
	194	.num_resources = 1,
	195	.resource = &mx27ads_flash_resource,
	196	};
	197
c981214a VB	198	static struct imxi2c_platform_data mx27ads_i2c_data = {
	199	.bitrate = 100000,
	200	};
	201
	202	static struct i2c_board_info mx27ads_i2c_devices[] = {
	203	};
	204
11cda13d VB	205	void lcd_power(int on)
	206	{
	207	if (on)
	208	__raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_SET_REG);
	209	else
	210	__raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_CLEAR_REG);
	211	}
	212
343684ff SH	213	static struct imx_fb_videomode mx27ads_modes[] = {
	214	{
	215	.mode = {
	216	.name = "Sharp-LQ035Q7",
	217	.refresh = 60,
	218	.xres = 240,
	219	.yres = 320,
	220	.pixclock = 188679, /* in ps (5.3MHz) */
	221	.hsync_len = 1,
	222	.left_margin = 9,
	223	.right_margin = 16,
	224	.vsync_len = 1,
	225	.upper_margin = 7,
	226	.lower_margin = 9,
	227	},
	228	.bpp = 16,
	229	.pcr = 0xFB008BC0,
	230	},
	231	};
11cda13d	232
343684ff SH	233	static struct imx_fb_platform_data mx27ads_fb_data = {
	234	.mode = mx27ads_modes,
	235	.num_modes = ARRAY_SIZE(mx27ads_modes),
11cda13d VB	236
	237	/*
	238	* - HSYNC active high
	239	* - VSYNC active high
	240	* - clk notenabled while idle
	241	* - clock inverted
	242	* - data not inverted
	243	* - data enable low active
	244	* - enable sharp mode
	245	*/
11cda13d VB	246	.pwmr = 0x00A903FF,
	247	.lscr1 = 0x00120300,
	248	.dmacr = 0x00020010,
	249
	250	.lcd_power = lcd_power,
	251	};
	252
60c24dc7 VB	253	static int mx27ads_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
	254	void *data)
	255	{
	256	return request_irq(IRQ_GPIOE(21), detect_irq, IRQF_TRIGGER_RISING,
	257	"sdhc1-card-detect", data);
	258	}
	259
	260	static int mx27ads_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
	261	void *data)
	262	{
	263	return request_irq(IRQ_GPIOB(7), detect_irq, IRQF_TRIGGER_RISING,
	264	"sdhc2-card-detect", data);
	265	}
	266
	267	static void mx27ads_sdhc1_exit(struct device dev, void data)
	268	{
	269	free_irq(IRQ_GPIOE(21), data);
	270	}
	271
	272	static void mx27ads_sdhc2_exit(struct device dev, void data)
	273	{
	274	free_irq(IRQ_GPIOB(7), data);
	275	}
	276
	277	static struct imxmmc_platform_data sdhc1_pdata = {
	278	.init = mx27ads_sdhc1_init,
	279	.exit = mx27ads_sdhc1_exit,
	280	};
	281
	282	static struct imxmmc_platform_data sdhc2_pdata = {
	283	.init = mx27ads_sdhc2_init,
	284	.exit = mx27ads_sdhc2_exit,
	285	};
	286
c1a6f123 VB	287	static struct platform_device *platform_devices[] __initdata = {
	288	&mx27ads_nor_mtd_device,
	289	&mxc_fec_device,
9366d8f6	290	&mxc_w1_master_device,
c1a6f123	291	};
80eedae6	292
80eedae6 JB	293	static struct imxuart_platform_data uart_pdata[] = {
80eedae6 JB	294	{
80eedae6 JB	295	.flags = IMXUART_HAVE_RTSCTS,
80eedae6 JB	296	}, {
80eedae6 JB	297	.flags = IMXUART_HAVE_RTSCTS,
80eedae6 JB	298	}, {
80eedae6 JB	299	.flags = IMXUART_HAVE_RTSCTS,
80eedae6 JB	300	}, {
80eedae6 JB	301	.flags = IMXUART_HAVE_RTSCTS,
80eedae6 JB	302	}, {
80eedae6 JB	303	.flags = IMXUART_HAVE_RTSCTS,
80eedae6 JB	304	}, {
80eedae6 JB	305	.flags = IMXUART_HAVE_RTSCTS,
	306	},
	307	};
	308
	309	static void __init mx27ads_board_init(void)
	310	{
c1a6f123 VB	311	mxc_gpio_setup_multiple_pins(mx27ads_pins, ARRAY_SIZE(mx27ads_pins),
c1a6f123 VB	312	"mx27ads");
80eedae6	313
551823e7 UKK	314	mxc_register_device(&imx2x_uart_device0, &uart_pdata[0]);
	315	mxc_register_device(&imx2x_uart_device1, &uart_pdata[1]);
	316	mxc_register_device(&imx2x_uart_device2, &uart_pdata[2]);
	317	mxc_register_device(&imx2x_uart_device3, &uart_pdata[3]);
	318	mxc_register_device(&imx2x_uart_device4, &uart_pdata[4]);
	319	mxc_register_device(&imx2x_uart_device5, &uart_pdata[5]);
0e7a29a8	320	imx27_add_mxc_nand(&mx27ads_nand_board_info);
c981214a VB	321
	322	/* only the i2c master 1 is used on this CPU card */
	323	i2c_register_board_info(1, mx27ads_i2c_devices,
	324	ARRAY_SIZE(mx27ads_i2c_devices));
	325	mxc_register_device(&mxc_i2c_device1, &mx27ads_i2c_data);
11cda13d	326	mxc_register_device(&mxc_fb_device, &mx27ads_fb_data);
60c24dc7 VB	327	mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata);
60c24dc7 VB	328	mxc_register_device(&mxc_sdhc_device1, &sdhc2_pdata);
80eedae6 JB	329
	330	platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
	331	}
	332
	333	static void __init mx27ads_timer_init(void)
	334	{
	335	unsigned long fref = 26000000;
	336
	337	if ((__raw_readw(PBC_VERSION_REG) & CKIH_27MHZ_BIT_SET) == 0)
	338	fref = 27000000;
	339
30c730f8	340	mx27_clocks_init(fref);
80eedae6 JB	341	}
80eedae6 JB	342
058b7a6f	343	static struct sys_timer mx27ads_timer = {
80eedae6 JB	344	.init = mx27ads_timer_init,
	345	};
	346
	347	static struct map_desc mx27ads_io_desc[] __initdata = {
	348	{
	349	.virtual = PBC_BASE_ADDRESS,
3f35d1f5	350	.pfn = __phys_to_pfn(MX27_CS4_BASE_ADDR),
80eedae6 JB	351	.length = SZ_1M,
	352	.type = MT_DEVICE,
	353	},
	354	};
	355
058b7a6f	356	static void __init mx27ads_map_io(void)
80eedae6	357	{
cd4a05f9	358	mx27_map_io();
80eedae6 JB	359	iotable_init(mx27ads_io_desc, ARRAY_SIZE(mx27ads_io_desc));
	360	}
	361
	362	MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
	363	/* maintainer: Freescale Semiconductor, Inc. */
3f35d1f5 UKK	364	.phys_io = MX27_AIPI_BASE_ADDR,
3f35d1f5 UKK	365	.io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
34101237	366	.boot_params = MX27_PHYS_OFFSET + 0x100,
80eedae6	367	.map_io = mx27ads_map_io,
c5aa0ad0	368	.init_irq = mx27_init_irq,
80eedae6 JB	369	.init_machine = mx27ads_board_init,
	370	.timer = &mx27ads_timer,
	371	MACHINE_END