[deliverable/linux.git] / arch / arm / mach-imx / mach-mx27ads.c

/*
 *  Copyright (C) 2000 Deep Blue Solutions Ltd
 *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
 *  Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/map.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
#include <linux/i2c.h>
#include <linux/irq.h>

#include <linux/regulator/fixed.h>
#include <linux/regulator/machine.h>

#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>

#include "common.h"
#include "devices-imx27.h"
#include "hardware.h"
#include "iomux-mx27.h"

/*
 * Base address of PBC controller, CS4
 */
#define PBC_BASE_ADDRESS        0xf4300000
#define PBC_REG_ADDR(offset)    (void __force __iomem *) \
		(PBC_BASE_ADDRESS + (offset))

/* When the PBC address connection is fixed in h/w, defined as 1 */
#define PBC_ADDR_SH             0

/* Offsets for the PBC Controller register */
/*
 * PBC Board version register offset
 */
#define PBC_VERSION_REG         PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH)
/*
 * PBC Board control register 1 set address.
 */
#define PBC_BCTRL1_SET_REG      PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH)
/*
 * PBC Board control register 1 clear address.
 */
#define PBC_BCTRL1_CLEAR_REG    PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH)

/* PBC Board Control Register 1 bit definitions */
#define PBC_BCTRL1_LCDON        0x0800	/* Enable the LCD */

/* to determine the correct external crystal reference */
#define CKIH_27MHZ_BIT_SET      (1 << 3)

static const int mx27ads_pins[] __initconst = {
	/* UART0 */
	PE12_PF_UART1_TXD,
	PE13_PF_UART1_RXD,
	PE14_PF_UART1_CTS,
	PE15_PF_UART1_RTS,
	/* UART1 */
	PE3_PF_UART2_CTS,
	PE4_PF_UART2_RTS,
	PE6_PF_UART2_TXD,
	PE7_PF_UART2_RXD,
	/* UART2 */
	PE8_PF_UART3_TXD,
	PE9_PF_UART3_RXD,
	PE10_PF_UART3_CTS,
	PE11_PF_UART3_RTS,
	/* UART3 */
	PB26_AF_UART4_RTS,
	PB28_AF_UART4_TXD,
	PB29_AF_UART4_CTS,
	PB31_AF_UART4_RXD,
	/* UART4 */
	PB18_AF_UART5_TXD,
	PB19_AF_UART5_RXD,
	PB20_AF_UART5_CTS,
	PB21_AF_UART5_RTS,
	/* UART5 */
	PB10_AF_UART6_TXD,
	PB12_AF_UART6_CTS,
	PB11_AF_UART6_RXD,
	PB13_AF_UART6_RTS,
	/* FEC */
	PD0_AIN_FEC_TXD0,
	PD1_AIN_FEC_TXD1,
	PD2_AIN_FEC_TXD2,
	PD3_AIN_FEC_TXD3,
	PD4_AOUT_FEC_RX_ER,
	PD5_AOUT_FEC_RXD1,
	PD6_AOUT_FEC_RXD2,
	PD7_AOUT_FEC_RXD3,
	PD8_AF_FEC_MDIO,
	PD9_AIN_FEC_MDC,
	PD10_AOUT_FEC_CRS,
	PD11_AOUT_FEC_TX_CLK,
	PD12_AOUT_FEC_RXD0,
	PD13_AOUT_FEC_RX_DV,
	PD14_AOUT_FEC_RX_CLK,
	PD15_AOUT_FEC_COL,
	PD16_AIN_FEC_TX_ER,
	PF23_AIN_FEC_TX_EN,
	/* I2C2 */
	PC5_PF_I2C2_SDA,
	PC6_PF_I2C2_SCL,
	/* FB */
	PA5_PF_LSCLK,
	PA6_PF_LD0,
	PA7_PF_LD1,
	PA8_PF_LD2,
	PA9_PF_LD3,
	PA10_PF_LD4,
	PA11_PF_LD5,
	PA12_PF_LD6,
	PA13_PF_LD7,
	PA14_PF_LD8,
	PA15_PF_LD9,
	PA16_PF_LD10,
	PA17_PF_LD11,
	PA18_PF_LD12,
	PA19_PF_LD13,
	PA20_PF_LD14,
	PA21_PF_LD15,
	PA22_PF_LD16,
	PA23_PF_LD17,
	PA24_PF_REV,
	PA25_PF_CLS,
	PA26_PF_PS,
	PA27_PF_SPL_SPR,
	PA28_PF_HSYNC,
	PA29_PF_VSYNC,
	PA30_PF_CONTRAST,
	PA31_PF_OE_ACD,
	/* OWIRE */
	PE16_AF_OWIRE,
	/* SDHC1*/
	PE18_PF_SD1_D0,
	PE19_PF_SD1_D1,
	PE20_PF_SD1_D2,
	PE21_PF_SD1_D3,
	PE22_PF_SD1_CMD,
	PE23_PF_SD1_CLK,
	/* SDHC2*/
	PB4_PF_SD2_D0,
	PB5_PF_SD2_D1,
	PB6_PF_SD2_D2,
	PB7_PF_SD2_D3,
	PB8_PF_SD2_CMD,
	PB9_PF_SD2_CLK,
};

static const struct mxc_nand_platform_data
mx27ads_nand_board_info __initconst = {
	.width = 1,
	.hw_ecc = 1,
};

/* ADS's NOR flash */
static struct physmap_flash_data mx27ads_flash_data = {
	.width = 2,
};

static struct resource mx27ads_flash_resource = {
	.start = 0xc0000000,
	.end = 0xc0000000 + 0x02000000 - 1,
	.flags = IORESOURCE_MEM,

};

static struct platform_device mx27ads_nor_mtd_device = {
	.name = "physmap-flash",
	.id = 0,
	.dev = {
		.platform_data = &mx27ads_flash_data,
	},
	.num_resources = 1,
	.resource = &mx27ads_flash_resource,
};

static const struct imxi2c_platform_data mx27ads_i2c1_data __initconst = {
	.bitrate = 100000,
};

static struct i2c_board_info mx27ads_i2c_devices[] = {
};

static void vgpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	if (value)
		__raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_SET_REG);
	else
		__raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_CLEAR_REG);
}

static int vgpio_dir_out(struct gpio_chip *chip, unsigned offset, int value)
{
	return 0;
}

#define MX27ADS_LCD_GPIO	(6 * 32)

static struct regulator_consumer_supply mx27ads_lcd_regulator_consumer =
	REGULATOR_SUPPLY("lcd", "imx-fb.0");

static struct regulator_init_data mx27ads_lcd_regulator_init_data = {
	.constraints	= {
		.valid_ops_mask	= REGULATOR_CHANGE_STATUS,
},
	.consumer_supplies	= &mx27ads_lcd_regulator_consumer,
	.num_consumer_supplies	= 1,
};

static struct fixed_voltage_config mx27ads_lcd_regulator_pdata = {
	.supply_name	= "LCD",
	.microvolts	= 3300000,
	.gpio		= MX27ADS_LCD_GPIO,
	.init_data	= &mx27ads_lcd_regulator_init_data,
};

static void __init mx27ads_regulator_init(void)
{
	struct gpio_chip *vchip;

	vchip = kzalloc(sizeof(*vchip), GFP_KERNEL);
	vchip->owner		= THIS_MODULE;
	vchip->label		= "LCD";
	vchip->base		= MX27ADS_LCD_GPIO;
	vchip->ngpio		= 1;
	vchip->direction_output	= vgpio_dir_out;
	vchip->set		= vgpio_set;
	gpiochip_add(vchip);

	platform_device_register_data(NULL, "reg-fixed-voltage",
				      PLATFORM_DEVID_AUTO,
				      &mx27ads_lcd_regulator_pdata,
				      sizeof(mx27ads_lcd_regulator_pdata));
}

static struct imx_fb_videomode mx27ads_modes[] = {
	{
		.mode = {
			.name		= "Sharp-LQ035Q7",
			.refresh	= 60,
			.xres		= 240,
			.yres		= 320,
			.pixclock	= 188679, /* in ps (5.3MHz) */
			.hsync_len	= 1,
			.left_margin	= 9,
			.right_margin	= 16,
			.vsync_len	= 1,
			.upper_margin	= 7,
			.lower_margin	= 9,
		},
		.bpp		= 16,
		.pcr		= 0xFB008BC0,
	},
};

static const struct imx_fb_platform_data mx27ads_fb_data __initconst = {
	.mode = mx27ads_modes,
	.num_modes = ARRAY_SIZE(mx27ads_modes),

	/*
	 * - HSYNC active high
	 * - VSYNC active high
	 * - clk notenabled while idle
	 * - clock inverted
	 * - data not inverted
	 * - data enable low active
	 * - enable sharp mode
	 */
	.pwmr		= 0x00A903FF,
	.lscr1		= 0x00120300,
	.dmacr		= 0x00020010,
};

static int mx27ads_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
			      void *data)
{
	return request_irq(gpio_to_irq(IMX_GPIO_NR(5, 21)), detect_irq,
			   IRQF_TRIGGER_RISING, "sdhc1-card-detect", data);
}

static int mx27ads_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
			      void *data)
{
	return request_irq(gpio_to_irq(IMX_GPIO_NR(2, 7)), detect_irq,
			   IRQF_TRIGGER_RISING, "sdhc2-card-detect", data);
}

static void mx27ads_sdhc1_exit(struct device *dev, void *data)
{
	free_irq(gpio_to_irq(IMX_GPIO_NR(5, 21)), data);
}

static void mx27ads_sdhc2_exit(struct device *dev, void *data)
{
	free_irq(gpio_to_irq(IMX_GPIO_NR(2, 7)), data);
}

static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
	.init = mx27ads_sdhc1_init,
	.exit = mx27ads_sdhc1_exit,
};

static const struct imxmmc_platform_data sdhc2_pdata __initconst = {
	.init = mx27ads_sdhc2_init,
	.exit = mx27ads_sdhc2_exit,
};

static struct platform_device *platform_devices[] __initdata = {
	&mx27ads_nor_mtd_device,
};

static const struct imxuart_platform_data uart_pdata __initconst = {
	.flags = IMXUART_HAVE_RTSCTS,
};

static void __init mx27ads_board_init(void)
{
	imx27_soc_init();

	mxc_gpio_setup_multiple_pins(mx27ads_pins, ARRAY_SIZE(mx27ads_pins),
			"mx27ads");

	imx27_add_imx_uart0(&uart_pdata);
	imx27_add_imx_uart1(&uart_pdata);
	imx27_add_imx_uart2(&uart_pdata);
	imx27_add_imx_uart3(&uart_pdata);
	imx27_add_imx_uart4(&uart_pdata);
	imx27_add_imx_uart5(&uart_pdata);
	imx27_add_mxc_nand(&mx27ads_nand_board_info);

	/* only the i2c master 1 is used on this CPU card */
	i2c_register_board_info(1, mx27ads_i2c_devices,
				ARRAY_SIZE(mx27ads_i2c_devices));
	imx27_add_imx_i2c(1, &mx27ads_i2c1_data);
	mx27ads_regulator_init();
	imx27_add_imx_fb(&mx27ads_fb_data);
	imx27_add_mxc_mmc(0, &sdhc1_pdata);
	imx27_add_mxc_mmc(1, &sdhc2_pdata);

	imx27_add_fec(NULL);
	platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
	imx27_add_mxc_w1();
}

static void __init mx27ads_timer_init(void)
{
	unsigned long fref = 26000000;

	if ((__raw_readw(PBC_VERSION_REG) & CKIH_27MHZ_BIT_SET) == 0)
		fref = 27000000;

	mx27_clocks_init(fref);
}

static struct map_desc mx27ads_io_desc[] __initdata = {
	{
		.virtual = PBC_BASE_ADDRESS,
		.pfn = __phys_to_pfn(MX27_CS4_BASE_ADDR),
		.length = SZ_1M,
		.type = MT_DEVICE,
	},
};

static void __init mx27ads_map_io(void)
{
	mx27_map_io();
	iotable_init(mx27ads_io_desc, ARRAY_SIZE(mx27ads_io_desc));
}

MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
	/* maintainer: Freescale Semiconductor, Inc. */
	.atag_offset = 0x100,
	.map_io = mx27ads_map_io,
	.init_early = imx27_init_early,
	.init_irq = mx27_init_irq,
	.init_time	= mx27ads_timer_init,
	.init_machine = mx27ads_board_init,
	.restart	= mxc_restart,
MACHINE_END
Commit	Line	Data
80eedae6 JB	1	/*
	2	* Copyright (C) 2000 Deep Blue Solutions Ltd
	3	* Copyright (C) 2002 Shane Nay (shane@minirl.com)
	4	* Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
80eedae6	15	*/
2f8163ba	16	#include <linux/gpio.h>
80eedae6 JB	17	#include <linux/platform_device.h>
	18	#include <linux/mtd/mtd.h>
	19	#include <linux/mtd/map.h>
	20	#include <linux/mtd/partitions.h>
	21	#include <linux/mtd/physmap.h>
c981214a	22	#include <linux/i2c.h>
60c24dc7	23	#include <linux/irq.h>
9fe21fdc AS	24
	25	#include <linux/regulator/fixed.h>
	26	#include <linux/regulator/machine.h>
	27
80eedae6 JB	28	#include <asm/mach-types.h>
	29	#include <asm/mach/arch.h>
	30	#include <asm/mach/time.h>
	31	#include <asm/mach/map.h>
80eedae6	32
e3372474	33	#include "common.h"
0e7a29a8	34	#include "devices-imx27.h"
50f2de61	35	#include "hardware.h"
267dd34c	36	#include "iomux-mx27.h"
7e90534a	37
1faeaab2 UKK	38	/*
	39	* Base address of PBC controller, CS4
	40	*/
	41	#define PBC_BASE_ADDRESS 0xf4300000
	42	#define PBC_REG_ADDR(offset) (void __force __iomem *) \
	43	(PBC_BASE_ADDRESS + (offset))
	44
	45	/* When the PBC address connection is fixed in h/w, defined as 1 */
	46	#define PBC_ADDR_SH 0
	47
	48	/* Offsets for the PBC Controller register */
	49	/*
	50	* PBC Board version register offset
	51	*/
	52	#define PBC_VERSION_REG PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH)
	53	/*
	54	* PBC Board control register 1 set address.
	55	*/
	56	#define PBC_BCTRL1_SET_REG PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH)
	57	/*
	58	* PBC Board control register 1 clear address.
	59	*/
	60	#define PBC_BCTRL1_CLEAR_REG PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH)
	61
	62	/* PBC Board Control Register 1 bit definitions */
	63	#define PBC_BCTRL1_LCDON 0x0800 /* Enable the LCD */
	64
	65	/* to determine the correct external crystal reference */
	66	#define CKIH_27MHZ_BIT_SET (1 << 3)
	67
6c80ee51	68	static const int mx27ads_pins[] __initconst = {
c1a6f123	69	/* UART0 */
80eedae6 JB	70	PE12_PF_UART1_TXD,
	71	PE13_PF_UART1_RXD,
	72	PE14_PF_UART1_CTS,
c1a6f123 VB	73	PE15_PF_UART1_RTS,
c1a6f123 VB	74	/* UART1 */
80eedae6 JB	75	PE3_PF_UART2_CTS,
	76	PE4_PF_UART2_RTS,
	77	PE6_PF_UART2_TXD,
c1a6f123 VB	78	PE7_PF_UART2_RXD,
c1a6f123 VB	79	/* UART2 */
80eedae6 JB	80	PE8_PF_UART3_TXD,
	81	PE9_PF_UART3_RXD,
	82	PE10_PF_UART3_CTS,
c1a6f123 VB	83	PE11_PF_UART3_RTS,
c1a6f123 VB	84	/* UART3 */
80eedae6 JB	85	PB26_AF_UART4_RTS,
	86	PB28_AF_UART4_TXD,
	87	PB29_AF_UART4_CTS,
c1a6f123 VB	88	PB31_AF_UART4_RXD,
c1a6f123 VB	89	/* UART4 */
80eedae6 JB	90	PB18_AF_UART5_TXD,
	91	PB19_AF_UART5_RXD,
	92	PB20_AF_UART5_CTS,
c1a6f123 VB	93	PB21_AF_UART5_RTS,
c1a6f123 VB	94	/* UART5 */
80eedae6 JB	95	PB10_AF_UART6_TXD,
	96	PB12_AF_UART6_CTS,
	97	PB11_AF_UART6_RXD,
c1a6f123 VB	98	PB13_AF_UART6_RTS,
c1a6f123 VB	99	/* FEC */
80eedae6 JB	100	PD0_AIN_FEC_TXD0,
	101	PD1_AIN_FEC_TXD1,
	102	PD2_AIN_FEC_TXD2,
	103	PD3_AIN_FEC_TXD3,
	104	PD4_AOUT_FEC_RX_ER,
	105	PD5_AOUT_FEC_RXD1,
	106	PD6_AOUT_FEC_RXD2,
	107	PD7_AOUT_FEC_RXD3,
	108	PD8_AF_FEC_MDIO,
	109	PD9_AIN_FEC_MDC,
	110	PD10_AOUT_FEC_CRS,
	111	PD11_AOUT_FEC_TX_CLK,
	112	PD12_AOUT_FEC_RXD0,
	113	PD13_AOUT_FEC_RX_DV,
ccfe30a7	114	PD14_AOUT_FEC_RX_CLK,
80eedae6 JB	115	PD15_AOUT_FEC_COL,
80eedae6 JB	116	PD16_AIN_FEC_TX_ER,
c1a6f123	117	PF23_AIN_FEC_TX_EN,
c981214a VB	118	/* I2C2 */
	119	PC5_PF_I2C2_SDA,
	120	PC6_PF_I2C2_SCL,
11cda13d VB	121	/* FB */
	122	PA5_PF_LSCLK,
	123	PA6_PF_LD0,
	124	PA7_PF_LD1,
	125	PA8_PF_LD2,
	126	PA9_PF_LD3,
	127	PA10_PF_LD4,
	128	PA11_PF_LD5,
	129	PA12_PF_LD6,
	130	PA13_PF_LD7,
	131	PA14_PF_LD8,
	132	PA15_PF_LD9,
	133	PA16_PF_LD10,
	134	PA17_PF_LD11,
	135	PA18_PF_LD12,
	136	PA19_PF_LD13,
	137	PA20_PF_LD14,
	138	PA21_PF_LD15,
	139	PA22_PF_LD16,
	140	PA23_PF_LD17,
	141	PA24_PF_REV,
	142	PA25_PF_CLS,
	143	PA26_PF_PS,
	144	PA27_PF_SPL_SPR,
	145	PA28_PF_HSYNC,
	146	PA29_PF_VSYNC,
	147	PA30_PF_CONTRAST,
	148	PA31_PF_OE_ACD,
9366d8f6 VB	149	/* OWIRE */
9366d8f6 VB	150	PE16_AF_OWIRE,
60c24dc7 VB	151	/* SDHC1*/
	152	PE18_PF_SD1_D0,
	153	PE19_PF_SD1_D1,
	154	PE20_PF_SD1_D2,
	155	PE21_PF_SD1_D3,
	156	PE22_PF_SD1_CMD,
	157	PE23_PF_SD1_CLK,
	158	/* SDHC2*/
	159	PB4_PF_SD2_D0,
	160	PB5_PF_SD2_D1,
	161	PB6_PF_SD2_D2,
	162	PB7_PF_SD2_D3,
	163	PB8_PF_SD2_CMD,
	164	PB9_PF_SD2_CLK,
80eedae6 JB	165	};
80eedae6 JB	166
0e7a29a8 UKK	167	static const struct mxc_nand_platform_data
0e7a29a8 UKK	168	mx27ads_nand_board_info __initconst = {
8d4fd258 VB	169	.width = 1,
	170	.hw_ecc = 1,
	171	};
	172
c1a6f123 VB	173	/* ADS's NOR flash */
	174	static struct physmap_flash_data mx27ads_flash_data = {
	175	.width = 2,
	176	};
	177
	178	static struct resource mx27ads_flash_resource = {
	179	.start = 0xc0000000,
	180	.end = 0xc0000000 + 0x02000000 - 1,
	181	.flags = IORESOURCE_MEM,
	182
	183	};
	184
	185	static struct platform_device mx27ads_nor_mtd_device = {
	186	.name = "physmap-flash",
	187	.id = 0,
	188	.dev = {
	189	.platform_data = &mx27ads_flash_data,
	190	},
	191	.num_resources = 1,
	192	.resource = &mx27ads_flash_resource,
	193	};
	194
c6987159	195	static const struct imxi2c_platform_data mx27ads_i2c1_data __initconst = {
c981214a VB	196	.bitrate = 100000,
	197	};
	198
	199	static struct i2c_board_info mx27ads_i2c_devices[] = {
	200	};
	201
9fe21fdc	202	static void vgpio_set(struct gpio_chip *chip, unsigned offset, int value)
11cda13d	203	{
9fe21fdc	204	if (value)
11cda13d VB	205	__raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_SET_REG);
	206	else
	207	__raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_CLEAR_REG);
	208	}
	209
9fe21fdc AS	210	static int vgpio_dir_out(struct gpio_chip *chip, unsigned offset, int value)
	211	{
	212	return 0;
	213	}
	214
	215	#define MX27ADS_LCD_GPIO (6 * 32)
	216
	217	static struct regulator_consumer_supply mx27ads_lcd_regulator_consumer =
	218	REGULATOR_SUPPLY("lcd", "imx-fb.0");
	219
	220	static struct regulator_init_data mx27ads_lcd_regulator_init_data = {
	221	.constraints = {
	222	.valid_ops_mask = REGULATOR_CHANGE_STATUS,
	223	},
	224	.consumer_supplies = &mx27ads_lcd_regulator_consumer,
	225	.num_consumer_supplies = 1,
	226	};
	227
	228	static struct fixed_voltage_config mx27ads_lcd_regulator_pdata = {
	229	.supply_name = "LCD",
	230	.microvolts = 3300000,
	231	.gpio = MX27ADS_LCD_GPIO,
	232	.init_data = &mx27ads_lcd_regulator_init_data,
	233	};
	234
	235	static void __init mx27ads_regulator_init(void)
	236	{
	237	struct gpio_chip *vchip;
	238
	239	vchip = kzalloc(sizeof(*vchip), GFP_KERNEL);
	240	vchip->owner = THIS_MODULE;
	241	vchip->label = "LCD";
	242	vchip->base = MX27ADS_LCD_GPIO;
	243	vchip->ngpio = 1;
	244	vchip->direction_output = vgpio_dir_out;
	245	vchip->set = vgpio_set;
	246	gpiochip_add(vchip);
	247
d2168146	248	platform_device_register_data(NULL, "reg-fixed-voltage",
9fe21fdc AS	249	PLATFORM_DEVID_AUTO,
	250	&mx27ads_lcd_regulator_pdata,
	251	sizeof(mx27ads_lcd_regulator_pdata));
	252	}
	253
343684ff SH	254	static struct imx_fb_videomode mx27ads_modes[] = {
	255	{
	256	.mode = {
	257	.name = "Sharp-LQ035Q7",
	258	.refresh = 60,
	259	.xres = 240,
	260	.yres = 320,
	261	.pixclock = 188679, /* in ps (5.3MHz) */
	262	.hsync_len = 1,
	263	.left_margin = 9,
	264	.right_margin = 16,
	265	.vsync_len = 1,
	266	.upper_margin = 7,
	267	.lower_margin = 9,
	268	},
	269	.bpp = 16,
	270	.pcr = 0xFB008BC0,
	271	},
	272	};
11cda13d	273
ad851bff	274	static const struct imx_fb_platform_data mx27ads_fb_data __initconst = {
343684ff SH	275	.mode = mx27ads_modes,
343684ff SH	276	.num_modes = ARRAY_SIZE(mx27ads_modes),
11cda13d VB	277
	278	/*
	279	* - HSYNC active high
	280	* - VSYNC active high
	281	* - clk notenabled while idle
	282	* - clock inverted
	283	* - data not inverted
	284	* - data enable low active
	285	* - enable sharp mode
	286	*/
11cda13d VB	287	.pwmr = 0x00A903FF,
	288	.lscr1 = 0x00120300,
	289	.dmacr = 0x00020010,
11cda13d VB	290	};
11cda13d VB	291
60c24dc7 VB	292	static int mx27ads_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
	293	void *data)
	294	{
438196c3 SG	295	return request_irq(gpio_to_irq(IMX_GPIO_NR(5, 21)), detect_irq,
438196c3 SG	296	IRQF_TRIGGER_RISING, "sdhc1-card-detect", data);
60c24dc7 VB	297	}
	298
	299	static int mx27ads_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
	300	void *data)
	301	{
438196c3 SG	302	return request_irq(gpio_to_irq(IMX_GPIO_NR(2, 7)), detect_irq,
438196c3 SG	303	IRQF_TRIGGER_RISING, "sdhc2-card-detect", data);
60c24dc7 VB	304	}
	305
	306	static void mx27ads_sdhc1_exit(struct device dev, void data)
	307	{
438196c3	308	free_irq(gpio_to_irq(IMX_GPIO_NR(5, 21)), data);
60c24dc7 VB	309	}
	310
	311	static void mx27ads_sdhc2_exit(struct device dev, void data)
	312	{
438196c3	313	free_irq(gpio_to_irq(IMX_GPIO_NR(2, 7)), data);
60c24dc7 VB	314	}
60c24dc7 VB	315
9d3d945a	316	static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
60c24dc7 VB	317	.init = mx27ads_sdhc1_init,
	318	.exit = mx27ads_sdhc1_exit,
	319	};
	320
9d3d945a	321	static const struct imxmmc_platform_data sdhc2_pdata __initconst = {
60c24dc7 VB	322	.init = mx27ads_sdhc2_init,
	323	.exit = mx27ads_sdhc2_exit,
	324	};
	325
c1a6f123 VB	326	static struct platform_device *platform_devices[] __initdata = {
c1a6f123 VB	327	&mx27ads_nor_mtd_device,
c1a6f123	328	};
80eedae6	329
d5dac4a6 UKK	330	static const struct imxuart_platform_data uart_pdata __initconst = {
d5dac4a6 UKK	331	.flags = IMXUART_HAVE_RTSCTS,
80eedae6 JB	332	};
	333
	334	static void __init mx27ads_board_init(void)
	335	{
b78d8e59 SG	336	imx27_soc_init();
b78d8e59 SG	337
c1a6f123 VB	338	mxc_gpio_setup_multiple_pins(mx27ads_pins, ARRAY_SIZE(mx27ads_pins),
c1a6f123 VB	339	"mx27ads");
80eedae6	340
d5dac4a6 UKK	341	imx27_add_imx_uart0(&uart_pdata);
	342	imx27_add_imx_uart1(&uart_pdata);
	343	imx27_add_imx_uart2(&uart_pdata);
	344	imx27_add_imx_uart3(&uart_pdata);
	345	imx27_add_imx_uart4(&uart_pdata);
	346	imx27_add_imx_uart5(&uart_pdata);
0e7a29a8	347	imx27_add_mxc_nand(&mx27ads_nand_board_info);
c981214a VB	348
	349	/* only the i2c master 1 is used on this CPU card */
	350	i2c_register_board_info(1, mx27ads_i2c_devices,
	351	ARRAY_SIZE(mx27ads_i2c_devices));
77a406da	352	imx27_add_imx_i2c(1, &mx27ads_i2c1_data);
9fe21fdc	353	mx27ads_regulator_init();
ad851bff	354	imx27_add_imx_fb(&mx27ads_fb_data);
9d3d945a UKK	355	imx27_add_mxc_mmc(0, &sdhc1_pdata);
9d3d945a UKK	356	imx27_add_mxc_mmc(1, &sdhc2_pdata);
80eedae6	357
6bd96f3c	358	imx27_add_fec(NULL);
80eedae6	359	platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
bec31a85	360	imx27_add_mxc_w1();
80eedae6 JB	361	}
	362
	363	static void __init mx27ads_timer_init(void)
	364	{
	365	unsigned long fref = 26000000;
	366
	367	if ((__raw_readw(PBC_VERSION_REG) & CKIH_27MHZ_BIT_SET) == 0)
	368	fref = 27000000;
	369
30c730f8	370	mx27_clocks_init(fref);
80eedae6 JB	371	}
80eedae6 JB	372
80eedae6 JB	373	static struct map_desc mx27ads_io_desc[] __initdata = {
	374	{
	375	.virtual = PBC_BASE_ADDRESS,
3f35d1f5	376	.pfn = __phys_to_pfn(MX27_CS4_BASE_ADDR),
80eedae6 JB	377	.length = SZ_1M,
	378	.type = MT_DEVICE,
	379	},
	380	};
	381
058b7a6f	382	static void __init mx27ads_map_io(void)
80eedae6	383	{
cd4a05f9	384	mx27_map_io();
80eedae6 JB	385	iotable_init(mx27ads_io_desc, ARRAY_SIZE(mx27ads_io_desc));
	386	}
	387
	388	MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
	389	/* maintainer: Freescale Semiconductor, Inc. */
dc8f1907	390	.atag_offset = 0x100,
3dac2196 UKK	391	.map_io = mx27ads_map_io,
	392	.init_early = imx27_init_early,
	393	.init_irq = mx27_init_irq,
6bb27d73	394	.init_time = mx27ads_timer_init,
3dac2196	395	.init_machine = mx27ads_board_init,
65ea7884	396	.restart = mxc_restart,
80eedae6	397	MACHINE_END