Commit | Line | Data |
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80eedae6 JB |
1 | /* |
2 | * Copyright (C) 2000 Deep Blue Solutions Ltd | |
3 | * Copyright (C) 2002 Shane Nay (shane@minirl.com) | |
4 | * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
80eedae6 JB |
15 | */ |
16 | ||
17 | #include <linux/platform_device.h> | |
18 | #include <linux/mtd/mtd.h> | |
19 | #include <linux/mtd/map.h> | |
20 | #include <linux/mtd/partitions.h> | |
21 | #include <linux/mtd/physmap.h> | |
c981214a | 22 | #include <linux/i2c.h> |
60c24dc7 | 23 | #include <linux/irq.h> |
a09e64fb RK |
24 | #include <mach/common.h> |
25 | #include <mach/hardware.h> | |
80eedae6 JB |
26 | #include <asm/mach-types.h> |
27 | #include <asm/mach/arch.h> | |
28 | #include <asm/mach/time.h> | |
29 | #include <asm/mach/map.h> | |
a09e64fb RK |
30 | #include <mach/gpio.h> |
31 | #include <mach/imx-uart.h> | |
e835d88e | 32 | #include <mach/iomux-mx27.h> |
8d4fd258 | 33 | #include <mach/mxc_nand.h> |
11cda13d | 34 | #include <mach/imxfb.h> |
60c24dc7 | 35 | #include <mach/mmc.h> |
80eedae6 | 36 | |
0e7a29a8 | 37 | #include "devices-imx27.h" |
7e90534a SH |
38 | #include "devices.h" |
39 | ||
1faeaab2 UKK |
40 | /* |
41 | * Base address of PBC controller, CS4 | |
42 | */ | |
43 | #define PBC_BASE_ADDRESS 0xf4300000 | |
44 | #define PBC_REG_ADDR(offset) (void __force __iomem *) \ | |
45 | (PBC_BASE_ADDRESS + (offset)) | |
46 | ||
47 | /* When the PBC address connection is fixed in h/w, defined as 1 */ | |
48 | #define PBC_ADDR_SH 0 | |
49 | ||
50 | /* Offsets for the PBC Controller register */ | |
51 | /* | |
52 | * PBC Board version register offset | |
53 | */ | |
54 | #define PBC_VERSION_REG PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH) | |
55 | /* | |
56 | * PBC Board control register 1 set address. | |
57 | */ | |
58 | #define PBC_BCTRL1_SET_REG PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH) | |
59 | /* | |
60 | * PBC Board control register 1 clear address. | |
61 | */ | |
62 | #define PBC_BCTRL1_CLEAR_REG PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH) | |
63 | ||
64 | /* PBC Board Control Register 1 bit definitions */ | |
65 | #define PBC_BCTRL1_LCDON 0x0800 /* Enable the LCD */ | |
66 | ||
67 | /* to determine the correct external crystal reference */ | |
68 | #define CKIH_27MHZ_BIT_SET (1 << 3) | |
69 | ||
c1a6f123 VB |
70 | static unsigned int mx27ads_pins[] = { |
71 | /* UART0 */ | |
80eedae6 JB |
72 | PE12_PF_UART1_TXD, |
73 | PE13_PF_UART1_RXD, | |
74 | PE14_PF_UART1_CTS, | |
c1a6f123 VB |
75 | PE15_PF_UART1_RTS, |
76 | /* UART1 */ | |
80eedae6 JB |
77 | PE3_PF_UART2_CTS, |
78 | PE4_PF_UART2_RTS, | |
79 | PE6_PF_UART2_TXD, | |
c1a6f123 VB |
80 | PE7_PF_UART2_RXD, |
81 | /* UART2 */ | |
80eedae6 JB |
82 | PE8_PF_UART3_TXD, |
83 | PE9_PF_UART3_RXD, | |
84 | PE10_PF_UART3_CTS, | |
c1a6f123 VB |
85 | PE11_PF_UART3_RTS, |
86 | /* UART3 */ | |
80eedae6 JB |
87 | PB26_AF_UART4_RTS, |
88 | PB28_AF_UART4_TXD, | |
89 | PB29_AF_UART4_CTS, | |
c1a6f123 VB |
90 | PB31_AF_UART4_RXD, |
91 | /* UART4 */ | |
80eedae6 JB |
92 | PB18_AF_UART5_TXD, |
93 | PB19_AF_UART5_RXD, | |
94 | PB20_AF_UART5_CTS, | |
c1a6f123 VB |
95 | PB21_AF_UART5_RTS, |
96 | /* UART5 */ | |
80eedae6 JB |
97 | PB10_AF_UART6_TXD, |
98 | PB12_AF_UART6_CTS, | |
99 | PB11_AF_UART6_RXD, | |
c1a6f123 VB |
100 | PB13_AF_UART6_RTS, |
101 | /* FEC */ | |
80eedae6 JB |
102 | PD0_AIN_FEC_TXD0, |
103 | PD1_AIN_FEC_TXD1, | |
104 | PD2_AIN_FEC_TXD2, | |
105 | PD3_AIN_FEC_TXD3, | |
106 | PD4_AOUT_FEC_RX_ER, | |
107 | PD5_AOUT_FEC_RXD1, | |
108 | PD6_AOUT_FEC_RXD2, | |
109 | PD7_AOUT_FEC_RXD3, | |
110 | PD8_AF_FEC_MDIO, | |
111 | PD9_AIN_FEC_MDC, | |
112 | PD10_AOUT_FEC_CRS, | |
113 | PD11_AOUT_FEC_TX_CLK, | |
114 | PD12_AOUT_FEC_RXD0, | |
115 | PD13_AOUT_FEC_RX_DV, | |
ccfe30a7 | 116 | PD14_AOUT_FEC_RX_CLK, |
80eedae6 JB |
117 | PD15_AOUT_FEC_COL, |
118 | PD16_AIN_FEC_TX_ER, | |
c1a6f123 | 119 | PF23_AIN_FEC_TX_EN, |
c981214a VB |
120 | /* I2C2 */ |
121 | PC5_PF_I2C2_SDA, | |
122 | PC6_PF_I2C2_SCL, | |
11cda13d VB |
123 | /* FB */ |
124 | PA5_PF_LSCLK, | |
125 | PA6_PF_LD0, | |
126 | PA7_PF_LD1, | |
127 | PA8_PF_LD2, | |
128 | PA9_PF_LD3, | |
129 | PA10_PF_LD4, | |
130 | PA11_PF_LD5, | |
131 | PA12_PF_LD6, | |
132 | PA13_PF_LD7, | |
133 | PA14_PF_LD8, | |
134 | PA15_PF_LD9, | |
135 | PA16_PF_LD10, | |
136 | PA17_PF_LD11, | |
137 | PA18_PF_LD12, | |
138 | PA19_PF_LD13, | |
139 | PA20_PF_LD14, | |
140 | PA21_PF_LD15, | |
141 | PA22_PF_LD16, | |
142 | PA23_PF_LD17, | |
143 | PA24_PF_REV, | |
144 | PA25_PF_CLS, | |
145 | PA26_PF_PS, | |
146 | PA27_PF_SPL_SPR, | |
147 | PA28_PF_HSYNC, | |
148 | PA29_PF_VSYNC, | |
149 | PA30_PF_CONTRAST, | |
150 | PA31_PF_OE_ACD, | |
9366d8f6 VB |
151 | /* OWIRE */ |
152 | PE16_AF_OWIRE, | |
60c24dc7 VB |
153 | /* SDHC1*/ |
154 | PE18_PF_SD1_D0, | |
155 | PE19_PF_SD1_D1, | |
156 | PE20_PF_SD1_D2, | |
157 | PE21_PF_SD1_D3, | |
158 | PE22_PF_SD1_CMD, | |
159 | PE23_PF_SD1_CLK, | |
160 | /* SDHC2*/ | |
161 | PB4_PF_SD2_D0, | |
162 | PB5_PF_SD2_D1, | |
163 | PB6_PF_SD2_D2, | |
164 | PB7_PF_SD2_D3, | |
165 | PB8_PF_SD2_CMD, | |
166 | PB9_PF_SD2_CLK, | |
80eedae6 JB |
167 | }; |
168 | ||
0e7a29a8 UKK |
169 | static const struct mxc_nand_platform_data |
170 | mx27ads_nand_board_info __initconst = { | |
8d4fd258 VB |
171 | .width = 1, |
172 | .hw_ecc = 1, | |
173 | }; | |
174 | ||
c1a6f123 VB |
175 | /* ADS's NOR flash */ |
176 | static struct physmap_flash_data mx27ads_flash_data = { | |
177 | .width = 2, | |
178 | }; | |
179 | ||
180 | static struct resource mx27ads_flash_resource = { | |
181 | .start = 0xc0000000, | |
182 | .end = 0xc0000000 + 0x02000000 - 1, | |
183 | .flags = IORESOURCE_MEM, | |
184 | ||
185 | }; | |
186 | ||
187 | static struct platform_device mx27ads_nor_mtd_device = { | |
188 | .name = "physmap-flash", | |
189 | .id = 0, | |
190 | .dev = { | |
191 | .platform_data = &mx27ads_flash_data, | |
192 | }, | |
193 | .num_resources = 1, | |
194 | .resource = &mx27ads_flash_resource, | |
195 | }; | |
196 | ||
c6987159 | 197 | static const struct imxi2c_platform_data mx27ads_i2c1_data __initconst = { |
c981214a VB |
198 | .bitrate = 100000, |
199 | }; | |
200 | ||
201 | static struct i2c_board_info mx27ads_i2c_devices[] = { | |
202 | }; | |
203 | ||
11cda13d VB |
204 | void lcd_power(int on) |
205 | { | |
206 | if (on) | |
207 | __raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_SET_REG); | |
208 | else | |
209 | __raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_CLEAR_REG); | |
210 | } | |
211 | ||
343684ff SH |
212 | static struct imx_fb_videomode mx27ads_modes[] = { |
213 | { | |
214 | .mode = { | |
215 | .name = "Sharp-LQ035Q7", | |
216 | .refresh = 60, | |
217 | .xres = 240, | |
218 | .yres = 320, | |
219 | .pixclock = 188679, /* in ps (5.3MHz) */ | |
220 | .hsync_len = 1, | |
221 | .left_margin = 9, | |
222 | .right_margin = 16, | |
223 | .vsync_len = 1, | |
224 | .upper_margin = 7, | |
225 | .lower_margin = 9, | |
226 | }, | |
227 | .bpp = 16, | |
228 | .pcr = 0xFB008BC0, | |
229 | }, | |
230 | }; | |
11cda13d | 231 | |
343684ff SH |
232 | static struct imx_fb_platform_data mx27ads_fb_data = { |
233 | .mode = mx27ads_modes, | |
234 | .num_modes = ARRAY_SIZE(mx27ads_modes), | |
11cda13d VB |
235 | |
236 | /* | |
237 | * - HSYNC active high | |
238 | * - VSYNC active high | |
239 | * - clk notenabled while idle | |
240 | * - clock inverted | |
241 | * - data not inverted | |
242 | * - data enable low active | |
243 | * - enable sharp mode | |
244 | */ | |
11cda13d VB |
245 | .pwmr = 0x00A903FF, |
246 | .lscr1 = 0x00120300, | |
247 | .dmacr = 0x00020010, | |
248 | ||
249 | .lcd_power = lcd_power, | |
250 | }; | |
251 | ||
60c24dc7 VB |
252 | static int mx27ads_sdhc1_init(struct device *dev, irq_handler_t detect_irq, |
253 | void *data) | |
254 | { | |
255 | return request_irq(IRQ_GPIOE(21), detect_irq, IRQF_TRIGGER_RISING, | |
256 | "sdhc1-card-detect", data); | |
257 | } | |
258 | ||
259 | static int mx27ads_sdhc2_init(struct device *dev, irq_handler_t detect_irq, | |
260 | void *data) | |
261 | { | |
262 | return request_irq(IRQ_GPIOB(7), detect_irq, IRQF_TRIGGER_RISING, | |
263 | "sdhc2-card-detect", data); | |
264 | } | |
265 | ||
266 | static void mx27ads_sdhc1_exit(struct device *dev, void *data) | |
267 | { | |
268 | free_irq(IRQ_GPIOE(21), data); | |
269 | } | |
270 | ||
271 | static void mx27ads_sdhc2_exit(struct device *dev, void *data) | |
272 | { | |
273 | free_irq(IRQ_GPIOB(7), data); | |
274 | } | |
275 | ||
276 | static struct imxmmc_platform_data sdhc1_pdata = { | |
277 | .init = mx27ads_sdhc1_init, | |
278 | .exit = mx27ads_sdhc1_exit, | |
279 | }; | |
280 | ||
281 | static struct imxmmc_platform_data sdhc2_pdata = { | |
282 | .init = mx27ads_sdhc2_init, | |
283 | .exit = mx27ads_sdhc2_exit, | |
284 | }; | |
285 | ||
c1a6f123 VB |
286 | static struct platform_device *platform_devices[] __initdata = { |
287 | &mx27ads_nor_mtd_device, | |
288 | &mxc_fec_device, | |
9366d8f6 | 289 | &mxc_w1_master_device, |
c1a6f123 | 290 | }; |
80eedae6 | 291 | |
80eedae6 JB |
292 | static struct imxuart_platform_data uart_pdata[] = { |
293 | { | |
80eedae6 JB |
294 | .flags = IMXUART_HAVE_RTSCTS, |
295 | }, { | |
80eedae6 JB |
296 | .flags = IMXUART_HAVE_RTSCTS, |
297 | }, { | |
80eedae6 JB |
298 | .flags = IMXUART_HAVE_RTSCTS, |
299 | }, { | |
80eedae6 JB |
300 | .flags = IMXUART_HAVE_RTSCTS, |
301 | }, { | |
80eedae6 JB |
302 | .flags = IMXUART_HAVE_RTSCTS, |
303 | }, { | |
80eedae6 JB |
304 | .flags = IMXUART_HAVE_RTSCTS, |
305 | }, | |
306 | }; | |
307 | ||
308 | static void __init mx27ads_board_init(void) | |
309 | { | |
c1a6f123 VB |
310 | mxc_gpio_setup_multiple_pins(mx27ads_pins, ARRAY_SIZE(mx27ads_pins), |
311 | "mx27ads"); | |
80eedae6 | 312 | |
551823e7 UKK |
313 | mxc_register_device(&imx2x_uart_device0, &uart_pdata[0]); |
314 | mxc_register_device(&imx2x_uart_device1, &uart_pdata[1]); | |
315 | mxc_register_device(&imx2x_uart_device2, &uart_pdata[2]); | |
316 | mxc_register_device(&imx2x_uart_device3, &uart_pdata[3]); | |
317 | mxc_register_device(&imx2x_uart_device4, &uart_pdata[4]); | |
318 | mxc_register_device(&imx2x_uart_device5, &uart_pdata[5]); | |
0e7a29a8 | 319 | imx27_add_mxc_nand(&mx27ads_nand_board_info); |
c981214a VB |
320 | |
321 | /* only the i2c master 1 is used on this CPU card */ | |
322 | i2c_register_board_info(1, mx27ads_i2c_devices, | |
323 | ARRAY_SIZE(mx27ads_i2c_devices)); | |
c6987159 | 324 | imx27_add_i2c_imx1(&mx27ads_i2c1_data); |
11cda13d | 325 | mxc_register_device(&mxc_fb_device, &mx27ads_fb_data); |
60c24dc7 VB |
326 | mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata); |
327 | mxc_register_device(&mxc_sdhc_device1, &sdhc2_pdata); | |
80eedae6 JB |
328 | |
329 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); | |
330 | } | |
331 | ||
332 | static void __init mx27ads_timer_init(void) | |
333 | { | |
334 | unsigned long fref = 26000000; | |
335 | ||
336 | if ((__raw_readw(PBC_VERSION_REG) & CKIH_27MHZ_BIT_SET) == 0) | |
337 | fref = 27000000; | |
338 | ||
30c730f8 | 339 | mx27_clocks_init(fref); |
80eedae6 JB |
340 | } |
341 | ||
058b7a6f | 342 | static struct sys_timer mx27ads_timer = { |
80eedae6 JB |
343 | .init = mx27ads_timer_init, |
344 | }; | |
345 | ||
346 | static struct map_desc mx27ads_io_desc[] __initdata = { | |
347 | { | |
348 | .virtual = PBC_BASE_ADDRESS, | |
3f35d1f5 | 349 | .pfn = __phys_to_pfn(MX27_CS4_BASE_ADDR), |
80eedae6 JB |
350 | .length = SZ_1M, |
351 | .type = MT_DEVICE, | |
352 | }, | |
353 | }; | |
354 | ||
058b7a6f | 355 | static void __init mx27ads_map_io(void) |
80eedae6 | 356 | { |
cd4a05f9 | 357 | mx27_map_io(); |
80eedae6 JB |
358 | iotable_init(mx27ads_io_desc, ARRAY_SIZE(mx27ads_io_desc)); |
359 | } | |
360 | ||
361 | MACHINE_START(MX27ADS, "Freescale i.MX27ADS") | |
362 | /* maintainer: Freescale Semiconductor, Inc. */ | |
3f35d1f5 UKK |
363 | .phys_io = MX27_AIPI_BASE_ADDR, |
364 | .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, | |
34101237 | 365 | .boot_params = MX27_PHYS_OFFSET + 0x100, |
80eedae6 | 366 | .map_io = mx27ads_map_io, |
c5aa0ad0 | 367 | .init_irq = mx27_init_irq, |
80eedae6 JB |
368 | .init_machine = mx27ads_board_init, |
369 | .timer = &mx27ads_timer, | |
370 | MACHINE_END |