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Merge tag 'timer' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
[deliverable/linux.git] / arch / arm / mach-imx / mach-mx31_3ds.c
CommitLineData
1553a1ec
FE		 1/*
2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
1553a1ec
FE		 13 */
14
a2ef4562 15#include <linux/delay.h>
b7f080cf 16#include <linux/dma-mapping.h>
1553a1ec
FE		 17#include <linux/types.h>
18#include <linux/init.h>
19#include <linux/clk.h>
20#include <linux/irq.h>
135cad36 21#include <linux/gpio.h>
2b0c3677 22#include <linux/platform_device.h>
ae7a3f13
AP		 23#include <linux/mfd/mc13783.h>
24#include <linux/spi/spi.h>
e42010e0 25#include <linux/spi/l4f00242t03.h>
ae7a3f13 26#include <linux/regulator/machine.h>
1c50e672
FE		 27#include <linux/usb/otg.h>
28#include <linux/usb/ulpi.h>
164f7b52
AP		 29#include <linux/memblock.h>
30
31#include <media/soc_camera.h>
1553a1ec
FE		 32
33#include <mach/hardware.h>
34#include <asm/mach-types.h>
35#include <asm/mach/arch.h>
36#include <asm/mach/time.h>
37#include <asm/memory.h>
38#include <asm/mach/map.h>
716a3dc2 39#include <asm/memblock.h>
1553a1ec 40#include <mach/common.h>
1553a1ec 41#include <mach/iomux-mx3.h>
c5d38f08 42#include <mach/3ds_debugboard.h>
1c50e672 43#include <mach/ulpi.h>
a2ceeef5
UKK		 44
45#include "devices-imx31.h"
1553a1ec 46
b396dc45
UKK		 47/* CPLD IRQ line for external uart, external ethernet etc */
48#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
49
11a332ad 50static int mx31_3ds_pins[] = {
153fa1d8 51 /* UART1 */
63d97667
VL		 52 MX31_PIN_CTS1__CTS1,
53 MX31_PIN_RTS1__RTS1,
54 MX31_PIN_TXD1__TXD1,
135cad36
ML		 55 MX31_PIN_RXD1__RXD1,
56 IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO),
e42010e0 57 /*SPI0*/
b2a08e3e
FE		 58 IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_ALT1),
59 IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_ALT1),
a1ac4424
AP		 60 /* SPI 1 */
61 MX31_PIN_CSPI2_SCLK__SCLK,
62 MX31_PIN_CSPI2_MOSI__MOSI,
63 MX31_PIN_CSPI2_MISO__MISO,
64 MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
65 MX31_PIN_CSPI2_SS0__SS0,
66 MX31_PIN_CSPI2_SS2__SS2, /*CS for MC13783 */
ae7a3f13
AP		 67 /* MC13783 IRQ */
68 IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO),
a2ef4562
ML		 69 /* USB OTG reset */
70 IOMUX_MODE(MX31_PIN_USB_PWR, IOMUX_CONFIG_GPIO),
71 /* USB OTG */
72 MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
73 MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
74 MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
75 MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
76 MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
77 MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
78 MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
79 MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
80 MX31_PIN_USBOTG_CLK__USBOTG_CLK,
81 MX31_PIN_USBOTG_DIR__USBOTG_DIR,
82 MX31_PIN_USBOTG_NXT__USBOTG_NXT,
83 MX31_PIN_USBOTG_STP__USBOTG_STP,
54c1f636
AP		 84 /*Keyboard*/
85 MX31_PIN_KEY_ROW0_KEY_ROW0,
86 MX31_PIN_KEY_ROW1_KEY_ROW1,
87 MX31_PIN_KEY_ROW2_KEY_ROW2,
88 MX31_PIN_KEY_COL0_KEY_COL0,
89 MX31_PIN_KEY_COL1_KEY_COL1,
90 MX31_PIN_KEY_COL2_KEY_COL2,
91 MX31_PIN_KEY_COL3_KEY_COL3,
0d95b75e
FE		 92 /* USB Host 2 */
93 IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
94 IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
95 IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
96 IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
97 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
98 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
99 IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT1),
100 IOMUX_MODE(MX31_PIN_PC_BVD1, IOMUX_CONFIG_ALT1),
101 IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT1),
102 IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT1),
103 IOMUX_MODE(MX31_PIN_IOIS16, IOMUX_CONFIG_ALT1),
104 IOMUX_MODE(MX31_PIN_PC_RW_B, IOMUX_CONFIG_ALT1),
105 /* USB Host2 reset */
106 IOMUX_MODE(MX31_PIN_USB_BYP, IOMUX_CONFIG_GPIO),
3d943024
FE		 107 /* I2C1 */
108 MX31_PIN_I2C_CLK__I2C1_SCL,
109 MX31_PIN_I2C_DAT__I2C1_SDA,
0ce88b34
AP		 110 /* SDHC1 */
111 MX31_PIN_SD1_DATA3__SD1_DATA3,
112 MX31_PIN_SD1_DATA2__SD1_DATA2,
113 MX31_PIN_SD1_DATA1__SD1_DATA1,
114 MX31_PIN_SD1_DATA0__SD1_DATA0,
115 MX31_PIN_SD1_CLK__SD1_CLK,
116 MX31_PIN_SD1_CMD__SD1_CMD,
117 MX31_PIN_GPIO3_1__GPIO3_1, /* Card detect */
118 MX31_PIN_GPIO3_0__GPIO3_0, /* OE */
e42010e0
AP		 119 /* Framebuffer */
120 MX31_PIN_LD0__LD0,
121 MX31_PIN_LD1__LD1,
122 MX31_PIN_LD2__LD2,
123 MX31_PIN_LD3__LD3,
124 MX31_PIN_LD4__LD4,
125 MX31_PIN_LD5__LD5,
126 MX31_PIN_LD6__LD6,
127 MX31_PIN_LD7__LD7,
128 MX31_PIN_LD8__LD8,
129 MX31_PIN_LD9__LD9,
130 MX31_PIN_LD10__LD10,
131 MX31_PIN_LD11__LD11,
132 MX31_PIN_LD12__LD12,
133 MX31_PIN_LD13__LD13,
134 MX31_PIN_LD14__LD14,
135 MX31_PIN_LD15__LD15,
136 MX31_PIN_LD16__LD16,
137 MX31_PIN_LD17__LD17,
138 MX31_PIN_VSYNC3__VSYNC3,
139 MX31_PIN_HSYNC__HSYNC,
140 MX31_PIN_FPSHIFT__FPSHIFT,
141 MX31_PIN_CONTRAST__CONTRAST,
164f7b52
AP		 142 /* CSI */
143 MX31_PIN_CSI_D6__CSI_D6,
144 MX31_PIN_CSI_D7__CSI_D7,
145 MX31_PIN_CSI_D8__CSI_D8,
146 MX31_PIN_CSI_D9__CSI_D9,
147 MX31_PIN_CSI_D10__CSI_D10,
148 MX31_PIN_CSI_D11__CSI_D11,
149 MX31_PIN_CSI_D12__CSI_D12,
150 MX31_PIN_CSI_D13__CSI_D13,
151 MX31_PIN_CSI_D14__CSI_D14,
152 MX31_PIN_CSI_D15__CSI_D15,
153 MX31_PIN_CSI_HSYNC__CSI_HSYNC,
154 MX31_PIN_CSI_MCLK__CSI_MCLK,
155 MX31_PIN_CSI_PIXCLK__CSI_PIXCLK,
156 MX31_PIN_CSI_VSYNC__CSI_VSYNC,
157 MX31_PIN_CSI_D5__GPIO3_5, /* CMOS PWDN */
158 IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_GPIO), /* CMOS reset */
5fb86e5d
PR		 159 /* SSI */
160 MX31_PIN_STXD4__STXD4,
161 MX31_PIN_SRXD4__SRXD4,
162 MX31_PIN_SCK4__SCK4,
163 MX31_PIN_SFS4__SFS4,
164f7b52
AP		 164};
165
166/*
167 * Camera support
168 */
169static phys_addr_t mx3_camera_base __initdata;
170#define MX31_3DS_CAMERA_BUF_SIZE SZ_8M
171
172#define MX31_3DS_GPIO_CAMERA_PW IOMUX_TO_GPIO(MX31_PIN_CSI_D5)
173#define MX31_3DS_GPIO_CAMERA_RST IOMUX_TO_GPIO(MX31_PIN_RI_DTE1)
174
175static struct gpio mx31_3ds_camera_gpios[] = {
176 { MX31_3DS_GPIO_CAMERA_PW, GPIOF_OUT_INIT_HIGH, "camera-power" },
177 { MX31_3DS_GPIO_CAMERA_RST, GPIOF_OUT_INIT_HIGH, "camera-reset" },
178};
179
afa77ef3
UKK		 180static const struct mx3_camera_pdata mx31_3ds_camera_pdata __initconst = {
181 .flags = MX3_CAMERA_DATAWIDTH_10,
182 .mclk_10khz = 2600,
183};
184
185static int __init mx31_3ds_init_camera(void)
164f7b52 186{
afa77ef3
UKK		 187 int dma, ret = -ENOMEM;
188 struct platform_device *pdev =
189 imx31_alloc_mx3_camera(&mx31_3ds_camera_pdata);
190
191 if (IS_ERR(pdev))
192 return PTR_ERR(pdev);
164f7b52
AP		 193
194 if (!mx3_camera_base)
afa77ef3 195 goto err;
164f7b52 196
afa77ef3 197 dma = dma_declare_coherent_memory(&pdev->dev,
164f7b52
AP		 198 mx3_camera_base, mx3_camera_base,
199 MX31_3DS_CAMERA_BUF_SIZE,
200 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
201
202 if (!(dma & DMA_MEMORY_MAP))
afa77ef3 203 goto err;
164f7b52 204
afa77ef3
UKK		 205 ret = platform_device_add(pdev);
206 if (ret)
207err:
208 platform_device_put(pdev);
209
210 return ret;
164f7b52
AP		 211}
212
213static int mx31_3ds_camera_power(struct device *dev, int on)
214{
215 /* enable or disable the camera */
216 pr_debug("%s: %s the camera\n", __func__, on ? "ENABLE" : "DISABLE");
217 gpio_set_value(MX31_3DS_GPIO_CAMERA_PW, on ? 0 : 1);
218
219 if (!on)
220 goto out;
221
222 /* If enabled, give a reset impulse */
223 gpio_set_value(MX31_3DS_GPIO_CAMERA_RST, 0);
224 msleep(20);
225 gpio_set_value(MX31_3DS_GPIO_CAMERA_RST, 1);
226 msleep(100);
227
228out:
229 return 0;
230}
231
232static struct i2c_board_info mx31_3ds_i2c_camera = {
233 I2C_BOARD_INFO("ov2640", 0x30),
234};
235
236static struct regulator_bulk_data mx31_3ds_camera_regs[] = {
237 { .supply = "cmos_vcore" },
238 { .supply = "cmos_2v8" },
239};
240
241static struct soc_camera_link iclink_ov2640 = {
242 .bus_id = 0,
243 .board_info = &mx31_3ds_i2c_camera,
244 .i2c_adapter_id = 0,
245 .power = mx31_3ds_camera_power,
246 .regulators = mx31_3ds_camera_regs,
247 .num_regulators = ARRAY_SIZE(mx31_3ds_camera_regs),
248};
249
250static struct platform_device mx31_3ds_ov2640 = {
251 .name = "soc-camera-pdrv",
252 .id = 0,
253 .dev = {
254 .platform_data = &iclink_ov2640,
255 },
256};
257
e42010e0
AP		 258/*
259 * FB support
260 */
261static const struct fb_videomode fb_modedb[] = {
262 { /* 480x640 @ 60 Hz */
263 .name = "Epson-VGA",
264 .refresh = 60,
265 .xres = 480,
266 .yres = 640,
267 .pixclock = 41701,
268 .left_margin = 20,
269 .right_margin = 41,
270 .upper_margin = 10,
271 .lower_margin = 5,
272 .hsync_len = 20,
273 .vsync_len = 10,
274 .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
275 .vmode = FB_VMODE_NONINTERLACED,
276 .flag = 0,
277 },
278};
279
280static struct ipu_platform_data mx3_ipu_data = {
281 .irq_base = MXC_IPU_IRQ_START,
282};
283
afa77ef3 284static struct mx3fb_platform_data mx3fb_pdata __initdata = {
e42010e0
AP		 285 .name = "Epson-VGA",
286 .mode = fb_modedb,
287 .num_modes = ARRAY_SIZE(fb_modedb),
288};
289
290/* LCD */
291static struct l4f00242t03_pdata mx31_3ds_l4f00242t03_pdata = {
292 .reset_gpio = IOMUX_TO_GPIO(MX31_PIN_LCS1),
293 .data_enable_gpio = IOMUX_TO_GPIO(MX31_PIN_SER_RS),
0ce88b34
AP		 294};
295
296/*
297 * Support for SD card slot in personality board
298 */
299#define MX31_3DS_GPIO_SDHC1_CD IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)
300#define MX31_3DS_GPIO_SDHC1_BE IOMUX_TO_GPIO(MX31_PIN_GPIO3_0)
301
302static struct gpio mx31_3ds_sdhc1_gpios[] = {
303 { MX31_3DS_GPIO_SDHC1_CD, GPIOF_IN, "sdhc1-card-detect" },
304 { MX31_3DS_GPIO_SDHC1_BE, GPIOF_OUT_INIT_LOW, "sdhc1-bus-en" },
305};
306
307static int mx31_3ds_sdhc1_init(struct device *dev,
308 irq_handler_t detect_irq,
309 void *data)
310{
311 int ret;
312
313 ret = gpio_request_array(mx31_3ds_sdhc1_gpios,
314 ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
315 if (ret) {
316 pr_warning("Unable to request the SD/MMC GPIOs.\n");
317 return ret;
318 }
319
320 ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
321 detect_irq, IRQF_DISABLED |
322 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
323 "sdhc1-detect", data);
324 if (ret) {
325 pr_warning("Unable to request the SD/MMC card-detect IRQ.\n");
326 goto gpio_free;
327 }
328
329 return 0;
330
331gpio_free:
332 gpio_free_array(mx31_3ds_sdhc1_gpios,
333 ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
334 return ret;
335}
336
337static void mx31_3ds_sdhc1_exit(struct device *dev, void *data)
338{
339 free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO3_1), data);
340 gpio_free_array(mx31_3ds_sdhc1_gpios,
341 ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
342}
343
344static void mx31_3ds_sdhc1_setpower(struct device *dev, unsigned int vdd)
345{
346 /*
347 * While the voltage stuff is done by the driver, activate the
348 * Buffer Enable Pin only if there is a card in slot to fix the card
349 * voltage issue caused by bi-directional chip TXB0108 on 3Stack.
350 * Done here because at this stage we have for sure a debounced value
351 * of the presence of the card, showed by the value of vdd.
352 * 7 == ilog2(MMC_VDD_165_195)
353 */
354 if (vdd > 7)
355 gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 1);
356 else
357 gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 0);
358}
359
360static struct imxmmc_platform_data sdhc1_pdata = {
361 .init = mx31_3ds_sdhc1_init,
362 .exit = mx31_3ds_sdhc1_exit,
363 .setpower = mx31_3ds_sdhc1_setpower,
54c1f636
AP		 364};
365
366/*
367 * Matrix keyboard
368 */
369
370static const uint32_t mx31_3ds_keymap[] = {
371 KEY(0, 0, KEY_UP),
372 KEY(0, 1, KEY_DOWN),
373 KEY(1, 0, KEY_RIGHT),
374 KEY(1, 1, KEY_LEFT),
375 KEY(1, 2, KEY_ENTER),
376 KEY(2, 0, KEY_F6),
377 KEY(2, 1, KEY_F8),
378 KEY(2, 2, KEY_F9),
379 KEY(2, 3, KEY_F10),
380};
381
d690b4c4 382static const struct matrix_keymap_data mx31_3ds_keymap_data __initconst = {
54c1f636
AP		 383 .keymap = mx31_3ds_keymap,
384 .keymap_size = ARRAY_SIZE(mx31_3ds_keymap),
ae7a3f13
AP		 385};
386
387/* Regulators */
388static struct regulator_init_data pwgtx_init = {
389 .constraints = {
390 .boot_on = 1,
391 .always_on = 1,
392 },
393};
394
0d95b75e
FE		 395static struct regulator_init_data gpo_init = {
396 .constraints = {
397 .boot_on = 1,
398 .always_on = 1,
399 }
400};
401
0ce88b34
AP		 402static struct regulator_consumer_supply vmmc2_consumers[] = {
403 REGULATOR_SUPPLY("vmmc", "mxc-mmc.0"),
404};
405
406static struct regulator_init_data vmmc2_init = {
407 .constraints = {
408 .min_uV = 3000000,
409 .max_uV = 3000000,
410 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
411 REGULATOR_CHANGE_STATUS,
412 },
413 .num_consumer_supplies = ARRAY_SIZE(vmmc2_consumers),
414 .consumer_supplies = vmmc2_consumers,
415};
416
e42010e0 417static struct regulator_consumer_supply vmmc1_consumers[] = {
0556dc34 418 REGULATOR_SUPPLY("vcore", "spi0.0"),
164f7b52 419 REGULATOR_SUPPLY("cmos_2v8", "soc-camera-pdrv.0"),
e42010e0
AP		 420};
421
422static struct regulator_init_data vmmc1_init = {
423 .constraints = {
424 .min_uV = 2800000,
425 .max_uV = 2800000,
426 .apply_uV = 1,
427 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
428 REGULATOR_CHANGE_STATUS,
429 },
430 .num_consumer_supplies = ARRAY_SIZE(vmmc1_consumers),
431 .consumer_supplies = vmmc1_consumers,
432};
433
434static struct regulator_consumer_supply vgen_consumers[] = {
0556dc34 435 REGULATOR_SUPPLY("vdd", "spi0.0"),
e42010e0
AP		 436};
437
438static struct regulator_init_data vgen_init = {
439 .constraints = {
440 .min_uV = 1800000,
441 .max_uV = 1800000,
442 .apply_uV = 1,
443 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
444 REGULATOR_CHANGE_STATUS,
445 },
446 .num_consumer_supplies = ARRAY_SIZE(vgen_consumers),
447 .consumer_supplies = vgen_consumers,
448};
449
164f7b52
AP		 450static struct regulator_consumer_supply vvib_consumers[] = {
451 REGULATOR_SUPPLY("cmos_vcore", "soc-camera-pdrv.0"),
452};
453
454static struct regulator_init_data vvib_init = {
455 .constraints = {
456 .min_uV = 1300000,
457 .max_uV = 1300000,
458 .apply_uV = 1,
459 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
460 REGULATOR_CHANGE_STATUS,
461 },
462 .num_consumer_supplies = ARRAY_SIZE(vvib_consumers),
463 .consumer_supplies = vvib_consumers,
464};
465
5836372e 466static struct mc13xxx_regulator_init_data mx31_3ds_regulators[] = {
ae7a3f13 467 {
57c78e35 468 .id = MC13783_REG_PWGT1SPI, /* Power Gate for ARM core. */
ae7a3f13
AP		 469 .init_data = &pwgtx_init,
470 }, {
57c78e35 471 .id = MC13783_REG_PWGT2SPI, /* Power Gate for L2 Cache. */
ae7a3f13 472 .init_data = &pwgtx_init,
0d95b75e
FE		 473 }, {
474
c97b7393 475 .id = MC13783_REG_GPO1, /* Turn on 1.8V */
0d95b75e
FE		 476 .init_data = &gpo_init,
477 }, {
c97b7393 478 .id = MC13783_REG_GPO3, /* Turn on 3.3V */
0d95b75e 479 .init_data = &gpo_init,
0ce88b34
AP		 480 }, {
481 .id = MC13783_REG_VMMC2, /* Power MMC/SD, WiFi/Bluetooth. */
482 .init_data = &vmmc2_init,
e42010e0
AP		 483 }, {
484 .id = MC13783_REG_VMMC1, /* Power LCD, CMOS, FM, GPS, Accel. */
485 .init_data = &vmmc1_init,
486 }, {
487 .id = MC13783_REG_VGEN, /* Power LCD */
488 .init_data = &vgen_init,
164f7b52
AP		 489 }, {
490 .id = MC13783_REG_VVIB, /* Power CMOS */
491 .init_data = &vvib_init,
ae7a3f13
AP		 492 },
493};
494
495/* MC13783 */
5fb86e5d
PR		 496static struct mc13xxx_codec_platform_data mx31_3ds_codec = {
497 .dac_ssi_port = MC13783_SSI1_PORT,
498 .adc_ssi_port = MC13783_SSI1_PORT,
499};
500
4ec1b54c
AS		 501static struct mc13xxx_platform_data mc13783_pdata = {
502 .regulators = {
503 .regulators = mx31_3ds_regulators,
504 .num_regulators = ARRAY_SIZE(mx31_3ds_regulators),
505 },
5fb86e5d
PR		 506 .codec = &mx31_3ds_codec,
507 .flags = MC13XXX_USE_TOUCHSCREEN | MC13XXX_USE_RTC | MC13XXX_USE_CODEC,
508
509};
510
511static struct imx_ssi_platform_data mx31_3ds_ssi_pdata = {
512 .flags = IMX_SSI_DMA | IMX_SSI_NET,
a1ac4424
AP		 513};
514
515/* SPI */
e42010e0
AP		 516static int spi0_internal_chipselect[] = {
517 MXC_SPI_CS(2),
518};
519
520static const struct spi_imx_master spi0_pdata __initconst = {
521 .chipselect = spi0_internal_chipselect,
522 .num_chipselect = ARRAY_SIZE(spi0_internal_chipselect),
523};
524
a1ac4424
AP		 525static int spi1_internal_chipselect[] = {
526 MXC_SPI_CS(0),
527 MXC_SPI_CS(2),
528};
529
06606ff1 530static const struct spi_imx_master spi1_pdata __initconst = {
a1ac4424
AP		 531 .chipselect = spi1_internal_chipselect,
532 .num_chipselect = ARRAY_SIZE(spi1_internal_chipselect),
63d97667
VL		 533};
534
ae7a3f13
AP		 535static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
536 {
537 .modalias = "mc13783",
538 .max_speed_hz = 1000000,
539 .bus_num = 1,
540 .chip_select = 1, /* SS2 */
541 .platform_data = &mc13783_pdata,
542 .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
543 .mode = SPI_CS_HIGH,
e42010e0
AP		 544 }, {
545 .modalias = "l4f00242t03",
546 .max_speed_hz = 5000000,
547 .bus_num = 0,
548 .chip_select = 0, /* SS2 */
549 .platform_data = &mx31_3ds_l4f00242t03_pdata,
ae7a3f13
AP		 550 },
551};
552
a1b67b95
AP		 553/*
554 * NAND Flash
555 */
a2ceeef5
UKK		 556static const struct mxc_nand_platform_data
557mx31_3ds_nand_board_info __initconst = {
a1b67b95
AP		 558 .width = 1,
559 .hw_ecc = 1,
5328ecbb 560#ifdef CONFIG_MACH_MX31_3DS_MXC_NAND_USE_BBT
a1b67b95
AP		 561 .flash_bbt = 1,
562#endif
563};
564
a2ef4562
ML		 565/*
566 * USB OTG
567 */
568
569#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
570 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
571
572#define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR)
0d95b75e 573#define USBH2_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_BYP)
a2ef4562 574
41f63475 575static int mx31_3ds_usbotg_init(void)
a2ef4562 576{
41f63475
FE		 577 int err;
578
a2ef4562
ML		 579 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
580 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
581 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
582 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG);
583 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG);
584 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG);
585 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG);
586 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG);
587 mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG);
588 mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG);
589 mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
590 mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
591
41f63475
FE		 592 err = gpio_request(USBOTG_RST_B, "otgusb-reset");
593 if (err) {
594 pr_err("Failed to request the USB OTG reset gpio\n");
595 return err;
596 }
597
598 err = gpio_direction_output(USBOTG_RST_B, 0);
599 if (err) {
600 pr_err("Failed to drive the USB OTG reset gpio\n");
601 goto usbotg_free_reset;
602 }
603
a2ef4562
ML		 604 mdelay(1);
605 gpio_set_value(USBOTG_RST_B, 1);
41f63475
FE		 606 return 0;
607
608usbotg_free_reset:
609 gpio_free(USBOTG_RST_B);
610 return err;
a2ef4562
ML		 611}
612
4bd597b6
SH		 613static int mx31_3ds_otg_init(struct platform_device *pdev)
614{
615 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
616}
617
618static int mx31_3ds_host2_init(struct platform_device *pdev)
0d95b75e
FE		 619{
620 int err;
621
622 mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
623 mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
624 mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
625 mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
626 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
627 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
628 mxc_iomux_set_pad(MX31_PIN_PC_VS2, USB_PAD_CFG);
629 mxc_iomux_set_pad(MX31_PIN_PC_BVD1, USB_PAD_CFG);
630 mxc_iomux_set_pad(MX31_PIN_PC_BVD2, USB_PAD_CFG);
631 mxc_iomux_set_pad(MX31_PIN_PC_RST, USB_PAD_CFG);
632 mxc_iomux_set_pad(MX31_PIN_IOIS16, USB_PAD_CFG);
633 mxc_iomux_set_pad(MX31_PIN_PC_RW_B, USB_PAD_CFG);
634
635 err = gpio_request(USBH2_RST_B, "usbh2-reset");
636 if (err) {
637 pr_err("Failed to request the USB Host 2 reset gpio\n");
638 return err;
639 }
640
641 err = gpio_direction_output(USBH2_RST_B, 0);
642 if (err) {
643 pr_err("Failed to drive the USB Host 2 reset gpio\n");
644 goto usbotg_free_reset;
645 }
646
647 mdelay(1);
648 gpio_set_value(USBH2_RST_B, 1);
4bd597b6
SH		 649
650 mdelay(10);
651
652 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
0d95b75e
FE		 653
654usbotg_free_reset:
655 gpio_free(USBH2_RST_B);
656 return err;
657}
658
1c50e672 659static struct mxc_usbh_platform_data otg_pdata __initdata = {
4bd597b6 660 .init = mx31_3ds_otg_init,
1c50e672 661 .portsc = MXC_EHCI_MODE_ULPI,
1c50e672 662};
0d95b75e
FE		 663
664static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
665 .init = mx31_3ds_host2_init,
666 .portsc = MXC_EHCI_MODE_ULPI,
0d95b75e 667};
1c50e672 668
9e1dde33 669static const struct fsl_usb2_platform_data usbotg_pdata __initconst = {
a2ef4562
ML		 670 .operating_mode = FSL_USB2_DR_DEVICE,
671 .phy_mode = FSL_USB2_PHY_ULPI,
672};
673
33a264dd 674static bool otg_mode_host __initdata;
1c50e672
FE		 675
676static int __init mx31_3ds_otg_mode(char *options)
677{
678 if (!strcmp(options, "host"))
33a264dd 679 otg_mode_host = true;
1c50e672 680 else if (!strcmp(options, "device"))
33a264dd 681 otg_mode_host = false;
1c50e672
FE		 682 else
683 pr_info("otg_mode neither \"host\" nor \"device\". "
684 "Defaulting to device\n");
33a264dd 685 return 1;
1c50e672
FE		 686}
687__setup("otg_mode=", mx31_3ds_otg_mode);
688
16cf5c41 689static const struct imxuart_platform_data uart_pdata __initconst = {
153fa1d8
ML		 690 .flags = IMXUART_HAVE_RTSCTS,
691};
1553a1ec 692
3d943024
FE		 693static const struct imxi2c_platform_data mx31_3ds_i2c0_data __initconst = {
694 .bitrate = 100000,
695};
696
164f7b52
AP		 697static struct platform_device *devices[] __initdata = {
698 &mx31_3ds_ov2640,
699};
700
e134fb2b 701static void __init mx31_3ds_init(void)
1553a1ec 702{
164f7b52
AP		 703 int ret;
704
b78d8e59
SG		 705 imx31_soc_init();
706
b2a08e3e
FE		 707 /* Configure SPI1 IOMUX */
708 mxc_iomux_set_gpr(MUX_PGP_CSPI_BB, true);
709
11a332ad
AP		 710 mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
711 "mx31_3ds");
153fa1d8 712
16cf5c41 713 imx31_add_imx_uart0(&uart_pdata);
a2ceeef5 714 imx31_add_mxc_nand(&mx31_3ds_nand_board_info);
ae7a3f13 715
4a74bddc 716 imx31_add_spi_imx1(&spi1_pdata);
ae7a3f13
AP		 717 spi_register_board_info(mx31_3ds_spi_devs,
718 ARRAY_SIZE(mx31_3ds_spi_devs));
135cad36 719
164f7b52
AP		 720 platform_add_devices(devices, ARRAY_SIZE(devices));
721
d690b4c4 722 imx31_add_imx_keypad(&mx31_3ds_keymap_data);
54c1f636 723
a2ef4562 724 mx31_3ds_usbotg_init();
1c50e672 725 if (otg_mode_host) {
48f6b099
SH		 726 otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
727 ULPI_OTG_DRVVBUS_EXT);
728 if (otg_pdata.otg)
729 imx31_add_mxc_ehci_otg(&otg_pdata);
1c50e672 730 }
48f6b099
SH		 731 usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
732 ULPI_OTG_DRVVBUS_EXT);
733 if (usbh2_pdata.otg)
734 imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
735
1c50e672
FE		 736 if (!otg_mode_host)
737 imx31_add_fsl_usb2_udc(&usbotg_pdata);
a2ef4562 738
b8be7b9a
RP		 739 if (mxc_expio_init(MX31_CS5_BASE_ADDR, EXPIO_PARENT_INT))
740 printk(KERN_WARNING "Init of the debug board failed, all "
741 "devices on the debug board are unusable.\n");
bec31a85 742 imx31_add_imx2_wdt();
3d943024 743 imx31_add_imx_i2c0(&mx31_3ds_i2c0_data);
0ce88b34 744 imx31_add_mxc_mmc(0, &sdhc1_pdata);
e42010e0
AP		 745
746 imx31_add_spi_imx0(&spi0_pdata);
afa77ef3
UKK		 747 imx31_add_ipu_core(&mx3_ipu_data);
748 imx31_add_mx3_sdc_fb(&mx3fb_pdata);
164f7b52
AP		 749
750 /* CSI */
751 /* Camera power: default - off */
752 ret = gpio_request_array(mx31_3ds_camera_gpios,
753 ARRAY_SIZE(mx31_3ds_camera_gpios));
754 if (ret) {
755 pr_err("Failed to request camera gpios");
756 iclink_ov2640.power = NULL;
757 }
758
afa77ef3 759 mx31_3ds_init_camera();
5fb86e5d
PR		 760
761 imx31_add_imx_ssi(0, &mx31_3ds_ssi_pdata);
762
763 imx_add_platform_device("imx_mc13783", 0, NULL, 0, NULL, 0);
1553a1ec
FE		 764}
765
11a332ad 766static void __init mx31_3ds_timer_init(void)
1553a1ec 767{
30c730f8 768 mx31_clocks_init(26000000);
1553a1ec
FE		 769}
770
11a332ad
AP		 771static struct sys_timer mx31_3ds_timer = {
772 .init = mx31_3ds_timer_init,
1553a1ec
FE		 773};
774
164f7b52
AP		 775static void __init mx31_3ds_reserve(void)
776{
777 /* reserve MX31_3DS_CAMERA_BUF_SIZE bytes for mx3-camera */
716a3dc2 778 mx3_camera_base = arm_memblock_steal(MX31_3DS_CAMERA_BUF_SIZE,
164f7b52 779 MX31_3DS_CAMERA_BUF_SIZE);
164f7b52
AP		 780}
781
1553a1ec
FE		 782MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
783 /* Maintainer: Freescale Semiconductor, Inc. */
dc8f1907 784 .atag_offset = 0x100,
97976e22
UKK		 785 .map_io = mx31_map_io,
786 .init_early = imx31_init_early,
787 .init_irq = mx31_init_irq,
ffa2ea3f 788 .handle_irq = imx31_handle_irq,
97976e22 789 .timer = &mx31_3ds_timer,
e134fb2b 790 .init_machine = mx31_3ds_init,
164f7b52 791 .reserve = mx31_3ds_reserve,
65ea7884 792 .restart = mxc_restart,
1553a1ec 793MACHINE_END
Linux kernel - Deliverables
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