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dcb: Add missing error check in dcb_ieee_set()
[deliverable/linux.git] / arch / arm / mach-imx / mach-mx31_3ds.c
CommitLineData
1553a1ec
FE		 1/*
2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
1553a1ec
FE		 13 */
14
a2ef4562 15#include <linux/delay.h>
1553a1ec
FE		 16#include <linux/types.h>
17#include <linux/init.h>
18#include <linux/clk.h>
19#include <linux/irq.h>
135cad36 20#include <linux/gpio.h>
2b0c3677 21#include <linux/platform_device.h>
ae7a3f13
AP		 22#include <linux/mfd/mc13783.h>
23#include <linux/spi/spi.h>
e42010e0 24#include <linux/spi/l4f00242t03.h>
ae7a3f13 25#include <linux/regulator/machine.h>
1c50e672
FE		 26#include <linux/usb/otg.h>
27#include <linux/usb/ulpi.h>
164f7b52
AP		 28#include <linux/memblock.h>
29
30#include <media/soc_camera.h>
1553a1ec
FE		 31
32#include <mach/hardware.h>
33#include <asm/mach-types.h>
34#include <asm/mach/arch.h>
35#include <asm/mach/time.h>
36#include <asm/memory.h>
37#include <asm/mach/map.h>
38#include <mach/common.h>
1553a1ec 39#include <mach/iomux-mx3.h>
c5d38f08 40#include <mach/3ds_debugboard.h>
1c50e672 41#include <mach/ulpi.h>
a2ceeef5
UKK		 42
43#include "devices-imx31.h"
1553a1ec 44
b396dc45
UKK		 45/* CPLD IRQ line for external uart, external ethernet etc */
46#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
47
11a332ad 48static int mx31_3ds_pins[] = {
153fa1d8 49 /* UART1 */
63d97667
VL		 50 MX31_PIN_CTS1__CTS1,
51 MX31_PIN_RTS1__RTS1,
52 MX31_PIN_TXD1__TXD1,
135cad36
ML		 53 MX31_PIN_RXD1__RXD1,
54 IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO),
e42010e0
AP		 55 /*SPI0*/
56 MX31_PIN_CSPI1_SCLK__SCLK,
57 MX31_PIN_CSPI1_MOSI__MOSI,
58 MX31_PIN_CSPI1_MISO__MISO,
59 MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
60 MX31_PIN_CSPI1_SS2__SS2, /* CS for LCD */
a1ac4424
AP		 61 /* SPI 1 */
62 MX31_PIN_CSPI2_SCLK__SCLK,
63 MX31_PIN_CSPI2_MOSI__MOSI,
64 MX31_PIN_CSPI2_MISO__MISO,
65 MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
66 MX31_PIN_CSPI2_SS0__SS0,
67 MX31_PIN_CSPI2_SS2__SS2, /*CS for MC13783 */
ae7a3f13
AP		 68 /* MC13783 IRQ */
69 IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO),
a2ef4562
ML		 70 /* USB OTG reset */
71 IOMUX_MODE(MX31_PIN_USB_PWR, IOMUX_CONFIG_GPIO),
72 /* USB OTG */
73 MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
74 MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
75 MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
76 MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
77 MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
78 MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
79 MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
80 MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
81 MX31_PIN_USBOTG_CLK__USBOTG_CLK,
82 MX31_PIN_USBOTG_DIR__USBOTG_DIR,
83 MX31_PIN_USBOTG_NXT__USBOTG_NXT,
84 MX31_PIN_USBOTG_STP__USBOTG_STP,
54c1f636
AP		 85 /*Keyboard*/
86 MX31_PIN_KEY_ROW0_KEY_ROW0,
87 MX31_PIN_KEY_ROW1_KEY_ROW1,
88 MX31_PIN_KEY_ROW2_KEY_ROW2,
89 MX31_PIN_KEY_COL0_KEY_COL0,
90 MX31_PIN_KEY_COL1_KEY_COL1,
91 MX31_PIN_KEY_COL2_KEY_COL2,
92 MX31_PIN_KEY_COL3_KEY_COL3,
0d95b75e
FE		 93 /* USB Host 2 */
94 IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
95 IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
96 IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
97 IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
98 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
99 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
100 IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT1),
101 IOMUX_MODE(MX31_PIN_PC_BVD1, IOMUX_CONFIG_ALT1),
102 IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT1),
103 IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT1),
104 IOMUX_MODE(MX31_PIN_IOIS16, IOMUX_CONFIG_ALT1),
105 IOMUX_MODE(MX31_PIN_PC_RW_B, IOMUX_CONFIG_ALT1),
106 /* USB Host2 reset */
107 IOMUX_MODE(MX31_PIN_USB_BYP, IOMUX_CONFIG_GPIO),
3d943024
FE		 108 /* I2C1 */
109 MX31_PIN_I2C_CLK__I2C1_SCL,
110 MX31_PIN_I2C_DAT__I2C1_SDA,
0ce88b34
AP		 111 /* SDHC1 */
112 MX31_PIN_SD1_DATA3__SD1_DATA3,
113 MX31_PIN_SD1_DATA2__SD1_DATA2,
114 MX31_PIN_SD1_DATA1__SD1_DATA1,
115 MX31_PIN_SD1_DATA0__SD1_DATA0,
116 MX31_PIN_SD1_CLK__SD1_CLK,
117 MX31_PIN_SD1_CMD__SD1_CMD,
118 MX31_PIN_GPIO3_1__GPIO3_1, /* Card detect */
119 MX31_PIN_GPIO3_0__GPIO3_0, /* OE */
e42010e0
AP		 120 /* Framebuffer */
121 MX31_PIN_LD0__LD0,
122 MX31_PIN_LD1__LD1,
123 MX31_PIN_LD2__LD2,
124 MX31_PIN_LD3__LD3,
125 MX31_PIN_LD4__LD4,
126 MX31_PIN_LD5__LD5,
127 MX31_PIN_LD6__LD6,
128 MX31_PIN_LD7__LD7,
129 MX31_PIN_LD8__LD8,
130 MX31_PIN_LD9__LD9,
131 MX31_PIN_LD10__LD10,
132 MX31_PIN_LD11__LD11,
133 MX31_PIN_LD12__LD12,
134 MX31_PIN_LD13__LD13,
135 MX31_PIN_LD14__LD14,
136 MX31_PIN_LD15__LD15,
137 MX31_PIN_LD16__LD16,
138 MX31_PIN_LD17__LD17,
139 MX31_PIN_VSYNC3__VSYNC3,
140 MX31_PIN_HSYNC__HSYNC,
141 MX31_PIN_FPSHIFT__FPSHIFT,
142 MX31_PIN_CONTRAST__CONTRAST,
164f7b52
AP		 143 /* CSI */
144 MX31_PIN_CSI_D6__CSI_D6,
145 MX31_PIN_CSI_D7__CSI_D7,
146 MX31_PIN_CSI_D8__CSI_D8,
147 MX31_PIN_CSI_D9__CSI_D9,
148 MX31_PIN_CSI_D10__CSI_D10,
149 MX31_PIN_CSI_D11__CSI_D11,
150 MX31_PIN_CSI_D12__CSI_D12,
151 MX31_PIN_CSI_D13__CSI_D13,
152 MX31_PIN_CSI_D14__CSI_D14,
153 MX31_PIN_CSI_D15__CSI_D15,
154 MX31_PIN_CSI_HSYNC__CSI_HSYNC,
155 MX31_PIN_CSI_MCLK__CSI_MCLK,
156 MX31_PIN_CSI_PIXCLK__CSI_PIXCLK,
157 MX31_PIN_CSI_VSYNC__CSI_VSYNC,
158 MX31_PIN_CSI_D5__GPIO3_5, /* CMOS PWDN */
159 IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_GPIO), /* CMOS reset */
160};
161
162/*
163 * Camera support
164 */
165static phys_addr_t mx3_camera_base __initdata;
166#define MX31_3DS_CAMERA_BUF_SIZE SZ_8M
167
168#define MX31_3DS_GPIO_CAMERA_PW IOMUX_TO_GPIO(MX31_PIN_CSI_D5)
169#define MX31_3DS_GPIO_CAMERA_RST IOMUX_TO_GPIO(MX31_PIN_RI_DTE1)
170
171static struct gpio mx31_3ds_camera_gpios[] = {
172 { MX31_3DS_GPIO_CAMERA_PW, GPIOF_OUT_INIT_HIGH, "camera-power" },
173 { MX31_3DS_GPIO_CAMERA_RST, GPIOF_OUT_INIT_HIGH, "camera-reset" },
174};
175
afa77ef3
UKK		 176static const struct mx3_camera_pdata mx31_3ds_camera_pdata __initconst = {
177 .flags = MX3_CAMERA_DATAWIDTH_10,
178 .mclk_10khz = 2600,
179};
180
181static int __init mx31_3ds_init_camera(void)
164f7b52 182{
afa77ef3
UKK		 183 int dma, ret = -ENOMEM;
184 struct platform_device *pdev =
185 imx31_alloc_mx3_camera(&mx31_3ds_camera_pdata);
186
187 if (IS_ERR(pdev))
188 return PTR_ERR(pdev);
164f7b52
AP		 189
190 if (!mx3_camera_base)
afa77ef3 191 goto err;
164f7b52 192
afa77ef3 193 dma = dma_declare_coherent_memory(&pdev->dev,
164f7b52
AP		 194 mx3_camera_base, mx3_camera_base,
195 MX31_3DS_CAMERA_BUF_SIZE,
196 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
197
198 if (!(dma & DMA_MEMORY_MAP))
afa77ef3 199 goto err;
164f7b52 200
afa77ef3
UKK		 201 ret = platform_device_add(pdev);
202 if (ret)
203err:
204 platform_device_put(pdev);
205
206 return ret;
164f7b52
AP		 207}
208
209static int mx31_3ds_camera_power(struct device *dev, int on)
210{
211 /* enable or disable the camera */
212 pr_debug("%s: %s the camera\n", __func__, on ? "ENABLE" : "DISABLE");
213 gpio_set_value(MX31_3DS_GPIO_CAMERA_PW, on ? 0 : 1);
214
215 if (!on)
216 goto out;
217
218 /* If enabled, give a reset impulse */
219 gpio_set_value(MX31_3DS_GPIO_CAMERA_RST, 0);
220 msleep(20);
221 gpio_set_value(MX31_3DS_GPIO_CAMERA_RST, 1);
222 msleep(100);
223
224out:
225 return 0;
226}
227
228static struct i2c_board_info mx31_3ds_i2c_camera = {
229 I2C_BOARD_INFO("ov2640", 0x30),
230};
231
232static struct regulator_bulk_data mx31_3ds_camera_regs[] = {
233 { .supply = "cmos_vcore" },
234 { .supply = "cmos_2v8" },
235};
236
237static struct soc_camera_link iclink_ov2640 = {
238 .bus_id = 0,
239 .board_info = &mx31_3ds_i2c_camera,
240 .i2c_adapter_id = 0,
241 .power = mx31_3ds_camera_power,
242 .regulators = mx31_3ds_camera_regs,
243 .num_regulators = ARRAY_SIZE(mx31_3ds_camera_regs),
244};
245
246static struct platform_device mx31_3ds_ov2640 = {
247 .name = "soc-camera-pdrv",
248 .id = 0,
249 .dev = {
250 .platform_data = &iclink_ov2640,
251 },
252};
253
e42010e0
AP		 254/*
255 * FB support
256 */
257static const struct fb_videomode fb_modedb[] = {
258 { /* 480x640 @ 60 Hz */
259 .name = "Epson-VGA",
260 .refresh = 60,
261 .xres = 480,
262 .yres = 640,
263 .pixclock = 41701,
264 .left_margin = 20,
265 .right_margin = 41,
266 .upper_margin = 10,
267 .lower_margin = 5,
268 .hsync_len = 20,
269 .vsync_len = 10,
270 .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
271 .vmode = FB_VMODE_NONINTERLACED,
272 .flag = 0,
273 },
274};
275
276static struct ipu_platform_data mx3_ipu_data = {
277 .irq_base = MXC_IPU_IRQ_START,
278};
279
afa77ef3 280static struct mx3fb_platform_data mx3fb_pdata __initdata = {
e42010e0
AP		 281 .name = "Epson-VGA",
282 .mode = fb_modedb,
283 .num_modes = ARRAY_SIZE(fb_modedb),
284};
285
286/* LCD */
287static struct l4f00242t03_pdata mx31_3ds_l4f00242t03_pdata = {
288 .reset_gpio = IOMUX_TO_GPIO(MX31_PIN_LCS1),
289 .data_enable_gpio = IOMUX_TO_GPIO(MX31_PIN_SER_RS),
290 .core_supply = "lcd_2v8",
291 .io_supply = "vdd_lcdio",
0ce88b34
AP		 292};
293
294/*
295 * Support for SD card slot in personality board
296 */
297#define MX31_3DS_GPIO_SDHC1_CD IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)
298#define MX31_3DS_GPIO_SDHC1_BE IOMUX_TO_GPIO(MX31_PIN_GPIO3_0)
299
300static struct gpio mx31_3ds_sdhc1_gpios[] = {
301 { MX31_3DS_GPIO_SDHC1_CD, GPIOF_IN, "sdhc1-card-detect" },
302 { MX31_3DS_GPIO_SDHC1_BE, GPIOF_OUT_INIT_LOW, "sdhc1-bus-en" },
303};
304
305static int mx31_3ds_sdhc1_init(struct device *dev,
306 irq_handler_t detect_irq,
307 void *data)
308{
309 int ret;
310
311 ret = gpio_request_array(mx31_3ds_sdhc1_gpios,
312 ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
313 if (ret) {
314 pr_warning("Unable to request the SD/MMC GPIOs.\n");
315 return ret;
316 }
317
318 ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
319 detect_irq, IRQF_DISABLED |
320 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
321 "sdhc1-detect", data);
322 if (ret) {
323 pr_warning("Unable to request the SD/MMC card-detect IRQ.\n");
324 goto gpio_free;
325 }
326
327 return 0;
328
329gpio_free:
330 gpio_free_array(mx31_3ds_sdhc1_gpios,
331 ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
332 return ret;
333}
334
335static void mx31_3ds_sdhc1_exit(struct device *dev, void *data)
336{
337 free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO3_1), data);
338 gpio_free_array(mx31_3ds_sdhc1_gpios,
339 ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
340}
341
342static void mx31_3ds_sdhc1_setpower(struct device *dev, unsigned int vdd)
343{
344 /*
345 * While the voltage stuff is done by the driver, activate the
346 * Buffer Enable Pin only if there is a card in slot to fix the card
347 * voltage issue caused by bi-directional chip TXB0108 on 3Stack.
348 * Done here because at this stage we have for sure a debounced value
349 * of the presence of the card, showed by the value of vdd.
350 * 7 == ilog2(MMC_VDD_165_195)
351 */
352 if (vdd > 7)
353 gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 1);
354 else
355 gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 0);
356}
357
358static struct imxmmc_platform_data sdhc1_pdata = {
359 .init = mx31_3ds_sdhc1_init,
360 .exit = mx31_3ds_sdhc1_exit,
361 .setpower = mx31_3ds_sdhc1_setpower,
54c1f636
AP		 362};
363
364/*
365 * Matrix keyboard
366 */
367
368static const uint32_t mx31_3ds_keymap[] = {
369 KEY(0, 0, KEY_UP),
370 KEY(0, 1, KEY_DOWN),
371 KEY(1, 0, KEY_RIGHT),
372 KEY(1, 1, KEY_LEFT),
373 KEY(1, 2, KEY_ENTER),
374 KEY(2, 0, KEY_F6),
375 KEY(2, 1, KEY_F8),
376 KEY(2, 2, KEY_F9),
377 KEY(2, 3, KEY_F10),
378};
379
d690b4c4 380static const struct matrix_keymap_data mx31_3ds_keymap_data __initconst = {
54c1f636
AP		 381 .keymap = mx31_3ds_keymap,
382 .keymap_size = ARRAY_SIZE(mx31_3ds_keymap),
ae7a3f13
AP		 383};
384
385/* Regulators */
386static struct regulator_init_data pwgtx_init = {
387 .constraints = {
388 .boot_on = 1,
389 .always_on = 1,
390 },
391};
392
0d95b75e
FE		 393static struct regulator_init_data gpo_init = {
394 .constraints = {
395 .boot_on = 1,
396 .always_on = 1,
397 }
398};
399
0ce88b34
AP		 400static struct regulator_consumer_supply vmmc2_consumers[] = {
401 REGULATOR_SUPPLY("vmmc", "mxc-mmc.0"),
402};
403
404static struct regulator_init_data vmmc2_init = {
405 .constraints = {
406 .min_uV = 3000000,
407 .max_uV = 3000000,
408 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
409 REGULATOR_CHANGE_STATUS,
410 },
411 .num_consumer_supplies = ARRAY_SIZE(vmmc2_consumers),
412 .consumer_supplies = vmmc2_consumers,
413};
414
e42010e0
AP		 415static struct regulator_consumer_supply vmmc1_consumers[] = {
416 REGULATOR_SUPPLY("lcd_2v8", NULL),
164f7b52 417 REGULATOR_SUPPLY("cmos_2v8", "soc-camera-pdrv.0"),
e42010e0
AP		 418};
419
420static struct regulator_init_data vmmc1_init = {
421 .constraints = {
422 .min_uV = 2800000,
423 .max_uV = 2800000,
424 .apply_uV = 1,
425 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
426 REGULATOR_CHANGE_STATUS,
427 },
428 .num_consumer_supplies = ARRAY_SIZE(vmmc1_consumers),
429 .consumer_supplies = vmmc1_consumers,
430};
431
432static struct regulator_consumer_supply vgen_consumers[] = {
433 REGULATOR_SUPPLY("vdd_lcdio", NULL),
434};
435
436static struct regulator_init_data vgen_init = {
437 .constraints = {
438 .min_uV = 1800000,
439 .max_uV = 1800000,
440 .apply_uV = 1,
441 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
442 REGULATOR_CHANGE_STATUS,
443 },
444 .num_consumer_supplies = ARRAY_SIZE(vgen_consumers),
445 .consumer_supplies = vgen_consumers,
446};
447
164f7b52
AP		 448static struct regulator_consumer_supply vvib_consumers[] = {
449 REGULATOR_SUPPLY("cmos_vcore", "soc-camera-pdrv.0"),
450};
451
452static struct regulator_init_data vvib_init = {
453 .constraints = {
454 .min_uV = 1300000,
455 .max_uV = 1300000,
456 .apply_uV = 1,
457 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
458 REGULATOR_CHANGE_STATUS,
459 },
460 .num_consumer_supplies = ARRAY_SIZE(vvib_consumers),
461 .consumer_supplies = vvib_consumers,
462};
463
5836372e 464static struct mc13xxx_regulator_init_data mx31_3ds_regulators[] = {
ae7a3f13 465 {
57c78e35 466 .id = MC13783_REG_PWGT1SPI, /* Power Gate for ARM core. */
ae7a3f13
AP		 467 .init_data = &pwgtx_init,
468 }, {
57c78e35 469 .id = MC13783_REG_PWGT2SPI, /* Power Gate for L2 Cache. */
ae7a3f13 470 .init_data = &pwgtx_init,
0d95b75e
FE		 471 }, {
472
c97b7393 473 .id = MC13783_REG_GPO1, /* Turn on 1.8V */
0d95b75e
FE		 474 .init_data = &gpo_init,
475 }, {
c97b7393 476 .id = MC13783_REG_GPO3, /* Turn on 3.3V */
0d95b75e 477 .init_data = &gpo_init,
0ce88b34
AP		 478 }, {
479 .id = MC13783_REG_VMMC2, /* Power MMC/SD, WiFi/Bluetooth. */
480 .init_data = &vmmc2_init,
e42010e0
AP		 481 }, {
482 .id = MC13783_REG_VMMC1, /* Power LCD, CMOS, FM, GPS, Accel. */
483 .init_data = &vmmc1_init,
484 }, {
485 .id = MC13783_REG_VGEN, /* Power LCD */
486 .init_data = &vgen_init,
164f7b52
AP		 487 }, {
488 .id = MC13783_REG_VVIB, /* Power CMOS */
489 .init_data = &vvib_init,
ae7a3f13
AP		 490 },
491};
492
493/* MC13783 */
4ec1b54c
AS		 494static struct mc13xxx_platform_data mc13783_pdata = {
495 .regulators = {
496 .regulators = mx31_3ds_regulators,
497 .num_regulators = ARRAY_SIZE(mx31_3ds_regulators),
498 },
499 .flags = MC13783_USE_REGULATOR | MC13783_USE_TOUCHSCREEN,
a1ac4424
AP		 500};
501
502/* SPI */
e42010e0
AP		 503static int spi0_internal_chipselect[] = {
504 MXC_SPI_CS(2),
505};
506
507static const struct spi_imx_master spi0_pdata __initconst = {
508 .chipselect = spi0_internal_chipselect,
509 .num_chipselect = ARRAY_SIZE(spi0_internal_chipselect),
510};
511
a1ac4424
AP		 512static int spi1_internal_chipselect[] = {
513 MXC_SPI_CS(0),
514 MXC_SPI_CS(2),
515};
516
06606ff1 517static const struct spi_imx_master spi1_pdata __initconst = {
a1ac4424
AP		 518 .chipselect = spi1_internal_chipselect,
519 .num_chipselect = ARRAY_SIZE(spi1_internal_chipselect),
63d97667
VL		 520};
521
ae7a3f13
AP		 522static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
523 {
524 .modalias = "mc13783",
525 .max_speed_hz = 1000000,
526 .bus_num = 1,
527 .chip_select = 1, /* SS2 */
528 .platform_data = &mc13783_pdata,
529 .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
530 .mode = SPI_CS_HIGH,
e42010e0
AP		 531 }, {
532 .modalias = "l4f00242t03",
533 .max_speed_hz = 5000000,
534 .bus_num = 0,
535 .chip_select = 0, /* SS2 */
536 .platform_data = &mx31_3ds_l4f00242t03_pdata,
ae7a3f13
AP		 537 },
538};
539
a1b67b95
AP		 540/*
541 * NAND Flash
542 */
a2ceeef5
UKK		 543static const struct mxc_nand_platform_data
544mx31_3ds_nand_board_info __initconst = {
a1b67b95
AP		 545 .width = 1,
546 .hw_ecc = 1,
547#ifdef MACH_MX31_3DS_MXC_NAND_USE_BBT
548 .flash_bbt = 1,
549#endif
550};
551
a2ef4562
ML		 552/*
553 * USB OTG
554 */
555
556#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
557 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
558
559#define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR)
0d95b75e 560#define USBH2_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_BYP)
a2ef4562 561
41f63475 562static int mx31_3ds_usbotg_init(void)
a2ef4562 563{
41f63475
FE		 564 int err;
565
a2ef4562
ML		 566 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
567 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
568 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
569 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG);
570 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG);
571 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG);
572 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG);
573 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG);
574 mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG);
575 mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG);
576 mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
577 mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
578
41f63475
FE		 579 err = gpio_request(USBOTG_RST_B, "otgusb-reset");
580 if (err) {
581 pr_err("Failed to request the USB OTG reset gpio\n");
582 return err;
583 }
584
585 err = gpio_direction_output(USBOTG_RST_B, 0);
586 if (err) {
587 pr_err("Failed to drive the USB OTG reset gpio\n");
588 goto usbotg_free_reset;
589 }
590
a2ef4562
ML		 591 mdelay(1);
592 gpio_set_value(USBOTG_RST_B, 1);
41f63475
FE		 593 return 0;
594
595usbotg_free_reset:
596 gpio_free(USBOTG_RST_B);
597 return err;
a2ef4562
ML		 598}
599
4bd597b6
SH		 600static int mx31_3ds_otg_init(struct platform_device *pdev)
601{
602 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
603}
604
605static int mx31_3ds_host2_init(struct platform_device *pdev)
0d95b75e
FE		 606{
607 int err;
608
609 mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
610 mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
611 mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
612 mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
613 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
614 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
615 mxc_iomux_set_pad(MX31_PIN_PC_VS2, USB_PAD_CFG);
616 mxc_iomux_set_pad(MX31_PIN_PC_BVD1, USB_PAD_CFG);
617 mxc_iomux_set_pad(MX31_PIN_PC_BVD2, USB_PAD_CFG);
618 mxc_iomux_set_pad(MX31_PIN_PC_RST, USB_PAD_CFG);
619 mxc_iomux_set_pad(MX31_PIN_IOIS16, USB_PAD_CFG);
620 mxc_iomux_set_pad(MX31_PIN_PC_RW_B, USB_PAD_CFG);
621
622 err = gpio_request(USBH2_RST_B, "usbh2-reset");
623 if (err) {
624 pr_err("Failed to request the USB Host 2 reset gpio\n");
625 return err;
626 }
627
628 err = gpio_direction_output(USBH2_RST_B, 0);
629 if (err) {
630 pr_err("Failed to drive the USB Host 2 reset gpio\n");
631 goto usbotg_free_reset;
632 }
633
634 mdelay(1);
635 gpio_set_value(USBH2_RST_B, 1);
4bd597b6
SH		 636
637 mdelay(10);
638
639 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
0d95b75e
FE		 640
641usbotg_free_reset:
642 gpio_free(USBH2_RST_B);
643 return err;
644}
645
1c50e672 646static struct mxc_usbh_platform_data otg_pdata __initdata = {
4bd597b6 647 .init = mx31_3ds_otg_init,
1c50e672 648 .portsc = MXC_EHCI_MODE_ULPI,
1c50e672 649};
0d95b75e
FE		 650
651static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
652 .init = mx31_3ds_host2_init,
653 .portsc = MXC_EHCI_MODE_ULPI,
0d95b75e 654};
1c50e672 655
9e1dde33 656static const struct fsl_usb2_platform_data usbotg_pdata __initconst = {
a2ef4562
ML		 657 .operating_mode = FSL_USB2_DR_DEVICE,
658 .phy_mode = FSL_USB2_PHY_ULPI,
659};
660
1c50e672
FE		 661static int otg_mode_host;
662
663static int __init mx31_3ds_otg_mode(char *options)
664{
665 if (!strcmp(options, "host"))
666 otg_mode_host = 1;
667 else if (!strcmp(options, "device"))
668 otg_mode_host = 0;
669 else
670 pr_info("otg_mode neither \"host\" nor \"device\". "
671 "Defaulting to device\n");
672 return 0;
673}
674__setup("otg_mode=", mx31_3ds_otg_mode);
675
16cf5c41 676static const struct imxuart_platform_data uart_pdata __initconst = {
153fa1d8
ML		 677 .flags = IMXUART_HAVE_RTSCTS,
678};
1553a1ec 679
3d943024
FE		 680static const struct imxi2c_platform_data mx31_3ds_i2c0_data __initconst = {
681 .bitrate = 100000,
682};
683
164f7b52
AP		 684static struct platform_device *devices[] __initdata = {
685 &mx31_3ds_ov2640,
686};
687
e134fb2b 688static void __init mx31_3ds_init(void)
1553a1ec 689{
164f7b52
AP		 690 int ret;
691
11a332ad
AP		 692 mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
693 "mx31_3ds");
153fa1d8 694
16cf5c41 695 imx31_add_imx_uart0(&uart_pdata);
a2ceeef5 696 imx31_add_mxc_nand(&mx31_3ds_nand_board_info);
ae7a3f13 697
4a74bddc 698 imx31_add_spi_imx1(&spi1_pdata);
ae7a3f13
AP		 699 spi_register_board_info(mx31_3ds_spi_devs,
700 ARRAY_SIZE(mx31_3ds_spi_devs));
135cad36 701
164f7b52
AP		 702 platform_add_devices(devices, ARRAY_SIZE(devices));
703
d690b4c4 704 imx31_add_imx_keypad(&mx31_3ds_keymap_data);
54c1f636 705
a2ef4562 706 mx31_3ds_usbotg_init();
1c50e672 707 if (otg_mode_host) {
48f6b099
SH		 708 otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
709 ULPI_OTG_DRVVBUS_EXT);
710 if (otg_pdata.otg)
711 imx31_add_mxc_ehci_otg(&otg_pdata);
1c50e672 712 }
48f6b099
SH		 713 usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
714 ULPI_OTG_DRVVBUS_EXT);
715 if (usbh2_pdata.otg)
716 imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
717
1c50e672
FE		 718 if (!otg_mode_host)
719 imx31_add_fsl_usb2_udc(&usbotg_pdata);
a2ef4562 720
b8be7b9a
RP		 721 if (mxc_expio_init(MX31_CS5_BASE_ADDR, EXPIO_PARENT_INT))
722 printk(KERN_WARNING "Init of the debug board failed, all "
723 "devices on the debug board are unusable.\n");
bfdde3a9 724 imx31_add_imx2_wdt(NULL);
3d943024 725 imx31_add_imx_i2c0(&mx31_3ds_i2c0_data);
0ce88b34 726 imx31_add_mxc_mmc(0, &sdhc1_pdata);
e42010e0
AP		 727
728 imx31_add_spi_imx0(&spi0_pdata);
afa77ef3
UKK		 729 imx31_add_ipu_core(&mx3_ipu_data);
730 imx31_add_mx3_sdc_fb(&mx3fb_pdata);
164f7b52
AP		 731
732 /* CSI */
733 /* Camera power: default - off */
734 ret = gpio_request_array(mx31_3ds_camera_gpios,
735 ARRAY_SIZE(mx31_3ds_camera_gpios));
736 if (ret) {
737 pr_err("Failed to request camera gpios");
738 iclink_ov2640.power = NULL;
739 }
740
afa77ef3 741 mx31_3ds_init_camera();
1553a1ec
FE		 742}
743
11a332ad 744static void __init mx31_3ds_timer_init(void)
1553a1ec 745{
30c730f8 746 mx31_clocks_init(26000000);
1553a1ec
FE		 747}
748
11a332ad
AP		 749static struct sys_timer mx31_3ds_timer = {
750 .init = mx31_3ds_timer_init,
1553a1ec
FE		 751};
752
164f7b52
AP		 753static void __init mx31_3ds_reserve(void)
754{
755 /* reserve MX31_3DS_CAMERA_BUF_SIZE bytes for mx3-camera */
756 mx3_camera_base = memblock_alloc(MX31_3DS_CAMERA_BUF_SIZE,
757 MX31_3DS_CAMERA_BUF_SIZE);
758 memblock_free(mx3_camera_base, MX31_3DS_CAMERA_BUF_SIZE);
759 memblock_remove(mx3_camera_base, MX31_3DS_CAMERA_BUF_SIZE);
760}
761
1553a1ec
FE		 762MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
763 /* Maintainer: Freescale Semiconductor, Inc. */
97976e22
UKK		 764 .boot_params = MX3x_PHYS_OFFSET + 0x100,
765 .map_io = mx31_map_io,
766 .init_early = imx31_init_early,
767 .init_irq = mx31_init_irq,
768 .timer = &mx31_3ds_timer,
e134fb2b 769 .init_machine = mx31_3ds_init,
164f7b52 770 .reserve = mx31_3ds_reserve,
1553a1ec 771MACHINE_END
Linux kernel - Deliverables
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