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ARM: imx: Fix typo 'MACH_MX31_3DS_MXC_NAND_USE_BBT'
[deliverable/linux.git] / arch / arm / mach-imx / mach-mx31_3ds.c
CommitLineData
1553a1ec
FE		 1/*
2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
1553a1ec
FE		 13 */
14
a2ef4562 15#include <linux/delay.h>
b7f080cf 16#include <linux/dma-mapping.h>
1553a1ec
FE		 17#include <linux/types.h>
18#include <linux/init.h>
19#include <linux/clk.h>
20#include <linux/irq.h>
135cad36 21#include <linux/gpio.h>
2b0c3677 22#include <linux/platform_device.h>
ae7a3f13
AP		 23#include <linux/mfd/mc13783.h>
24#include <linux/spi/spi.h>
e42010e0 25#include <linux/spi/l4f00242t03.h>
ae7a3f13 26#include <linux/regulator/machine.h>
1c50e672
FE		 27#include <linux/usb/otg.h>
28#include <linux/usb/ulpi.h>
164f7b52
AP		 29#include <linux/memblock.h>
30
31#include <media/soc_camera.h>
1553a1ec
FE		 32
33#include <mach/hardware.h>
34#include <asm/mach-types.h>
35#include <asm/mach/arch.h>
36#include <asm/mach/time.h>
37#include <asm/memory.h>
38#include <asm/mach/map.h>
39#include <mach/common.h>
1553a1ec 40#include <mach/iomux-mx3.h>
c5d38f08 41#include <mach/3ds_debugboard.h>
1c50e672 42#include <mach/ulpi.h>
a2ceeef5
UKK		 43
44#include "devices-imx31.h"
1553a1ec 45
b396dc45
UKK		 46/* CPLD IRQ line for external uart, external ethernet etc */
47#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
48
11a332ad 49static int mx31_3ds_pins[] = {
153fa1d8 50 /* UART1 */
63d97667
VL		 51 MX31_PIN_CTS1__CTS1,
52 MX31_PIN_RTS1__RTS1,
53 MX31_PIN_TXD1__TXD1,
135cad36
ML		 54 MX31_PIN_RXD1__RXD1,
55 IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO),
e42010e0 56 /*SPI0*/
b2a08e3e
FE		 57 IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_ALT1),
58 IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_ALT1),
a1ac4424
AP		 59 /* SPI 1 */
60 MX31_PIN_CSPI2_SCLK__SCLK,
61 MX31_PIN_CSPI2_MOSI__MOSI,
62 MX31_PIN_CSPI2_MISO__MISO,
63 MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
64 MX31_PIN_CSPI2_SS0__SS0,
65 MX31_PIN_CSPI2_SS2__SS2, /*CS for MC13783 */
ae7a3f13
AP		 66 /* MC13783 IRQ */
67 IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO),
a2ef4562
ML		 68 /* USB OTG reset */
69 IOMUX_MODE(MX31_PIN_USB_PWR, IOMUX_CONFIG_GPIO),
70 /* USB OTG */
71 MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
72 MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
73 MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
74 MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
75 MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
76 MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
77 MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
78 MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
79 MX31_PIN_USBOTG_CLK__USBOTG_CLK,
80 MX31_PIN_USBOTG_DIR__USBOTG_DIR,
81 MX31_PIN_USBOTG_NXT__USBOTG_NXT,
82 MX31_PIN_USBOTG_STP__USBOTG_STP,
54c1f636
AP		 83 /*Keyboard*/
84 MX31_PIN_KEY_ROW0_KEY_ROW0,
85 MX31_PIN_KEY_ROW1_KEY_ROW1,
86 MX31_PIN_KEY_ROW2_KEY_ROW2,
87 MX31_PIN_KEY_COL0_KEY_COL0,
88 MX31_PIN_KEY_COL1_KEY_COL1,
89 MX31_PIN_KEY_COL2_KEY_COL2,
90 MX31_PIN_KEY_COL3_KEY_COL3,
0d95b75e
FE		 91 /* USB Host 2 */
92 IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
93 IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
94 IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
95 IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
96 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
97 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
98 IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT1),
99 IOMUX_MODE(MX31_PIN_PC_BVD1, IOMUX_CONFIG_ALT1),
100 IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT1),
101 IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT1),
102 IOMUX_MODE(MX31_PIN_IOIS16, IOMUX_CONFIG_ALT1),
103 IOMUX_MODE(MX31_PIN_PC_RW_B, IOMUX_CONFIG_ALT1),
104 /* USB Host2 reset */
105 IOMUX_MODE(MX31_PIN_USB_BYP, IOMUX_CONFIG_GPIO),
3d943024
FE		 106 /* I2C1 */
107 MX31_PIN_I2C_CLK__I2C1_SCL,
108 MX31_PIN_I2C_DAT__I2C1_SDA,
0ce88b34
AP		 109 /* SDHC1 */
110 MX31_PIN_SD1_DATA3__SD1_DATA3,
111 MX31_PIN_SD1_DATA2__SD1_DATA2,
112 MX31_PIN_SD1_DATA1__SD1_DATA1,
113 MX31_PIN_SD1_DATA0__SD1_DATA0,
114 MX31_PIN_SD1_CLK__SD1_CLK,
115 MX31_PIN_SD1_CMD__SD1_CMD,
116 MX31_PIN_GPIO3_1__GPIO3_1, /* Card detect */
117 MX31_PIN_GPIO3_0__GPIO3_0, /* OE */
e42010e0
AP		 118 /* Framebuffer */
119 MX31_PIN_LD0__LD0,
120 MX31_PIN_LD1__LD1,
121 MX31_PIN_LD2__LD2,
122 MX31_PIN_LD3__LD3,
123 MX31_PIN_LD4__LD4,
124 MX31_PIN_LD5__LD5,
125 MX31_PIN_LD6__LD6,
126 MX31_PIN_LD7__LD7,
127 MX31_PIN_LD8__LD8,
128 MX31_PIN_LD9__LD9,
129 MX31_PIN_LD10__LD10,
130 MX31_PIN_LD11__LD11,
131 MX31_PIN_LD12__LD12,
132 MX31_PIN_LD13__LD13,
133 MX31_PIN_LD14__LD14,
134 MX31_PIN_LD15__LD15,
135 MX31_PIN_LD16__LD16,
136 MX31_PIN_LD17__LD17,
137 MX31_PIN_VSYNC3__VSYNC3,
138 MX31_PIN_HSYNC__HSYNC,
139 MX31_PIN_FPSHIFT__FPSHIFT,
140 MX31_PIN_CONTRAST__CONTRAST,
164f7b52
AP		 141 /* CSI */
142 MX31_PIN_CSI_D6__CSI_D6,
143 MX31_PIN_CSI_D7__CSI_D7,
144 MX31_PIN_CSI_D8__CSI_D8,
145 MX31_PIN_CSI_D9__CSI_D9,
146 MX31_PIN_CSI_D10__CSI_D10,
147 MX31_PIN_CSI_D11__CSI_D11,
148 MX31_PIN_CSI_D12__CSI_D12,
149 MX31_PIN_CSI_D13__CSI_D13,
150 MX31_PIN_CSI_D14__CSI_D14,
151 MX31_PIN_CSI_D15__CSI_D15,
152 MX31_PIN_CSI_HSYNC__CSI_HSYNC,
153 MX31_PIN_CSI_MCLK__CSI_MCLK,
154 MX31_PIN_CSI_PIXCLK__CSI_PIXCLK,
155 MX31_PIN_CSI_VSYNC__CSI_VSYNC,
156 MX31_PIN_CSI_D5__GPIO3_5, /* CMOS PWDN */
157 IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_GPIO), /* CMOS reset */
158};
159
160/*
161 * Camera support
162 */
163static phys_addr_t mx3_camera_base __initdata;
164#define MX31_3DS_CAMERA_BUF_SIZE SZ_8M
165
166#define MX31_3DS_GPIO_CAMERA_PW IOMUX_TO_GPIO(MX31_PIN_CSI_D5)
167#define MX31_3DS_GPIO_CAMERA_RST IOMUX_TO_GPIO(MX31_PIN_RI_DTE1)
168
169static struct gpio mx31_3ds_camera_gpios[] = {
170 { MX31_3DS_GPIO_CAMERA_PW, GPIOF_OUT_INIT_HIGH, "camera-power" },
171 { MX31_3DS_GPIO_CAMERA_RST, GPIOF_OUT_INIT_HIGH, "camera-reset" },
172};
173
afa77ef3
UKK		 174static const struct mx3_camera_pdata mx31_3ds_camera_pdata __initconst = {
175 .flags = MX3_CAMERA_DATAWIDTH_10,
176 .mclk_10khz = 2600,
177};
178
179static int __init mx31_3ds_init_camera(void)
164f7b52 180{
afa77ef3
UKK		 181 int dma, ret = -ENOMEM;
182 struct platform_device *pdev =
183 imx31_alloc_mx3_camera(&mx31_3ds_camera_pdata);
184
185 if (IS_ERR(pdev))
186 return PTR_ERR(pdev);
164f7b52
AP		 187
188 if (!mx3_camera_base)
afa77ef3 189 goto err;
164f7b52 190
afa77ef3 191 dma = dma_declare_coherent_memory(&pdev->dev,
164f7b52
AP		 192 mx3_camera_base, mx3_camera_base,
193 MX31_3DS_CAMERA_BUF_SIZE,
194 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
195
196 if (!(dma & DMA_MEMORY_MAP))
afa77ef3 197 goto err;
164f7b52 198
afa77ef3
UKK		 199 ret = platform_device_add(pdev);
200 if (ret)
201err:
202 platform_device_put(pdev);
203
204 return ret;
164f7b52
AP		 205}
206
207static int mx31_3ds_camera_power(struct device *dev, int on)
208{
209 /* enable or disable the camera */
210 pr_debug("%s: %s the camera\n", __func__, on ? "ENABLE" : "DISABLE");
211 gpio_set_value(MX31_3DS_GPIO_CAMERA_PW, on ? 0 : 1);
212
213 if (!on)
214 goto out;
215
216 /* If enabled, give a reset impulse */
217 gpio_set_value(MX31_3DS_GPIO_CAMERA_RST, 0);
218 msleep(20);
219 gpio_set_value(MX31_3DS_GPIO_CAMERA_RST, 1);
220 msleep(100);
221
222out:
223 return 0;
224}
225
226static struct i2c_board_info mx31_3ds_i2c_camera = {
227 I2C_BOARD_INFO("ov2640", 0x30),
228};
229
230static struct regulator_bulk_data mx31_3ds_camera_regs[] = {
231 { .supply = "cmos_vcore" },
232 { .supply = "cmos_2v8" },
233};
234
235static struct soc_camera_link iclink_ov2640 = {
236 .bus_id = 0,
237 .board_info = &mx31_3ds_i2c_camera,
238 .i2c_adapter_id = 0,
239 .power = mx31_3ds_camera_power,
240 .regulators = mx31_3ds_camera_regs,
241 .num_regulators = ARRAY_SIZE(mx31_3ds_camera_regs),
242};
243
244static struct platform_device mx31_3ds_ov2640 = {
245 .name = "soc-camera-pdrv",
246 .id = 0,
247 .dev = {
248 .platform_data = &iclink_ov2640,
249 },
250};
251
e42010e0
AP		 252/*
253 * FB support
254 */
255static const struct fb_videomode fb_modedb[] = {
256 { /* 480x640 @ 60 Hz */
257 .name = "Epson-VGA",
258 .refresh = 60,
259 .xres = 480,
260 .yres = 640,
261 .pixclock = 41701,
262 .left_margin = 20,
263 .right_margin = 41,
264 .upper_margin = 10,
265 .lower_margin = 5,
266 .hsync_len = 20,
267 .vsync_len = 10,
268 .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
269 .vmode = FB_VMODE_NONINTERLACED,
270 .flag = 0,
271 },
272};
273
274static struct ipu_platform_data mx3_ipu_data = {
275 .irq_base = MXC_IPU_IRQ_START,
276};
277
afa77ef3 278static struct mx3fb_platform_data mx3fb_pdata __initdata = {
e42010e0
AP		 279 .name = "Epson-VGA",
280 .mode = fb_modedb,
281 .num_modes = ARRAY_SIZE(fb_modedb),
282};
283
284/* LCD */
285static struct l4f00242t03_pdata mx31_3ds_l4f00242t03_pdata = {
286 .reset_gpio = IOMUX_TO_GPIO(MX31_PIN_LCS1),
287 .data_enable_gpio = IOMUX_TO_GPIO(MX31_PIN_SER_RS),
288 .core_supply = "lcd_2v8",
289 .io_supply = "vdd_lcdio",
0ce88b34
AP		 290};
291
292/*
293 * Support for SD card slot in personality board
294 */
295#define MX31_3DS_GPIO_SDHC1_CD IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)
296#define MX31_3DS_GPIO_SDHC1_BE IOMUX_TO_GPIO(MX31_PIN_GPIO3_0)
297
298static struct gpio mx31_3ds_sdhc1_gpios[] = {
299 { MX31_3DS_GPIO_SDHC1_CD, GPIOF_IN, "sdhc1-card-detect" },
300 { MX31_3DS_GPIO_SDHC1_BE, GPIOF_OUT_INIT_LOW, "sdhc1-bus-en" },
301};
302
303static int mx31_3ds_sdhc1_init(struct device *dev,
304 irq_handler_t detect_irq,
305 void *data)
306{
307 int ret;
308
309 ret = gpio_request_array(mx31_3ds_sdhc1_gpios,
310 ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
311 if (ret) {
312 pr_warning("Unable to request the SD/MMC GPIOs.\n");
313 return ret;
314 }
315
316 ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
317 detect_irq, IRQF_DISABLED |
318 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
319 "sdhc1-detect", data);
320 if (ret) {
321 pr_warning("Unable to request the SD/MMC card-detect IRQ.\n");
322 goto gpio_free;
323 }
324
325 return 0;
326
327gpio_free:
328 gpio_free_array(mx31_3ds_sdhc1_gpios,
329 ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
330 return ret;
331}
332
333static void mx31_3ds_sdhc1_exit(struct device *dev, void *data)
334{
335 free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO3_1), data);
336 gpio_free_array(mx31_3ds_sdhc1_gpios,
337 ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
338}
339
340static void mx31_3ds_sdhc1_setpower(struct device *dev, unsigned int vdd)
341{
342 /*
343 * While the voltage stuff is done by the driver, activate the
344 * Buffer Enable Pin only if there is a card in slot to fix the card
345 * voltage issue caused by bi-directional chip TXB0108 on 3Stack.
346 * Done here because at this stage we have for sure a debounced value
347 * of the presence of the card, showed by the value of vdd.
348 * 7 == ilog2(MMC_VDD_165_195)
349 */
350 if (vdd > 7)
351 gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 1);
352 else
353 gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 0);
354}
355
356static struct imxmmc_platform_data sdhc1_pdata = {
357 .init = mx31_3ds_sdhc1_init,
358 .exit = mx31_3ds_sdhc1_exit,
359 .setpower = mx31_3ds_sdhc1_setpower,
54c1f636
AP		 360};
361
362/*
363 * Matrix keyboard
364 */
365
366static const uint32_t mx31_3ds_keymap[] = {
367 KEY(0, 0, KEY_UP),
368 KEY(0, 1, KEY_DOWN),
369 KEY(1, 0, KEY_RIGHT),
370 KEY(1, 1, KEY_LEFT),
371 KEY(1, 2, KEY_ENTER),
372 KEY(2, 0, KEY_F6),
373 KEY(2, 1, KEY_F8),
374 KEY(2, 2, KEY_F9),
375 KEY(2, 3, KEY_F10),
376};
377
d690b4c4 378static const struct matrix_keymap_data mx31_3ds_keymap_data __initconst = {
54c1f636
AP		 379 .keymap = mx31_3ds_keymap,
380 .keymap_size = ARRAY_SIZE(mx31_3ds_keymap),
ae7a3f13
AP		 381};
382
383/* Regulators */
384static struct regulator_init_data pwgtx_init = {
385 .constraints = {
386 .boot_on = 1,
387 .always_on = 1,
388 },
389};
390
0d95b75e
FE		 391static struct regulator_init_data gpo_init = {
392 .constraints = {
393 .boot_on = 1,
394 .always_on = 1,
395 }
396};
397
0ce88b34
AP		 398static struct regulator_consumer_supply vmmc2_consumers[] = {
399 REGULATOR_SUPPLY("vmmc", "mxc-mmc.0"),
400};
401
402static struct regulator_init_data vmmc2_init = {
403 .constraints = {
404 .min_uV = 3000000,
405 .max_uV = 3000000,
406 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
407 REGULATOR_CHANGE_STATUS,
408 },
409 .num_consumer_supplies = ARRAY_SIZE(vmmc2_consumers),
410 .consumer_supplies = vmmc2_consumers,
411};
412
e42010e0
AP		 413static struct regulator_consumer_supply vmmc1_consumers[] = {
414 REGULATOR_SUPPLY("lcd_2v8", NULL),
164f7b52 415 REGULATOR_SUPPLY("cmos_2v8", "soc-camera-pdrv.0"),
e42010e0
AP		 416};
417
418static struct regulator_init_data vmmc1_init = {
419 .constraints = {
420 .min_uV = 2800000,
421 .max_uV = 2800000,
422 .apply_uV = 1,
423 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
424 REGULATOR_CHANGE_STATUS,
425 },
426 .num_consumer_supplies = ARRAY_SIZE(vmmc1_consumers),
427 .consumer_supplies = vmmc1_consumers,
428};
429
430static struct regulator_consumer_supply vgen_consumers[] = {
431 REGULATOR_SUPPLY("vdd_lcdio", NULL),
432};
433
434static struct regulator_init_data vgen_init = {
435 .constraints = {
436 .min_uV = 1800000,
437 .max_uV = 1800000,
438 .apply_uV = 1,
439 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
440 REGULATOR_CHANGE_STATUS,
441 },
442 .num_consumer_supplies = ARRAY_SIZE(vgen_consumers),
443 .consumer_supplies = vgen_consumers,
444};
445
164f7b52
AP		 446static struct regulator_consumer_supply vvib_consumers[] = {
447 REGULATOR_SUPPLY("cmos_vcore", "soc-camera-pdrv.0"),
448};
449
450static struct regulator_init_data vvib_init = {
451 .constraints = {
452 .min_uV = 1300000,
453 .max_uV = 1300000,
454 .apply_uV = 1,
455 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
456 REGULATOR_CHANGE_STATUS,
457 },
458 .num_consumer_supplies = ARRAY_SIZE(vvib_consumers),
459 .consumer_supplies = vvib_consumers,
460};
461
5836372e 462static struct mc13xxx_regulator_init_data mx31_3ds_regulators[] = {
ae7a3f13 463 {
57c78e35 464 .id = MC13783_REG_PWGT1SPI, /* Power Gate for ARM core. */
ae7a3f13
AP		 465 .init_data = &pwgtx_init,
466 }, {
57c78e35 467 .id = MC13783_REG_PWGT2SPI, /* Power Gate for L2 Cache. */
ae7a3f13 468 .init_data = &pwgtx_init,
0d95b75e
FE		 469 }, {
470
c97b7393 471 .id = MC13783_REG_GPO1, /* Turn on 1.8V */
0d95b75e
FE		 472 .init_data = &gpo_init,
473 }, {
c97b7393 474 .id = MC13783_REG_GPO3, /* Turn on 3.3V */
0d95b75e 475 .init_data = &gpo_init,
0ce88b34
AP		 476 }, {
477 .id = MC13783_REG_VMMC2, /* Power MMC/SD, WiFi/Bluetooth. */
478 .init_data = &vmmc2_init,
e42010e0
AP		 479 }, {
480 .id = MC13783_REG_VMMC1, /* Power LCD, CMOS, FM, GPS, Accel. */
481 .init_data = &vmmc1_init,
482 }, {
483 .id = MC13783_REG_VGEN, /* Power LCD */
484 .init_data = &vgen_init,
164f7b52
AP		 485 }, {
486 .id = MC13783_REG_VVIB, /* Power CMOS */
487 .init_data = &vvib_init,
ae7a3f13
AP		 488 },
489};
490
491/* MC13783 */
4ec1b54c
AS		 492static struct mc13xxx_platform_data mc13783_pdata = {
493 .regulators = {
494 .regulators = mx31_3ds_regulators,
495 .num_regulators = ARRAY_SIZE(mx31_3ds_regulators),
496 },
497 .flags = MC13783_USE_REGULATOR | MC13783_USE_TOUCHSCREEN,
a1ac4424
AP		 498};
499
500/* SPI */
e42010e0
AP		 501static int spi0_internal_chipselect[] = {
502 MXC_SPI_CS(2),
503};
504
505static const struct spi_imx_master spi0_pdata __initconst = {
506 .chipselect = spi0_internal_chipselect,
507 .num_chipselect = ARRAY_SIZE(spi0_internal_chipselect),
508};
509
a1ac4424
AP		 510static int spi1_internal_chipselect[] = {
511 MXC_SPI_CS(0),
512 MXC_SPI_CS(2),
513};
514
06606ff1 515static const struct spi_imx_master spi1_pdata __initconst = {
a1ac4424
AP		 516 .chipselect = spi1_internal_chipselect,
517 .num_chipselect = ARRAY_SIZE(spi1_internal_chipselect),
63d97667
VL		 518};
519
ae7a3f13
AP		 520static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
521 {
522 .modalias = "mc13783",
523 .max_speed_hz = 1000000,
524 .bus_num = 1,
525 .chip_select = 1, /* SS2 */
526 .platform_data = &mc13783_pdata,
527 .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
528 .mode = SPI_CS_HIGH,
e42010e0
AP		 529 }, {
530 .modalias = "l4f00242t03",
531 .max_speed_hz = 5000000,
532 .bus_num = 0,
533 .chip_select = 0, /* SS2 */
534 .platform_data = &mx31_3ds_l4f00242t03_pdata,
ae7a3f13
AP		 535 },
536};
537
a1b67b95
AP		 538/*
539 * NAND Flash
540 */
a2ceeef5
UKK		 541static const struct mxc_nand_platform_data
542mx31_3ds_nand_board_info __initconst = {
a1b67b95
AP		 543 .width = 1,
544 .hw_ecc = 1,
5328ecbb 545#ifdef CONFIG_MACH_MX31_3DS_MXC_NAND_USE_BBT
a1b67b95
AP		 546 .flash_bbt = 1,
547#endif
548};
549
a2ef4562
ML		 550/*
551 * USB OTG
552 */
553
554#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
555 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
556
557#define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR)
0d95b75e 558#define USBH2_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_BYP)
a2ef4562 559
41f63475 560static int mx31_3ds_usbotg_init(void)
a2ef4562 561{
41f63475
FE		 562 int err;
563
a2ef4562
ML		 564 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
565 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
566 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
567 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG);
568 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG);
569 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG);
570 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG);
571 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG);
572 mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG);
573 mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG);
574 mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
575 mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
576
41f63475
FE		 577 err = gpio_request(USBOTG_RST_B, "otgusb-reset");
578 if (err) {
579 pr_err("Failed to request the USB OTG reset gpio\n");
580 return err;
581 }
582
583 err = gpio_direction_output(USBOTG_RST_B, 0);
584 if (err) {
585 pr_err("Failed to drive the USB OTG reset gpio\n");
586 goto usbotg_free_reset;
587 }
588
a2ef4562
ML		 589 mdelay(1);
590 gpio_set_value(USBOTG_RST_B, 1);
41f63475
FE		 591 return 0;
592
593usbotg_free_reset:
594 gpio_free(USBOTG_RST_B);
595 return err;
a2ef4562
ML		 596}
597
4bd597b6
SH		 598static int mx31_3ds_otg_init(struct platform_device *pdev)
599{
600 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
601}
602
603static int mx31_3ds_host2_init(struct platform_device *pdev)
0d95b75e
FE		 604{
605 int err;
606
607 mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
608 mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
609 mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
610 mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
611 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
612 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
613 mxc_iomux_set_pad(MX31_PIN_PC_VS2, USB_PAD_CFG);
614 mxc_iomux_set_pad(MX31_PIN_PC_BVD1, USB_PAD_CFG);
615 mxc_iomux_set_pad(MX31_PIN_PC_BVD2, USB_PAD_CFG);
616 mxc_iomux_set_pad(MX31_PIN_PC_RST, USB_PAD_CFG);
617 mxc_iomux_set_pad(MX31_PIN_IOIS16, USB_PAD_CFG);
618 mxc_iomux_set_pad(MX31_PIN_PC_RW_B, USB_PAD_CFG);
619
620 err = gpio_request(USBH2_RST_B, "usbh2-reset");
621 if (err) {
622 pr_err("Failed to request the USB Host 2 reset gpio\n");
623 return err;
624 }
625
626 err = gpio_direction_output(USBH2_RST_B, 0);
627 if (err) {
628 pr_err("Failed to drive the USB Host 2 reset gpio\n");
629 goto usbotg_free_reset;
630 }
631
632 mdelay(1);
633 gpio_set_value(USBH2_RST_B, 1);
4bd597b6
SH		 634
635 mdelay(10);
636
637 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
0d95b75e
FE		 638
639usbotg_free_reset:
640 gpio_free(USBH2_RST_B);
641 return err;
642}
643
1c50e672 644static struct mxc_usbh_platform_data otg_pdata __initdata = {
4bd597b6 645 .init = mx31_3ds_otg_init,
1c50e672 646 .portsc = MXC_EHCI_MODE_ULPI,
1c50e672 647};
0d95b75e
FE		 648
649static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
650 .init = mx31_3ds_host2_init,
651 .portsc = MXC_EHCI_MODE_ULPI,
0d95b75e 652};
1c50e672 653
9e1dde33 654static const struct fsl_usb2_platform_data usbotg_pdata __initconst = {
a2ef4562
ML		 655 .operating_mode = FSL_USB2_DR_DEVICE,
656 .phy_mode = FSL_USB2_PHY_ULPI,
657};
658
1c50e672
FE		 659static int otg_mode_host;
660
661static int __init mx31_3ds_otg_mode(char *options)
662{
663 if (!strcmp(options, "host"))
664 otg_mode_host = 1;
665 else if (!strcmp(options, "device"))
666 otg_mode_host = 0;
667 else
668 pr_info("otg_mode neither \"host\" nor \"device\". "
669 "Defaulting to device\n");
670 return 0;
671}
672__setup("otg_mode=", mx31_3ds_otg_mode);
673
16cf5c41 674static const struct imxuart_platform_data uart_pdata __initconst = {
153fa1d8
ML		 675 .flags = IMXUART_HAVE_RTSCTS,
676};
1553a1ec 677
3d943024
FE		 678static const struct imxi2c_platform_data mx31_3ds_i2c0_data __initconst = {
679 .bitrate = 100000,
680};
681
164f7b52
AP		 682static struct platform_device *devices[] __initdata = {
683 &mx31_3ds_ov2640,
684};
685
e134fb2b 686static void __init mx31_3ds_init(void)
1553a1ec 687{
164f7b52
AP		 688 int ret;
689
b78d8e59
SG		 690 imx31_soc_init();
691
b2a08e3e
FE		 692 /* Configure SPI1 IOMUX */
693 mxc_iomux_set_gpr(MUX_PGP_CSPI_BB, true);
694
11a332ad
AP		 695 mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
696 "mx31_3ds");
153fa1d8 697
16cf5c41 698 imx31_add_imx_uart0(&uart_pdata);
a2ceeef5 699 imx31_add_mxc_nand(&mx31_3ds_nand_board_info);
ae7a3f13 700
4a74bddc 701 imx31_add_spi_imx1(&spi1_pdata);
ae7a3f13
AP		 702 spi_register_board_info(mx31_3ds_spi_devs,
703 ARRAY_SIZE(mx31_3ds_spi_devs));
135cad36 704
164f7b52
AP		 705 platform_add_devices(devices, ARRAY_SIZE(devices));
706
d690b4c4 707 imx31_add_imx_keypad(&mx31_3ds_keymap_data);
54c1f636 708
a2ef4562 709 mx31_3ds_usbotg_init();
1c50e672 710 if (otg_mode_host) {
48f6b099
SH		 711 otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
712 ULPI_OTG_DRVVBUS_EXT);
713 if (otg_pdata.otg)
714 imx31_add_mxc_ehci_otg(&otg_pdata);
1c50e672 715 }
48f6b099
SH		 716 usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
717 ULPI_OTG_DRVVBUS_EXT);
718 if (usbh2_pdata.otg)
719 imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
720
1c50e672
FE		 721 if (!otg_mode_host)
722 imx31_add_fsl_usb2_udc(&usbotg_pdata);
a2ef4562 723
b8be7b9a
RP		 724 if (mxc_expio_init(MX31_CS5_BASE_ADDR, EXPIO_PARENT_INT))
725 printk(KERN_WARNING "Init of the debug board failed, all "
726 "devices on the debug board are unusable.\n");
bfdde3a9 727 imx31_add_imx2_wdt(NULL);
3d943024 728 imx31_add_imx_i2c0(&mx31_3ds_i2c0_data);
0ce88b34 729 imx31_add_mxc_mmc(0, &sdhc1_pdata);
e42010e0
AP		 730
731 imx31_add_spi_imx0(&spi0_pdata);
afa77ef3
UKK		 732 imx31_add_ipu_core(&mx3_ipu_data);
733 imx31_add_mx3_sdc_fb(&mx3fb_pdata);
164f7b52
AP		 734
735 /* CSI */
736 /* Camera power: default - off */
737 ret = gpio_request_array(mx31_3ds_camera_gpios,
738 ARRAY_SIZE(mx31_3ds_camera_gpios));
739 if (ret) {
740 pr_err("Failed to request camera gpios");
741 iclink_ov2640.power = NULL;
742 }
743
afa77ef3 744 mx31_3ds_init_camera();
1553a1ec
FE		 745}
746
11a332ad 747static void __init mx31_3ds_timer_init(void)
1553a1ec 748{
30c730f8 749 mx31_clocks_init(26000000);
1553a1ec
FE		 750}
751
11a332ad
AP		 752static struct sys_timer mx31_3ds_timer = {
753 .init = mx31_3ds_timer_init,
1553a1ec
FE		 754};
755
164f7b52
AP		 756static void __init mx31_3ds_reserve(void)
757{
758 /* reserve MX31_3DS_CAMERA_BUF_SIZE bytes for mx3-camera */
759 mx3_camera_base = memblock_alloc(MX31_3DS_CAMERA_BUF_SIZE,
760 MX31_3DS_CAMERA_BUF_SIZE);
761 memblock_free(mx3_camera_base, MX31_3DS_CAMERA_BUF_SIZE);
762 memblock_remove(mx3_camera_base, MX31_3DS_CAMERA_BUF_SIZE);
763}
764
1553a1ec
FE		 765MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
766 /* Maintainer: Freescale Semiconductor, Inc. */
97976e22
UKK		 767 .boot_params = MX3x_PHYS_OFFSET + 0x100,
768 .map_io = mx31_map_io,
769 .init_early = imx31_init_early,
770 .init_irq = mx31_init_irq,
771 .timer = &mx31_3ds_timer,
e134fb2b 772 .init_machine = mx31_3ds_init,
164f7b52 773 .reserve = mx31_3ds_reserve,
1553a1ec 774MACHINE_END
Linux kernel - Deliverables
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