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ARM: imx: move irq_domain_add_legacy call into avic driver
[deliverable/linux.git] / arch / arm / mach-imx / mach-mx31_3ds.c
CommitLineData
1553a1ec
FE		 1/*
2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
1553a1ec
FE		 13 */
14
a2ef4562 15#include <linux/delay.h>
b7f080cf 16#include <linux/dma-mapping.h>
1553a1ec
FE		 17#include <linux/types.h>
18#include <linux/init.h>
19#include <linux/clk.h>
20#include <linux/irq.h>
135cad36 21#include <linux/gpio.h>
2b0c3677 22#include <linux/platform_device.h>
ae7a3f13
AP		 23#include <linux/mfd/mc13783.h>
24#include <linux/spi/spi.h>
e42010e0 25#include <linux/spi/l4f00242t03.h>
ae7a3f13 26#include <linux/regulator/machine.h>
1c50e672
FE		 27#include <linux/usb/otg.h>
28#include <linux/usb/ulpi.h>
164f7b52
AP		 29#include <linux/memblock.h>
30
31#include <media/soc_camera.h>
1553a1ec
FE		 32
33#include <mach/hardware.h>
34#include <asm/mach-types.h>
35#include <asm/mach/arch.h>
36#include <asm/mach/time.h>
37#include <asm/memory.h>
38#include <asm/mach/map.h>
716a3dc2 39#include <asm/memblock.h>
1553a1ec 40#include <mach/common.h>
1553a1ec 41#include <mach/iomux-mx3.h>
c5d38f08 42#include <mach/3ds_debugboard.h>
1c50e672 43#include <mach/ulpi.h>
a2ceeef5
UKK		 44
45#include "devices-imx31.h"
1553a1ec 46
11a332ad 47static int mx31_3ds_pins[] = {
153fa1d8 48 /* UART1 */
63d97667
VL		 49 MX31_PIN_CTS1__CTS1,
50 MX31_PIN_RTS1__RTS1,
51 MX31_PIN_TXD1__TXD1,
135cad36
ML		 52 MX31_PIN_RXD1__RXD1,
53 IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO),
e42010e0 54 /*SPI0*/
b2a08e3e
FE		 55 IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_ALT1),
56 IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_ALT1),
a1ac4424
AP		 57 /* SPI 1 */
58 MX31_PIN_CSPI2_SCLK__SCLK,
59 MX31_PIN_CSPI2_MOSI__MOSI,
60 MX31_PIN_CSPI2_MISO__MISO,
61 MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
62 MX31_PIN_CSPI2_SS0__SS0,
63 MX31_PIN_CSPI2_SS2__SS2, /*CS for MC13783 */
ae7a3f13
AP		 64 /* MC13783 IRQ */
65 IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO),
a2ef4562
ML		 66 /* USB OTG reset */
67 IOMUX_MODE(MX31_PIN_USB_PWR, IOMUX_CONFIG_GPIO),
68 /* USB OTG */
69 MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
70 MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
71 MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
72 MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
73 MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
74 MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
75 MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
76 MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
77 MX31_PIN_USBOTG_CLK__USBOTG_CLK,
78 MX31_PIN_USBOTG_DIR__USBOTG_DIR,
79 MX31_PIN_USBOTG_NXT__USBOTG_NXT,
80 MX31_PIN_USBOTG_STP__USBOTG_STP,
54c1f636
AP		 81 /*Keyboard*/
82 MX31_PIN_KEY_ROW0_KEY_ROW0,
83 MX31_PIN_KEY_ROW1_KEY_ROW1,
84 MX31_PIN_KEY_ROW2_KEY_ROW2,
85 MX31_PIN_KEY_COL0_KEY_COL0,
86 MX31_PIN_KEY_COL1_KEY_COL1,
87 MX31_PIN_KEY_COL2_KEY_COL2,
88 MX31_PIN_KEY_COL3_KEY_COL3,
0d95b75e
FE		 89 /* USB Host 2 */
90 IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
91 IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
92 IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
93 IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
94 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
95 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
96 IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT1),
97 IOMUX_MODE(MX31_PIN_PC_BVD1, IOMUX_CONFIG_ALT1),
98 IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT1),
99 IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT1),
100 IOMUX_MODE(MX31_PIN_IOIS16, IOMUX_CONFIG_ALT1),
101 IOMUX_MODE(MX31_PIN_PC_RW_B, IOMUX_CONFIG_ALT1),
102 /* USB Host2 reset */
103 IOMUX_MODE(MX31_PIN_USB_BYP, IOMUX_CONFIG_GPIO),
3d943024
FE		 104 /* I2C1 */
105 MX31_PIN_I2C_CLK__I2C1_SCL,
106 MX31_PIN_I2C_DAT__I2C1_SDA,
0ce88b34
AP		 107 /* SDHC1 */
108 MX31_PIN_SD1_DATA3__SD1_DATA3,
109 MX31_PIN_SD1_DATA2__SD1_DATA2,
110 MX31_PIN_SD1_DATA1__SD1_DATA1,
111 MX31_PIN_SD1_DATA0__SD1_DATA0,
112 MX31_PIN_SD1_CLK__SD1_CLK,
113 MX31_PIN_SD1_CMD__SD1_CMD,
114 MX31_PIN_GPIO3_1__GPIO3_1, /* Card detect */
115 MX31_PIN_GPIO3_0__GPIO3_0, /* OE */
e42010e0
AP		 116 /* Framebuffer */
117 MX31_PIN_LD0__LD0,
118 MX31_PIN_LD1__LD1,
119 MX31_PIN_LD2__LD2,
120 MX31_PIN_LD3__LD3,
121 MX31_PIN_LD4__LD4,
122 MX31_PIN_LD5__LD5,
123 MX31_PIN_LD6__LD6,
124 MX31_PIN_LD7__LD7,
125 MX31_PIN_LD8__LD8,
126 MX31_PIN_LD9__LD9,
127 MX31_PIN_LD10__LD10,
128 MX31_PIN_LD11__LD11,
129 MX31_PIN_LD12__LD12,
130 MX31_PIN_LD13__LD13,
131 MX31_PIN_LD14__LD14,
132 MX31_PIN_LD15__LD15,
133 MX31_PIN_LD16__LD16,
134 MX31_PIN_LD17__LD17,
135 MX31_PIN_VSYNC3__VSYNC3,
136 MX31_PIN_HSYNC__HSYNC,
137 MX31_PIN_FPSHIFT__FPSHIFT,
138 MX31_PIN_CONTRAST__CONTRAST,
164f7b52
AP		 139 /* CSI */
140 MX31_PIN_CSI_D6__CSI_D6,
141 MX31_PIN_CSI_D7__CSI_D7,
142 MX31_PIN_CSI_D8__CSI_D8,
143 MX31_PIN_CSI_D9__CSI_D9,
144 MX31_PIN_CSI_D10__CSI_D10,
145 MX31_PIN_CSI_D11__CSI_D11,
146 MX31_PIN_CSI_D12__CSI_D12,
147 MX31_PIN_CSI_D13__CSI_D13,
148 MX31_PIN_CSI_D14__CSI_D14,
149 MX31_PIN_CSI_D15__CSI_D15,
150 MX31_PIN_CSI_HSYNC__CSI_HSYNC,
151 MX31_PIN_CSI_MCLK__CSI_MCLK,
152 MX31_PIN_CSI_PIXCLK__CSI_PIXCLK,
153 MX31_PIN_CSI_VSYNC__CSI_VSYNC,
154 MX31_PIN_CSI_D5__GPIO3_5, /* CMOS PWDN */
155 IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_GPIO), /* CMOS reset */
5fb86e5d
PR		 156 /* SSI */
157 MX31_PIN_STXD4__STXD4,
158 MX31_PIN_SRXD4__SRXD4,
159 MX31_PIN_SCK4__SCK4,
160 MX31_PIN_SFS4__SFS4,
164f7b52
AP		 161};
162
163/*
164 * Camera support
165 */
166static phys_addr_t mx3_camera_base __initdata;
167#define MX31_3DS_CAMERA_BUF_SIZE SZ_8M
168
169#define MX31_3DS_GPIO_CAMERA_PW IOMUX_TO_GPIO(MX31_PIN_CSI_D5)
170#define MX31_3DS_GPIO_CAMERA_RST IOMUX_TO_GPIO(MX31_PIN_RI_DTE1)
171
172static struct gpio mx31_3ds_camera_gpios[] = {
173 { MX31_3DS_GPIO_CAMERA_PW, GPIOF_OUT_INIT_HIGH, "camera-power" },
174 { MX31_3DS_GPIO_CAMERA_RST, GPIOF_OUT_INIT_HIGH, "camera-reset" },
175};
176
afa77ef3
UKK		 177static const struct mx3_camera_pdata mx31_3ds_camera_pdata __initconst = {
178 .flags = MX3_CAMERA_DATAWIDTH_10,
179 .mclk_10khz = 2600,
180};
181
182static int __init mx31_3ds_init_camera(void)
164f7b52 183{
afa77ef3
UKK		 184 int dma, ret = -ENOMEM;
185 struct platform_device *pdev =
186 imx31_alloc_mx3_camera(&mx31_3ds_camera_pdata);
187
188 if (IS_ERR(pdev))
189 return PTR_ERR(pdev);
164f7b52
AP		 190
191 if (!mx3_camera_base)
afa77ef3 192 goto err;
164f7b52 193
afa77ef3 194 dma = dma_declare_coherent_memory(&pdev->dev,
164f7b52
AP		 195 mx3_camera_base, mx3_camera_base,
196 MX31_3DS_CAMERA_BUF_SIZE,
197 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
198
199 if (!(dma & DMA_MEMORY_MAP))
afa77ef3 200 goto err;
164f7b52 201
afa77ef3
UKK		 202 ret = platform_device_add(pdev);
203 if (ret)
204err:
205 platform_device_put(pdev);
206
207 return ret;
164f7b52
AP		 208}
209
210static int mx31_3ds_camera_power(struct device *dev, int on)
211{
212 /* enable or disable the camera */
213 pr_debug("%s: %s the camera\n", __func__, on ? "ENABLE" : "DISABLE");
214 gpio_set_value(MX31_3DS_GPIO_CAMERA_PW, on ? 0 : 1);
215
216 if (!on)
217 goto out;
218
219 /* If enabled, give a reset impulse */
220 gpio_set_value(MX31_3DS_GPIO_CAMERA_RST, 0);
221 msleep(20);
222 gpio_set_value(MX31_3DS_GPIO_CAMERA_RST, 1);
223 msleep(100);
224
225out:
226 return 0;
227}
228
229static struct i2c_board_info mx31_3ds_i2c_camera = {
230 I2C_BOARD_INFO("ov2640", 0x30),
231};
232
233static struct regulator_bulk_data mx31_3ds_camera_regs[] = {
234 { .supply = "cmos_vcore" },
235 { .supply = "cmos_2v8" },
236};
237
238static struct soc_camera_link iclink_ov2640 = {
239 .bus_id = 0,
240 .board_info = &mx31_3ds_i2c_camera,
241 .i2c_adapter_id = 0,
242 .power = mx31_3ds_camera_power,
243 .regulators = mx31_3ds_camera_regs,
244 .num_regulators = ARRAY_SIZE(mx31_3ds_camera_regs),
245};
246
247static struct platform_device mx31_3ds_ov2640 = {
248 .name = "soc-camera-pdrv",
249 .id = 0,
250 .dev = {
251 .platform_data = &iclink_ov2640,
252 },
253};
254
e42010e0
AP		 255/*
256 * FB support
257 */
258static const struct fb_videomode fb_modedb[] = {
259 { /* 480x640 @ 60 Hz */
260 .name = "Epson-VGA",
261 .refresh = 60,
262 .xres = 480,
263 .yres = 640,
264 .pixclock = 41701,
265 .left_margin = 20,
266 .right_margin = 41,
267 .upper_margin = 10,
268 .lower_margin = 5,
269 .hsync_len = 20,
270 .vsync_len = 10,
271 .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
272 .vmode = FB_VMODE_NONINTERLACED,
273 .flag = 0,
274 },
275};
276
277static struct ipu_platform_data mx3_ipu_data = {
278 .irq_base = MXC_IPU_IRQ_START,
279};
280
afa77ef3 281static struct mx3fb_platform_data mx3fb_pdata __initdata = {
e42010e0
AP		 282 .name = "Epson-VGA",
283 .mode = fb_modedb,
284 .num_modes = ARRAY_SIZE(fb_modedb),
285};
286
287/* LCD */
288static struct l4f00242t03_pdata mx31_3ds_l4f00242t03_pdata = {
289 .reset_gpio = IOMUX_TO_GPIO(MX31_PIN_LCS1),
290 .data_enable_gpio = IOMUX_TO_GPIO(MX31_PIN_SER_RS),
0ce88b34
AP		 291};
292
293/*
294 * Support for SD card slot in personality board
295 */
296#define MX31_3DS_GPIO_SDHC1_CD IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)
297#define MX31_3DS_GPIO_SDHC1_BE IOMUX_TO_GPIO(MX31_PIN_GPIO3_0)
298
299static struct gpio mx31_3ds_sdhc1_gpios[] = {
300 { MX31_3DS_GPIO_SDHC1_CD, GPIOF_IN, "sdhc1-card-detect" },
301 { MX31_3DS_GPIO_SDHC1_BE, GPIOF_OUT_INIT_LOW, "sdhc1-bus-en" },
302};
303
304static int mx31_3ds_sdhc1_init(struct device *dev,
305 irq_handler_t detect_irq,
306 void *data)
307{
308 int ret;
309
310 ret = gpio_request_array(mx31_3ds_sdhc1_gpios,
311 ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
312 if (ret) {
313 pr_warning("Unable to request the SD/MMC GPIOs.\n");
314 return ret;
315 }
316
ed175343 317 ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)),
0ce88b34
AP		 318 detect_irq, IRQF_DISABLED |
319 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
320 "sdhc1-detect", data);
321 if (ret) {
322 pr_warning("Unable to request the SD/MMC card-detect IRQ.\n");
323 goto gpio_free;
324 }
325
326 return 0;
327
328gpio_free:
329 gpio_free_array(mx31_3ds_sdhc1_gpios,
330 ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
331 return ret;
332}
333
334static void mx31_3ds_sdhc1_exit(struct device *dev, void *data)
335{
ed175343 336 free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)), data);
0ce88b34
AP		 337 gpio_free_array(mx31_3ds_sdhc1_gpios,
338 ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
339}
340
341static void mx31_3ds_sdhc1_setpower(struct device *dev, unsigned int vdd)
342{
343 /*
344 * While the voltage stuff is done by the driver, activate the
345 * Buffer Enable Pin only if there is a card in slot to fix the card
346 * voltage issue caused by bi-directional chip TXB0108 on 3Stack.
347 * Done here because at this stage we have for sure a debounced value
348 * of the presence of the card, showed by the value of vdd.
349 * 7 == ilog2(MMC_VDD_165_195)
350 */
351 if (vdd > 7)
352 gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 1);
353 else
354 gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 0);
355}
356
357static struct imxmmc_platform_data sdhc1_pdata = {
358 .init = mx31_3ds_sdhc1_init,
359 .exit = mx31_3ds_sdhc1_exit,
360 .setpower = mx31_3ds_sdhc1_setpower,
54c1f636
AP		 361};
362
363/*
364 * Matrix keyboard
365 */
366
367static const uint32_t mx31_3ds_keymap[] = {
368 KEY(0, 0, KEY_UP),
369 KEY(0, 1, KEY_DOWN),
370 KEY(1, 0, KEY_RIGHT),
371 KEY(1, 1, KEY_LEFT),
372 KEY(1, 2, KEY_ENTER),
373 KEY(2, 0, KEY_F6),
374 KEY(2, 1, KEY_F8),
375 KEY(2, 2, KEY_F9),
376 KEY(2, 3, KEY_F10),
377};
378
d690b4c4 379static const struct matrix_keymap_data mx31_3ds_keymap_data __initconst = {
54c1f636
AP		 380 .keymap = mx31_3ds_keymap,
381 .keymap_size = ARRAY_SIZE(mx31_3ds_keymap),
ae7a3f13
AP		 382};
383
384/* Regulators */
385static struct regulator_init_data pwgtx_init = {
386 .constraints = {
387 .boot_on = 1,
388 .always_on = 1,
389 },
390};
391
0d95b75e
FE		 392static struct regulator_init_data gpo_init = {
393 .constraints = {
394 .boot_on = 1,
395 .always_on = 1,
396 }
397};
398
0ce88b34
AP		 399static struct regulator_consumer_supply vmmc2_consumers[] = {
400 REGULATOR_SUPPLY("vmmc", "mxc-mmc.0"),
401};
402
403static struct regulator_init_data vmmc2_init = {
404 .constraints = {
405 .min_uV = 3000000,
406 .max_uV = 3000000,
407 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
408 REGULATOR_CHANGE_STATUS,
409 },
410 .num_consumer_supplies = ARRAY_SIZE(vmmc2_consumers),
411 .consumer_supplies = vmmc2_consumers,
412};
413
e42010e0 414static struct regulator_consumer_supply vmmc1_consumers[] = {
0556dc34 415 REGULATOR_SUPPLY("vcore", "spi0.0"),
164f7b52 416 REGULATOR_SUPPLY("cmos_2v8", "soc-camera-pdrv.0"),
e42010e0
AP		 417};
418
419static struct regulator_init_data vmmc1_init = {
420 .constraints = {
421 .min_uV = 2800000,
422 .max_uV = 2800000,
423 .apply_uV = 1,
424 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
425 REGULATOR_CHANGE_STATUS,
426 },
427 .num_consumer_supplies = ARRAY_SIZE(vmmc1_consumers),
428 .consumer_supplies = vmmc1_consumers,
429};
430
431static struct regulator_consumer_supply vgen_consumers[] = {
0556dc34 432 REGULATOR_SUPPLY("vdd", "spi0.0"),
e42010e0
AP		 433};
434
435static struct regulator_init_data vgen_init = {
436 .constraints = {
437 .min_uV = 1800000,
438 .max_uV = 1800000,
439 .apply_uV = 1,
440 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
441 REGULATOR_CHANGE_STATUS,
442 },
443 .num_consumer_supplies = ARRAY_SIZE(vgen_consumers),
444 .consumer_supplies = vgen_consumers,
445};
446
164f7b52
AP		 447static struct regulator_consumer_supply vvib_consumers[] = {
448 REGULATOR_SUPPLY("cmos_vcore", "soc-camera-pdrv.0"),
449};
450
451static struct regulator_init_data vvib_init = {
452 .constraints = {
453 .min_uV = 1300000,
454 .max_uV = 1300000,
455 .apply_uV = 1,
456 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
457 REGULATOR_CHANGE_STATUS,
458 },
459 .num_consumer_supplies = ARRAY_SIZE(vvib_consumers),
460 .consumer_supplies = vvib_consumers,
461};
462
5836372e 463static struct mc13xxx_regulator_init_data mx31_3ds_regulators[] = {
ae7a3f13 464 {
57c78e35 465 .id = MC13783_REG_PWGT1SPI, /* Power Gate for ARM core. */
ae7a3f13
AP		 466 .init_data = &pwgtx_init,
467 }, {
57c78e35 468 .id = MC13783_REG_PWGT2SPI, /* Power Gate for L2 Cache. */
ae7a3f13 469 .init_data = &pwgtx_init,
0d95b75e
FE		 470 }, {
471
c97b7393 472 .id = MC13783_REG_GPO1, /* Turn on 1.8V */
0d95b75e
FE		 473 .init_data = &gpo_init,
474 }, {
c97b7393 475 .id = MC13783_REG_GPO3, /* Turn on 3.3V */
0d95b75e 476 .init_data = &gpo_init,
0ce88b34
AP		 477 }, {
478 .id = MC13783_REG_VMMC2, /* Power MMC/SD, WiFi/Bluetooth. */
479 .init_data = &vmmc2_init,
e42010e0
AP		 480 }, {
481 .id = MC13783_REG_VMMC1, /* Power LCD, CMOS, FM, GPS, Accel. */
482 .init_data = &vmmc1_init,
483 }, {
484 .id = MC13783_REG_VGEN, /* Power LCD */
485 .init_data = &vgen_init,
164f7b52
AP		 486 }, {
487 .id = MC13783_REG_VVIB, /* Power CMOS */
488 .init_data = &vvib_init,
ae7a3f13
AP		 489 },
490};
491
492/* MC13783 */
5fb86e5d
PR		 493static struct mc13xxx_codec_platform_data mx31_3ds_codec = {
494 .dac_ssi_port = MC13783_SSI1_PORT,
495 .adc_ssi_port = MC13783_SSI1_PORT,
496};
497
4ec1b54c
AS		 498static struct mc13xxx_platform_data mc13783_pdata = {
499 .regulators = {
500 .regulators = mx31_3ds_regulators,
501 .num_regulators = ARRAY_SIZE(mx31_3ds_regulators),
502 },
5fb86e5d
PR		 503 .codec = &mx31_3ds_codec,
504 .flags = MC13XXX_USE_TOUCHSCREEN | MC13XXX_USE_RTC | MC13XXX_USE_CODEC,
505
506};
507
508static struct imx_ssi_platform_data mx31_3ds_ssi_pdata = {
509 .flags = IMX_SSI_DMA | IMX_SSI_NET,
a1ac4424
AP		 510};
511
512/* SPI */
e42010e0
AP		 513static int spi0_internal_chipselect[] = {
514 MXC_SPI_CS(2),
515};
516
517static const struct spi_imx_master spi0_pdata __initconst = {
518 .chipselect = spi0_internal_chipselect,
519 .num_chipselect = ARRAY_SIZE(spi0_internal_chipselect),
520};
521
a1ac4424
AP		 522static int spi1_internal_chipselect[] = {
523 MXC_SPI_CS(0),
524 MXC_SPI_CS(2),
525};
526
06606ff1 527static const struct spi_imx_master spi1_pdata __initconst = {
a1ac4424
AP		 528 .chipselect = spi1_internal_chipselect,
529 .num_chipselect = ARRAY_SIZE(spi1_internal_chipselect),
63d97667
VL		 530};
531
ae7a3f13
AP		 532static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
533 {
534 .modalias = "mc13783",
535 .max_speed_hz = 1000000,
536 .bus_num = 1,
537 .chip_select = 1, /* SS2 */
538 .platform_data = &mc13783_pdata,
ed175343 539 /* irq number is run-time assigned */
ae7a3f13 540 .mode = SPI_CS_HIGH,
e42010e0
AP		 541 }, {
542 .modalias = "l4f00242t03",
543 .max_speed_hz = 5000000,
544 .bus_num = 0,
545 .chip_select = 0, /* SS2 */
546 .platform_data = &mx31_3ds_l4f00242t03_pdata,
ae7a3f13
AP		 547 },
548};
549
a1b67b95
AP		 550/*
551 * NAND Flash
552 */
a2ceeef5
UKK		 553static const struct mxc_nand_platform_data
554mx31_3ds_nand_board_info __initconst = {
a1b67b95
AP		 555 .width = 1,
556 .hw_ecc = 1,
5328ecbb 557#ifdef CONFIG_MACH_MX31_3DS_MXC_NAND_USE_BBT
a1b67b95
AP		 558 .flash_bbt = 1,
559#endif
560};
561
a2ef4562
ML		 562/*
563 * USB OTG
564 */
565
566#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
567 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
568
569#define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR)
0d95b75e 570#define USBH2_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_BYP)
a2ef4562 571
41f63475 572static int mx31_3ds_usbotg_init(void)
a2ef4562 573{
41f63475
FE		 574 int err;
575
a2ef4562
ML		 576 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
577 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
578 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
579 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG);
580 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG);
581 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG);
582 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG);
583 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG);
584 mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG);
585 mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG);
586 mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
587 mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
588
41f63475
FE		 589 err = gpio_request(USBOTG_RST_B, "otgusb-reset");
590 if (err) {
591 pr_err("Failed to request the USB OTG reset gpio\n");
592 return err;
593 }
594
595 err = gpio_direction_output(USBOTG_RST_B, 0);
596 if (err) {
597 pr_err("Failed to drive the USB OTG reset gpio\n");
598 goto usbotg_free_reset;
599 }
600
a2ef4562
ML		 601 mdelay(1);
602 gpio_set_value(USBOTG_RST_B, 1);
41f63475
FE		 603 return 0;
604
605usbotg_free_reset:
606 gpio_free(USBOTG_RST_B);
607 return err;
a2ef4562
ML		 608}
609
4bd597b6
SH		 610static int mx31_3ds_otg_init(struct platform_device *pdev)
611{
612 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
613}
614
615static int mx31_3ds_host2_init(struct platform_device *pdev)
0d95b75e
FE		 616{
617 int err;
618
619 mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
620 mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
621 mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
622 mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
623 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
624 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
625 mxc_iomux_set_pad(MX31_PIN_PC_VS2, USB_PAD_CFG);
626 mxc_iomux_set_pad(MX31_PIN_PC_BVD1, USB_PAD_CFG);
627 mxc_iomux_set_pad(MX31_PIN_PC_BVD2, USB_PAD_CFG);
628 mxc_iomux_set_pad(MX31_PIN_PC_RST, USB_PAD_CFG);
629 mxc_iomux_set_pad(MX31_PIN_IOIS16, USB_PAD_CFG);
630 mxc_iomux_set_pad(MX31_PIN_PC_RW_B, USB_PAD_CFG);
631
632 err = gpio_request(USBH2_RST_B, "usbh2-reset");
633 if (err) {
634 pr_err("Failed to request the USB Host 2 reset gpio\n");
635 return err;
636 }
637
638 err = gpio_direction_output(USBH2_RST_B, 0);
639 if (err) {
640 pr_err("Failed to drive the USB Host 2 reset gpio\n");
641 goto usbotg_free_reset;
642 }
643
644 mdelay(1);
645 gpio_set_value(USBH2_RST_B, 1);
4bd597b6
SH		 646
647 mdelay(10);
648
649 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
0d95b75e
FE		 650
651usbotg_free_reset:
652 gpio_free(USBH2_RST_B);
653 return err;
654}
655
1c50e672 656static struct mxc_usbh_platform_data otg_pdata __initdata = {
4bd597b6 657 .init = mx31_3ds_otg_init,
1c50e672 658 .portsc = MXC_EHCI_MODE_ULPI,
1c50e672 659};
0d95b75e
FE		 660
661static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
662 .init = mx31_3ds_host2_init,
663 .portsc = MXC_EHCI_MODE_ULPI,
0d95b75e 664};
1c50e672 665
9e1dde33 666static const struct fsl_usb2_platform_data usbotg_pdata __initconst = {
a2ef4562
ML		 667 .operating_mode = FSL_USB2_DR_DEVICE,
668 .phy_mode = FSL_USB2_PHY_ULPI,
669};
670
1c50e672
FE		 671static int otg_mode_host;
672
673static int __init mx31_3ds_otg_mode(char *options)
674{
675 if (!strcmp(options, "host"))
676 otg_mode_host = 1;
677 else if (!strcmp(options, "device"))
678 otg_mode_host = 0;
679 else
680 pr_info("otg_mode neither \"host\" nor \"device\". "
681 "Defaulting to device\n");
682 return 0;
683}
684__setup("otg_mode=", mx31_3ds_otg_mode);
685
16cf5c41 686static const struct imxuart_platform_data uart_pdata __initconst = {
153fa1d8
ML		 687 .flags = IMXUART_HAVE_RTSCTS,
688};
1553a1ec 689
3d943024
FE		 690static const struct imxi2c_platform_data mx31_3ds_i2c0_data __initconst = {
691 .bitrate = 100000,
692};
693
164f7b52
AP		 694static struct platform_device *devices[] __initdata = {
695 &mx31_3ds_ov2640,
696};
697
e134fb2b 698static void __init mx31_3ds_init(void)
1553a1ec 699{
164f7b52
AP		 700 int ret;
701
b78d8e59
SG		 702 imx31_soc_init();
703
b2a08e3e
FE		 704 /* Configure SPI1 IOMUX */
705 mxc_iomux_set_gpr(MUX_PGP_CSPI_BB, true);
706
11a332ad
AP		 707 mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
708 "mx31_3ds");
153fa1d8 709
16cf5c41 710 imx31_add_imx_uart0(&uart_pdata);
a2ceeef5 711 imx31_add_mxc_nand(&mx31_3ds_nand_board_info);
ae7a3f13 712
4a74bddc 713 imx31_add_spi_imx1(&spi1_pdata);
ed175343 714 mx31_3ds_spi_devs[0].irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
ae7a3f13
AP		 715 spi_register_board_info(mx31_3ds_spi_devs,
716 ARRAY_SIZE(mx31_3ds_spi_devs));
135cad36 717
164f7b52
AP		 718 platform_add_devices(devices, ARRAY_SIZE(devices));
719
d690b4c4 720 imx31_add_imx_keypad(&mx31_3ds_keymap_data);
54c1f636 721
a2ef4562 722 mx31_3ds_usbotg_init();
1c50e672 723 if (otg_mode_host) {
48f6b099
SH		 724 otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
725 ULPI_OTG_DRVVBUS_EXT);
726 if (otg_pdata.otg)
727 imx31_add_mxc_ehci_otg(&otg_pdata);
1c50e672 728 }
48f6b099
SH		 729 usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
730 ULPI_OTG_DRVVBUS_EXT);
731 if (usbh2_pdata.otg)
732 imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
733
1c50e672
FE		 734 if (!otg_mode_host)
735 imx31_add_fsl_usb2_udc(&usbotg_pdata);
a2ef4562 736
ed175343
SG		 737 if (mxc_expio_init(MX31_CS5_BASE_ADDR,
738 gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1))))
b8be7b9a
RP		 739 printk(KERN_WARNING "Init of the debug board failed, all "
740 "devices on the debug board are unusable.\n");
bfdde3a9 741 imx31_add_imx2_wdt(NULL);
3d943024 742 imx31_add_imx_i2c0(&mx31_3ds_i2c0_data);
0ce88b34 743 imx31_add_mxc_mmc(0, &sdhc1_pdata);
e42010e0
AP		 744
745 imx31_add_spi_imx0(&spi0_pdata);
afa77ef3
UKK		 746 imx31_add_ipu_core(&mx3_ipu_data);
747 imx31_add_mx3_sdc_fb(&mx3fb_pdata);
164f7b52
AP		 748
749 /* CSI */
750 /* Camera power: default - off */
751 ret = gpio_request_array(mx31_3ds_camera_gpios,
752 ARRAY_SIZE(mx31_3ds_camera_gpios));
753 if (ret) {
754 pr_err("Failed to request camera gpios");
755 iclink_ov2640.power = NULL;
756 }
757
afa77ef3 758 mx31_3ds_init_camera();
5fb86e5d
PR		 759
760 imx31_add_imx_ssi(0, &mx31_3ds_ssi_pdata);
761
762 imx_add_platform_device("imx_mc13783", 0, NULL, 0, NULL, 0);
1553a1ec
FE		 763}
764
11a332ad 765static void __init mx31_3ds_timer_init(void)
1553a1ec 766{
30c730f8 767 mx31_clocks_init(26000000);
1553a1ec
FE		 768}
769
11a332ad
AP		 770static struct sys_timer mx31_3ds_timer = {
771 .init = mx31_3ds_timer_init,
1553a1ec
FE		 772};
773
164f7b52
AP		 774static void __init mx31_3ds_reserve(void)
775{
776 /* reserve MX31_3DS_CAMERA_BUF_SIZE bytes for mx3-camera */
716a3dc2 777 mx3_camera_base = arm_memblock_steal(MX31_3DS_CAMERA_BUF_SIZE,
164f7b52 778 MX31_3DS_CAMERA_BUF_SIZE);
164f7b52
AP		 779}
780
1553a1ec
FE		 781MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
782 /* Maintainer: Freescale Semiconductor, Inc. */
dc8f1907 783 .atag_offset = 0x100,
97976e22
UKK		 784 .map_io = mx31_map_io,
785 .init_early = imx31_init_early,
786 .init_irq = mx31_init_irq,
ffa2ea3f 787 .handle_irq = imx31_handle_irq,
97976e22 788 .timer = &mx31_3ds_timer,
e134fb2b 789 .init_machine = mx31_3ds_init,
164f7b52 790 .reserve = mx31_3ds_reserve,
65ea7884 791 .restart = mxc_restart,
1553a1ec 792MACHINE_END
Linux kernel - Deliverables
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