Commit | Line | Data |
---|---|---|
1553a1ec FE |
1 | /* |
2 | * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
1553a1ec FE |
13 | */ |
14 | ||
a2ef4562 | 15 | #include <linux/delay.h> |
b7f080cf | 16 | #include <linux/dma-mapping.h> |
1553a1ec FE |
17 | #include <linux/types.h> |
18 | #include <linux/init.h> | |
19 | #include <linux/clk.h> | |
20 | #include <linux/irq.h> | |
135cad36 | 21 | #include <linux/gpio.h> |
2b0c3677 | 22 | #include <linux/platform_device.h> |
ae7a3f13 AP |
23 | #include <linux/mfd/mc13783.h> |
24 | #include <linux/spi/spi.h> | |
e42010e0 | 25 | #include <linux/spi/l4f00242t03.h> |
ae7a3f13 | 26 | #include <linux/regulator/machine.h> |
1c50e672 FE |
27 | #include <linux/usb/otg.h> |
28 | #include <linux/usb/ulpi.h> | |
164f7b52 AP |
29 | #include <linux/memblock.h> |
30 | ||
31 | #include <media/soc_camera.h> | |
1553a1ec FE |
32 | |
33 | #include <mach/hardware.h> | |
34 | #include <asm/mach-types.h> | |
35 | #include <asm/mach/arch.h> | |
36 | #include <asm/mach/time.h> | |
37 | #include <asm/memory.h> | |
38 | #include <asm/mach/map.h> | |
716a3dc2 | 39 | #include <asm/memblock.h> |
1553a1ec | 40 | #include <mach/common.h> |
1553a1ec | 41 | #include <mach/iomux-mx3.h> |
c5d38f08 | 42 | #include <mach/3ds_debugboard.h> |
1c50e672 | 43 | #include <mach/ulpi.h> |
a2ceeef5 UKK |
44 | |
45 | #include "devices-imx31.h" | |
1553a1ec | 46 | |
b396dc45 UKK |
47 | /* CPLD IRQ line for external uart, external ethernet etc */ |
48 | #define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1) | |
49 | ||
11a332ad | 50 | static int mx31_3ds_pins[] = { |
153fa1d8 | 51 | /* UART1 */ |
63d97667 VL |
52 | MX31_PIN_CTS1__CTS1, |
53 | MX31_PIN_RTS1__RTS1, | |
54 | MX31_PIN_TXD1__TXD1, | |
135cad36 ML |
55 | MX31_PIN_RXD1__RXD1, |
56 | IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO), | |
e42010e0 | 57 | /*SPI0*/ |
b2a08e3e FE |
58 | IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_ALT1), |
59 | IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_ALT1), | |
a1ac4424 AP |
60 | /* SPI 1 */ |
61 | MX31_PIN_CSPI2_SCLK__SCLK, | |
62 | MX31_PIN_CSPI2_MOSI__MOSI, | |
63 | MX31_PIN_CSPI2_MISO__MISO, | |
64 | MX31_PIN_CSPI2_SPI_RDY__SPI_RDY, | |
65 | MX31_PIN_CSPI2_SS0__SS0, | |
66 | MX31_PIN_CSPI2_SS2__SS2, /*CS for MC13783 */ | |
ae7a3f13 AP |
67 | /* MC13783 IRQ */ |
68 | IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO), | |
a2ef4562 ML |
69 | /* USB OTG reset */ |
70 | IOMUX_MODE(MX31_PIN_USB_PWR, IOMUX_CONFIG_GPIO), | |
71 | /* USB OTG */ | |
72 | MX31_PIN_USBOTG_DATA0__USBOTG_DATA0, | |
73 | MX31_PIN_USBOTG_DATA1__USBOTG_DATA1, | |
74 | MX31_PIN_USBOTG_DATA2__USBOTG_DATA2, | |
75 | MX31_PIN_USBOTG_DATA3__USBOTG_DATA3, | |
76 | MX31_PIN_USBOTG_DATA4__USBOTG_DATA4, | |
77 | MX31_PIN_USBOTG_DATA5__USBOTG_DATA5, | |
78 | MX31_PIN_USBOTG_DATA6__USBOTG_DATA6, | |
79 | MX31_PIN_USBOTG_DATA7__USBOTG_DATA7, | |
80 | MX31_PIN_USBOTG_CLK__USBOTG_CLK, | |
81 | MX31_PIN_USBOTG_DIR__USBOTG_DIR, | |
82 | MX31_PIN_USBOTG_NXT__USBOTG_NXT, | |
83 | MX31_PIN_USBOTG_STP__USBOTG_STP, | |
54c1f636 AP |
84 | /*Keyboard*/ |
85 | MX31_PIN_KEY_ROW0_KEY_ROW0, | |
86 | MX31_PIN_KEY_ROW1_KEY_ROW1, | |
87 | MX31_PIN_KEY_ROW2_KEY_ROW2, | |
88 | MX31_PIN_KEY_COL0_KEY_COL0, | |
89 | MX31_PIN_KEY_COL1_KEY_COL1, | |
90 | MX31_PIN_KEY_COL2_KEY_COL2, | |
91 | MX31_PIN_KEY_COL3_KEY_COL3, | |
0d95b75e FE |
92 | /* USB Host 2 */ |
93 | IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC), | |
94 | IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC), | |
95 | IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC), | |
96 | IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC), | |
97 | IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC), | |
98 | IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC), | |
99 | IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT1), | |
100 | IOMUX_MODE(MX31_PIN_PC_BVD1, IOMUX_CONFIG_ALT1), | |
101 | IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT1), | |
102 | IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT1), | |
103 | IOMUX_MODE(MX31_PIN_IOIS16, IOMUX_CONFIG_ALT1), | |
104 | IOMUX_MODE(MX31_PIN_PC_RW_B, IOMUX_CONFIG_ALT1), | |
105 | /* USB Host2 reset */ | |
106 | IOMUX_MODE(MX31_PIN_USB_BYP, IOMUX_CONFIG_GPIO), | |
3d943024 FE |
107 | /* I2C1 */ |
108 | MX31_PIN_I2C_CLK__I2C1_SCL, | |
109 | MX31_PIN_I2C_DAT__I2C1_SDA, | |
0ce88b34 AP |
110 | /* SDHC1 */ |
111 | MX31_PIN_SD1_DATA3__SD1_DATA3, | |
112 | MX31_PIN_SD1_DATA2__SD1_DATA2, | |
113 | MX31_PIN_SD1_DATA1__SD1_DATA1, | |
114 | MX31_PIN_SD1_DATA0__SD1_DATA0, | |
115 | MX31_PIN_SD1_CLK__SD1_CLK, | |
116 | MX31_PIN_SD1_CMD__SD1_CMD, | |
117 | MX31_PIN_GPIO3_1__GPIO3_1, /* Card detect */ | |
118 | MX31_PIN_GPIO3_0__GPIO3_0, /* OE */ | |
e42010e0 AP |
119 | /* Framebuffer */ |
120 | MX31_PIN_LD0__LD0, | |
121 | MX31_PIN_LD1__LD1, | |
122 | MX31_PIN_LD2__LD2, | |
123 | MX31_PIN_LD3__LD3, | |
124 | MX31_PIN_LD4__LD4, | |
125 | MX31_PIN_LD5__LD5, | |
126 | MX31_PIN_LD6__LD6, | |
127 | MX31_PIN_LD7__LD7, | |
128 | MX31_PIN_LD8__LD8, | |
129 | MX31_PIN_LD9__LD9, | |
130 | MX31_PIN_LD10__LD10, | |
131 | MX31_PIN_LD11__LD11, | |
132 | MX31_PIN_LD12__LD12, | |
133 | MX31_PIN_LD13__LD13, | |
134 | MX31_PIN_LD14__LD14, | |
135 | MX31_PIN_LD15__LD15, | |
136 | MX31_PIN_LD16__LD16, | |
137 | MX31_PIN_LD17__LD17, | |
138 | MX31_PIN_VSYNC3__VSYNC3, | |
139 | MX31_PIN_HSYNC__HSYNC, | |
140 | MX31_PIN_FPSHIFT__FPSHIFT, | |
141 | MX31_PIN_CONTRAST__CONTRAST, | |
164f7b52 AP |
142 | /* CSI */ |
143 | MX31_PIN_CSI_D6__CSI_D6, | |
144 | MX31_PIN_CSI_D7__CSI_D7, | |
145 | MX31_PIN_CSI_D8__CSI_D8, | |
146 | MX31_PIN_CSI_D9__CSI_D9, | |
147 | MX31_PIN_CSI_D10__CSI_D10, | |
148 | MX31_PIN_CSI_D11__CSI_D11, | |
149 | MX31_PIN_CSI_D12__CSI_D12, | |
150 | MX31_PIN_CSI_D13__CSI_D13, | |
151 | MX31_PIN_CSI_D14__CSI_D14, | |
152 | MX31_PIN_CSI_D15__CSI_D15, | |
153 | MX31_PIN_CSI_HSYNC__CSI_HSYNC, | |
154 | MX31_PIN_CSI_MCLK__CSI_MCLK, | |
155 | MX31_PIN_CSI_PIXCLK__CSI_PIXCLK, | |
156 | MX31_PIN_CSI_VSYNC__CSI_VSYNC, | |
157 | MX31_PIN_CSI_D5__GPIO3_5, /* CMOS PWDN */ | |
158 | IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_GPIO), /* CMOS reset */ | |
159 | }; | |
160 | ||
161 | /* | |
162 | * Camera support | |
163 | */ | |
164 | static phys_addr_t mx3_camera_base __initdata; | |
165 | #define MX31_3DS_CAMERA_BUF_SIZE SZ_8M | |
166 | ||
167 | #define MX31_3DS_GPIO_CAMERA_PW IOMUX_TO_GPIO(MX31_PIN_CSI_D5) | |
168 | #define MX31_3DS_GPIO_CAMERA_RST IOMUX_TO_GPIO(MX31_PIN_RI_DTE1) | |
169 | ||
170 | static struct gpio mx31_3ds_camera_gpios[] = { | |
171 | { MX31_3DS_GPIO_CAMERA_PW, GPIOF_OUT_INIT_HIGH, "camera-power" }, | |
172 | { MX31_3DS_GPIO_CAMERA_RST, GPIOF_OUT_INIT_HIGH, "camera-reset" }, | |
173 | }; | |
174 | ||
afa77ef3 UKK |
175 | static const struct mx3_camera_pdata mx31_3ds_camera_pdata __initconst = { |
176 | .flags = MX3_CAMERA_DATAWIDTH_10, | |
177 | .mclk_10khz = 2600, | |
178 | }; | |
179 | ||
180 | static int __init mx31_3ds_init_camera(void) | |
164f7b52 | 181 | { |
afa77ef3 UKK |
182 | int dma, ret = -ENOMEM; |
183 | struct platform_device *pdev = | |
184 | imx31_alloc_mx3_camera(&mx31_3ds_camera_pdata); | |
185 | ||
186 | if (IS_ERR(pdev)) | |
187 | return PTR_ERR(pdev); | |
164f7b52 AP |
188 | |
189 | if (!mx3_camera_base) | |
afa77ef3 | 190 | goto err; |
164f7b52 | 191 | |
afa77ef3 | 192 | dma = dma_declare_coherent_memory(&pdev->dev, |
164f7b52 AP |
193 | mx3_camera_base, mx3_camera_base, |
194 | MX31_3DS_CAMERA_BUF_SIZE, | |
195 | DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE); | |
196 | ||
197 | if (!(dma & DMA_MEMORY_MAP)) | |
afa77ef3 | 198 | goto err; |
164f7b52 | 199 | |
afa77ef3 UKK |
200 | ret = platform_device_add(pdev); |
201 | if (ret) | |
202 | err: | |
203 | platform_device_put(pdev); | |
204 | ||
205 | return ret; | |
164f7b52 AP |
206 | } |
207 | ||
208 | static int mx31_3ds_camera_power(struct device *dev, int on) | |
209 | { | |
210 | /* enable or disable the camera */ | |
211 | pr_debug("%s: %s the camera\n", __func__, on ? "ENABLE" : "DISABLE"); | |
212 | gpio_set_value(MX31_3DS_GPIO_CAMERA_PW, on ? 0 : 1); | |
213 | ||
214 | if (!on) | |
215 | goto out; | |
216 | ||
217 | /* If enabled, give a reset impulse */ | |
218 | gpio_set_value(MX31_3DS_GPIO_CAMERA_RST, 0); | |
219 | msleep(20); | |
220 | gpio_set_value(MX31_3DS_GPIO_CAMERA_RST, 1); | |
221 | msleep(100); | |
222 | ||
223 | out: | |
224 | return 0; | |
225 | } | |
226 | ||
227 | static struct i2c_board_info mx31_3ds_i2c_camera = { | |
228 | I2C_BOARD_INFO("ov2640", 0x30), | |
229 | }; | |
230 | ||
231 | static struct regulator_bulk_data mx31_3ds_camera_regs[] = { | |
232 | { .supply = "cmos_vcore" }, | |
233 | { .supply = "cmos_2v8" }, | |
234 | }; | |
235 | ||
236 | static struct soc_camera_link iclink_ov2640 = { | |
237 | .bus_id = 0, | |
238 | .board_info = &mx31_3ds_i2c_camera, | |
239 | .i2c_adapter_id = 0, | |
240 | .power = mx31_3ds_camera_power, | |
241 | .regulators = mx31_3ds_camera_regs, | |
242 | .num_regulators = ARRAY_SIZE(mx31_3ds_camera_regs), | |
243 | }; | |
244 | ||
245 | static struct platform_device mx31_3ds_ov2640 = { | |
246 | .name = "soc-camera-pdrv", | |
247 | .id = 0, | |
248 | .dev = { | |
249 | .platform_data = &iclink_ov2640, | |
250 | }, | |
251 | }; | |
252 | ||
e42010e0 AP |
253 | /* |
254 | * FB support | |
255 | */ | |
256 | static const struct fb_videomode fb_modedb[] = { | |
257 | { /* 480x640 @ 60 Hz */ | |
258 | .name = "Epson-VGA", | |
259 | .refresh = 60, | |
260 | .xres = 480, | |
261 | .yres = 640, | |
262 | .pixclock = 41701, | |
263 | .left_margin = 20, | |
264 | .right_margin = 41, | |
265 | .upper_margin = 10, | |
266 | .lower_margin = 5, | |
267 | .hsync_len = 20, | |
268 | .vsync_len = 10, | |
269 | .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT, | |
270 | .vmode = FB_VMODE_NONINTERLACED, | |
271 | .flag = 0, | |
272 | }, | |
273 | }; | |
274 | ||
275 | static struct ipu_platform_data mx3_ipu_data = { | |
276 | .irq_base = MXC_IPU_IRQ_START, | |
277 | }; | |
278 | ||
afa77ef3 | 279 | static struct mx3fb_platform_data mx3fb_pdata __initdata = { |
e42010e0 AP |
280 | .name = "Epson-VGA", |
281 | .mode = fb_modedb, | |
282 | .num_modes = ARRAY_SIZE(fb_modedb), | |
283 | }; | |
284 | ||
285 | /* LCD */ | |
286 | static struct l4f00242t03_pdata mx31_3ds_l4f00242t03_pdata = { | |
287 | .reset_gpio = IOMUX_TO_GPIO(MX31_PIN_LCS1), | |
288 | .data_enable_gpio = IOMUX_TO_GPIO(MX31_PIN_SER_RS), | |
0ce88b34 AP |
289 | }; |
290 | ||
291 | /* | |
292 | * Support for SD card slot in personality board | |
293 | */ | |
294 | #define MX31_3DS_GPIO_SDHC1_CD IOMUX_TO_GPIO(MX31_PIN_GPIO3_1) | |
295 | #define MX31_3DS_GPIO_SDHC1_BE IOMUX_TO_GPIO(MX31_PIN_GPIO3_0) | |
296 | ||
297 | static struct gpio mx31_3ds_sdhc1_gpios[] = { | |
298 | { MX31_3DS_GPIO_SDHC1_CD, GPIOF_IN, "sdhc1-card-detect" }, | |
299 | { MX31_3DS_GPIO_SDHC1_BE, GPIOF_OUT_INIT_LOW, "sdhc1-bus-en" }, | |
300 | }; | |
301 | ||
302 | static int mx31_3ds_sdhc1_init(struct device *dev, | |
303 | irq_handler_t detect_irq, | |
304 | void *data) | |
305 | { | |
306 | int ret; | |
307 | ||
308 | ret = gpio_request_array(mx31_3ds_sdhc1_gpios, | |
309 | ARRAY_SIZE(mx31_3ds_sdhc1_gpios)); | |
310 | if (ret) { | |
311 | pr_warning("Unable to request the SD/MMC GPIOs.\n"); | |
312 | return ret; | |
313 | } | |
314 | ||
315 | ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO3_1), | |
316 | detect_irq, IRQF_DISABLED | | |
317 | IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, | |
318 | "sdhc1-detect", data); | |
319 | if (ret) { | |
320 | pr_warning("Unable to request the SD/MMC card-detect IRQ.\n"); | |
321 | goto gpio_free; | |
322 | } | |
323 | ||
324 | return 0; | |
325 | ||
326 | gpio_free: | |
327 | gpio_free_array(mx31_3ds_sdhc1_gpios, | |
328 | ARRAY_SIZE(mx31_3ds_sdhc1_gpios)); | |
329 | return ret; | |
330 | } | |
331 | ||
332 | static void mx31_3ds_sdhc1_exit(struct device *dev, void *data) | |
333 | { | |
334 | free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO3_1), data); | |
335 | gpio_free_array(mx31_3ds_sdhc1_gpios, | |
336 | ARRAY_SIZE(mx31_3ds_sdhc1_gpios)); | |
337 | } | |
338 | ||
339 | static void mx31_3ds_sdhc1_setpower(struct device *dev, unsigned int vdd) | |
340 | { | |
341 | /* | |
342 | * While the voltage stuff is done by the driver, activate the | |
343 | * Buffer Enable Pin only if there is a card in slot to fix the card | |
344 | * voltage issue caused by bi-directional chip TXB0108 on 3Stack. | |
345 | * Done here because at this stage we have for sure a debounced value | |
346 | * of the presence of the card, showed by the value of vdd. | |
347 | * 7 == ilog2(MMC_VDD_165_195) | |
348 | */ | |
349 | if (vdd > 7) | |
350 | gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 1); | |
351 | else | |
352 | gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 0); | |
353 | } | |
354 | ||
355 | static struct imxmmc_platform_data sdhc1_pdata = { | |
356 | .init = mx31_3ds_sdhc1_init, | |
357 | .exit = mx31_3ds_sdhc1_exit, | |
358 | .setpower = mx31_3ds_sdhc1_setpower, | |
54c1f636 AP |
359 | }; |
360 | ||
361 | /* | |
362 | * Matrix keyboard | |
363 | */ | |
364 | ||
365 | static const uint32_t mx31_3ds_keymap[] = { | |
366 | KEY(0, 0, KEY_UP), | |
367 | KEY(0, 1, KEY_DOWN), | |
368 | KEY(1, 0, KEY_RIGHT), | |
369 | KEY(1, 1, KEY_LEFT), | |
370 | KEY(1, 2, KEY_ENTER), | |
371 | KEY(2, 0, KEY_F6), | |
372 | KEY(2, 1, KEY_F8), | |
373 | KEY(2, 2, KEY_F9), | |
374 | KEY(2, 3, KEY_F10), | |
375 | }; | |
376 | ||
d690b4c4 | 377 | static const struct matrix_keymap_data mx31_3ds_keymap_data __initconst = { |
54c1f636 AP |
378 | .keymap = mx31_3ds_keymap, |
379 | .keymap_size = ARRAY_SIZE(mx31_3ds_keymap), | |
ae7a3f13 AP |
380 | }; |
381 | ||
382 | /* Regulators */ | |
383 | static struct regulator_init_data pwgtx_init = { | |
384 | .constraints = { | |
385 | .boot_on = 1, | |
386 | .always_on = 1, | |
387 | }, | |
388 | }; | |
389 | ||
0d95b75e FE |
390 | static struct regulator_init_data gpo_init = { |
391 | .constraints = { | |
392 | .boot_on = 1, | |
393 | .always_on = 1, | |
394 | } | |
395 | }; | |
396 | ||
0ce88b34 AP |
397 | static struct regulator_consumer_supply vmmc2_consumers[] = { |
398 | REGULATOR_SUPPLY("vmmc", "mxc-mmc.0"), | |
399 | }; | |
400 | ||
401 | static struct regulator_init_data vmmc2_init = { | |
402 | .constraints = { | |
403 | .min_uV = 3000000, | |
404 | .max_uV = 3000000, | |
405 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | | |
406 | REGULATOR_CHANGE_STATUS, | |
407 | }, | |
408 | .num_consumer_supplies = ARRAY_SIZE(vmmc2_consumers), | |
409 | .consumer_supplies = vmmc2_consumers, | |
410 | }; | |
411 | ||
e42010e0 | 412 | static struct regulator_consumer_supply vmmc1_consumers[] = { |
0556dc34 | 413 | REGULATOR_SUPPLY("vcore", "spi0.0"), |
164f7b52 | 414 | REGULATOR_SUPPLY("cmos_2v8", "soc-camera-pdrv.0"), |
e42010e0 AP |
415 | }; |
416 | ||
417 | static struct regulator_init_data vmmc1_init = { | |
418 | .constraints = { | |
419 | .min_uV = 2800000, | |
420 | .max_uV = 2800000, | |
421 | .apply_uV = 1, | |
422 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | | |
423 | REGULATOR_CHANGE_STATUS, | |
424 | }, | |
425 | .num_consumer_supplies = ARRAY_SIZE(vmmc1_consumers), | |
426 | .consumer_supplies = vmmc1_consumers, | |
427 | }; | |
428 | ||
429 | static struct regulator_consumer_supply vgen_consumers[] = { | |
0556dc34 | 430 | REGULATOR_SUPPLY("vdd", "spi0.0"), |
e42010e0 AP |
431 | }; |
432 | ||
433 | static struct regulator_init_data vgen_init = { | |
434 | .constraints = { | |
435 | .min_uV = 1800000, | |
436 | .max_uV = 1800000, | |
437 | .apply_uV = 1, | |
438 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | | |
439 | REGULATOR_CHANGE_STATUS, | |
440 | }, | |
441 | .num_consumer_supplies = ARRAY_SIZE(vgen_consumers), | |
442 | .consumer_supplies = vgen_consumers, | |
443 | }; | |
444 | ||
164f7b52 AP |
445 | static struct regulator_consumer_supply vvib_consumers[] = { |
446 | REGULATOR_SUPPLY("cmos_vcore", "soc-camera-pdrv.0"), | |
447 | }; | |
448 | ||
449 | static struct regulator_init_data vvib_init = { | |
450 | .constraints = { | |
451 | .min_uV = 1300000, | |
452 | .max_uV = 1300000, | |
453 | .apply_uV = 1, | |
454 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | | |
455 | REGULATOR_CHANGE_STATUS, | |
456 | }, | |
457 | .num_consumer_supplies = ARRAY_SIZE(vvib_consumers), | |
458 | .consumer_supplies = vvib_consumers, | |
459 | }; | |
460 | ||
5836372e | 461 | static struct mc13xxx_regulator_init_data mx31_3ds_regulators[] = { |
ae7a3f13 | 462 | { |
57c78e35 | 463 | .id = MC13783_REG_PWGT1SPI, /* Power Gate for ARM core. */ |
ae7a3f13 AP |
464 | .init_data = &pwgtx_init, |
465 | }, { | |
57c78e35 | 466 | .id = MC13783_REG_PWGT2SPI, /* Power Gate for L2 Cache. */ |
ae7a3f13 | 467 | .init_data = &pwgtx_init, |
0d95b75e FE |
468 | }, { |
469 | ||
c97b7393 | 470 | .id = MC13783_REG_GPO1, /* Turn on 1.8V */ |
0d95b75e FE |
471 | .init_data = &gpo_init, |
472 | }, { | |
c97b7393 | 473 | .id = MC13783_REG_GPO3, /* Turn on 3.3V */ |
0d95b75e | 474 | .init_data = &gpo_init, |
0ce88b34 AP |
475 | }, { |
476 | .id = MC13783_REG_VMMC2, /* Power MMC/SD, WiFi/Bluetooth. */ | |
477 | .init_data = &vmmc2_init, | |
e42010e0 AP |
478 | }, { |
479 | .id = MC13783_REG_VMMC1, /* Power LCD, CMOS, FM, GPS, Accel. */ | |
480 | .init_data = &vmmc1_init, | |
481 | }, { | |
482 | .id = MC13783_REG_VGEN, /* Power LCD */ | |
483 | .init_data = &vgen_init, | |
164f7b52 AP |
484 | }, { |
485 | .id = MC13783_REG_VVIB, /* Power CMOS */ | |
486 | .init_data = &vvib_init, | |
ae7a3f13 AP |
487 | }, |
488 | }; | |
489 | ||
490 | /* MC13783 */ | |
4ec1b54c AS |
491 | static struct mc13xxx_platform_data mc13783_pdata = { |
492 | .regulators = { | |
493 | .regulators = mx31_3ds_regulators, | |
494 | .num_regulators = ARRAY_SIZE(mx31_3ds_regulators), | |
495 | }, | |
039d7ba4 | 496 | .flags = MC13XXX_USE_TOUCHSCREEN | MC13XXX_USE_RTC, |
a1ac4424 AP |
497 | }; |
498 | ||
499 | /* SPI */ | |
e42010e0 AP |
500 | static int spi0_internal_chipselect[] = { |
501 | MXC_SPI_CS(2), | |
502 | }; | |
503 | ||
504 | static const struct spi_imx_master spi0_pdata __initconst = { | |
505 | .chipselect = spi0_internal_chipselect, | |
506 | .num_chipselect = ARRAY_SIZE(spi0_internal_chipselect), | |
507 | }; | |
508 | ||
a1ac4424 AP |
509 | static int spi1_internal_chipselect[] = { |
510 | MXC_SPI_CS(0), | |
511 | MXC_SPI_CS(2), | |
512 | }; | |
513 | ||
06606ff1 | 514 | static const struct spi_imx_master spi1_pdata __initconst = { |
a1ac4424 AP |
515 | .chipselect = spi1_internal_chipselect, |
516 | .num_chipselect = ARRAY_SIZE(spi1_internal_chipselect), | |
63d97667 VL |
517 | }; |
518 | ||
ae7a3f13 AP |
519 | static struct spi_board_info mx31_3ds_spi_devs[] __initdata = { |
520 | { | |
521 | .modalias = "mc13783", | |
522 | .max_speed_hz = 1000000, | |
523 | .bus_num = 1, | |
524 | .chip_select = 1, /* SS2 */ | |
525 | .platform_data = &mc13783_pdata, | |
526 | .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3), | |
527 | .mode = SPI_CS_HIGH, | |
e42010e0 AP |
528 | }, { |
529 | .modalias = "l4f00242t03", | |
530 | .max_speed_hz = 5000000, | |
531 | .bus_num = 0, | |
532 | .chip_select = 0, /* SS2 */ | |
533 | .platform_data = &mx31_3ds_l4f00242t03_pdata, | |
ae7a3f13 AP |
534 | }, |
535 | }; | |
536 | ||
a1b67b95 AP |
537 | /* |
538 | * NAND Flash | |
539 | */ | |
a2ceeef5 UKK |
540 | static const struct mxc_nand_platform_data |
541 | mx31_3ds_nand_board_info __initconst = { | |
a1b67b95 AP |
542 | .width = 1, |
543 | .hw_ecc = 1, | |
5328ecbb | 544 | #ifdef CONFIG_MACH_MX31_3DS_MXC_NAND_USE_BBT |
a1b67b95 AP |
545 | .flash_bbt = 1, |
546 | #endif | |
547 | }; | |
548 | ||
a2ef4562 ML |
549 | /* |
550 | * USB OTG | |
551 | */ | |
552 | ||
553 | #define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ | |
554 | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) | |
555 | ||
556 | #define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR) | |
0d95b75e | 557 | #define USBH2_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_BYP) |
a2ef4562 | 558 | |
41f63475 | 559 | static int mx31_3ds_usbotg_init(void) |
a2ef4562 | 560 | { |
41f63475 FE |
561 | int err; |
562 | ||
a2ef4562 ML |
563 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG); |
564 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG); | |
565 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG); | |
566 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG); | |
567 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG); | |
568 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG); | |
569 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG); | |
570 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG); | |
571 | mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG); | |
572 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG); | |
573 | mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG); | |
574 | mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG); | |
575 | ||
41f63475 FE |
576 | err = gpio_request(USBOTG_RST_B, "otgusb-reset"); |
577 | if (err) { | |
578 | pr_err("Failed to request the USB OTG reset gpio\n"); | |
579 | return err; | |
580 | } | |
581 | ||
582 | err = gpio_direction_output(USBOTG_RST_B, 0); | |
583 | if (err) { | |
584 | pr_err("Failed to drive the USB OTG reset gpio\n"); | |
585 | goto usbotg_free_reset; | |
586 | } | |
587 | ||
a2ef4562 ML |
588 | mdelay(1); |
589 | gpio_set_value(USBOTG_RST_B, 1); | |
41f63475 FE |
590 | return 0; |
591 | ||
592 | usbotg_free_reset: | |
593 | gpio_free(USBOTG_RST_B); | |
594 | return err; | |
a2ef4562 ML |
595 | } |
596 | ||
4bd597b6 SH |
597 | static int mx31_3ds_otg_init(struct platform_device *pdev) |
598 | { | |
599 | return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED); | |
600 | } | |
601 | ||
602 | static int mx31_3ds_host2_init(struct platform_device *pdev) | |
0d95b75e FE |
603 | { |
604 | int err; | |
605 | ||
606 | mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG); | |
607 | mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG); | |
608 | mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG); | |
609 | mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG); | |
610 | mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG); | |
611 | mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG); | |
612 | mxc_iomux_set_pad(MX31_PIN_PC_VS2, USB_PAD_CFG); | |
613 | mxc_iomux_set_pad(MX31_PIN_PC_BVD1, USB_PAD_CFG); | |
614 | mxc_iomux_set_pad(MX31_PIN_PC_BVD2, USB_PAD_CFG); | |
615 | mxc_iomux_set_pad(MX31_PIN_PC_RST, USB_PAD_CFG); | |
616 | mxc_iomux_set_pad(MX31_PIN_IOIS16, USB_PAD_CFG); | |
617 | mxc_iomux_set_pad(MX31_PIN_PC_RW_B, USB_PAD_CFG); | |
618 | ||
619 | err = gpio_request(USBH2_RST_B, "usbh2-reset"); | |
620 | if (err) { | |
621 | pr_err("Failed to request the USB Host 2 reset gpio\n"); | |
622 | return err; | |
623 | } | |
624 | ||
625 | err = gpio_direction_output(USBH2_RST_B, 0); | |
626 | if (err) { | |
627 | pr_err("Failed to drive the USB Host 2 reset gpio\n"); | |
628 | goto usbotg_free_reset; | |
629 | } | |
630 | ||
631 | mdelay(1); | |
632 | gpio_set_value(USBH2_RST_B, 1); | |
4bd597b6 SH |
633 | |
634 | mdelay(10); | |
635 | ||
636 | return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED); | |
0d95b75e FE |
637 | |
638 | usbotg_free_reset: | |
639 | gpio_free(USBH2_RST_B); | |
640 | return err; | |
641 | } | |
642 | ||
1c50e672 | 643 | static struct mxc_usbh_platform_data otg_pdata __initdata = { |
4bd597b6 | 644 | .init = mx31_3ds_otg_init, |
1c50e672 | 645 | .portsc = MXC_EHCI_MODE_ULPI, |
1c50e672 | 646 | }; |
0d95b75e FE |
647 | |
648 | static struct mxc_usbh_platform_data usbh2_pdata __initdata = { | |
649 | .init = mx31_3ds_host2_init, | |
650 | .portsc = MXC_EHCI_MODE_ULPI, | |
0d95b75e | 651 | }; |
1c50e672 | 652 | |
9e1dde33 | 653 | static const struct fsl_usb2_platform_data usbotg_pdata __initconst = { |
a2ef4562 ML |
654 | .operating_mode = FSL_USB2_DR_DEVICE, |
655 | .phy_mode = FSL_USB2_PHY_ULPI, | |
656 | }; | |
657 | ||
1c50e672 FE |
658 | static int otg_mode_host; |
659 | ||
660 | static int __init mx31_3ds_otg_mode(char *options) | |
661 | { | |
662 | if (!strcmp(options, "host")) | |
663 | otg_mode_host = 1; | |
664 | else if (!strcmp(options, "device")) | |
665 | otg_mode_host = 0; | |
666 | else | |
667 | pr_info("otg_mode neither \"host\" nor \"device\". " | |
668 | "Defaulting to device\n"); | |
669 | return 0; | |
670 | } | |
671 | __setup("otg_mode=", mx31_3ds_otg_mode); | |
672 | ||
16cf5c41 | 673 | static const struct imxuart_platform_data uart_pdata __initconst = { |
153fa1d8 ML |
674 | .flags = IMXUART_HAVE_RTSCTS, |
675 | }; | |
1553a1ec | 676 | |
3d943024 FE |
677 | static const struct imxi2c_platform_data mx31_3ds_i2c0_data __initconst = { |
678 | .bitrate = 100000, | |
679 | }; | |
680 | ||
164f7b52 AP |
681 | static struct platform_device *devices[] __initdata = { |
682 | &mx31_3ds_ov2640, | |
683 | }; | |
684 | ||
e134fb2b | 685 | static void __init mx31_3ds_init(void) |
1553a1ec | 686 | { |
164f7b52 AP |
687 | int ret; |
688 | ||
b78d8e59 SG |
689 | imx31_soc_init(); |
690 | ||
b2a08e3e FE |
691 | /* Configure SPI1 IOMUX */ |
692 | mxc_iomux_set_gpr(MUX_PGP_CSPI_BB, true); | |
693 | ||
11a332ad AP |
694 | mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins), |
695 | "mx31_3ds"); | |
153fa1d8 | 696 | |
16cf5c41 | 697 | imx31_add_imx_uart0(&uart_pdata); |
a2ceeef5 | 698 | imx31_add_mxc_nand(&mx31_3ds_nand_board_info); |
ae7a3f13 | 699 | |
4a74bddc | 700 | imx31_add_spi_imx1(&spi1_pdata); |
ae7a3f13 AP |
701 | spi_register_board_info(mx31_3ds_spi_devs, |
702 | ARRAY_SIZE(mx31_3ds_spi_devs)); | |
135cad36 | 703 | |
164f7b52 AP |
704 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
705 | ||
d690b4c4 | 706 | imx31_add_imx_keypad(&mx31_3ds_keymap_data); |
54c1f636 | 707 | |
a2ef4562 | 708 | mx31_3ds_usbotg_init(); |
1c50e672 | 709 | if (otg_mode_host) { |
48f6b099 SH |
710 | otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | |
711 | ULPI_OTG_DRVVBUS_EXT); | |
712 | if (otg_pdata.otg) | |
713 | imx31_add_mxc_ehci_otg(&otg_pdata); | |
1c50e672 | 714 | } |
48f6b099 SH |
715 | usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | |
716 | ULPI_OTG_DRVVBUS_EXT); | |
717 | if (usbh2_pdata.otg) | |
718 | imx31_add_mxc_ehci_hs(2, &usbh2_pdata); | |
719 | ||
1c50e672 FE |
720 | if (!otg_mode_host) |
721 | imx31_add_fsl_usb2_udc(&usbotg_pdata); | |
a2ef4562 | 722 | |
b8be7b9a RP |
723 | if (mxc_expio_init(MX31_CS5_BASE_ADDR, EXPIO_PARENT_INT)) |
724 | printk(KERN_WARNING "Init of the debug board failed, all " | |
725 | "devices on the debug board are unusable.\n"); | |
bfdde3a9 | 726 | imx31_add_imx2_wdt(NULL); |
3d943024 | 727 | imx31_add_imx_i2c0(&mx31_3ds_i2c0_data); |
0ce88b34 | 728 | imx31_add_mxc_mmc(0, &sdhc1_pdata); |
e42010e0 AP |
729 | |
730 | imx31_add_spi_imx0(&spi0_pdata); | |
afa77ef3 UKK |
731 | imx31_add_ipu_core(&mx3_ipu_data); |
732 | imx31_add_mx3_sdc_fb(&mx3fb_pdata); | |
164f7b52 AP |
733 | |
734 | /* CSI */ | |
735 | /* Camera power: default - off */ | |
736 | ret = gpio_request_array(mx31_3ds_camera_gpios, | |
737 | ARRAY_SIZE(mx31_3ds_camera_gpios)); | |
738 | if (ret) { | |
739 | pr_err("Failed to request camera gpios"); | |
740 | iclink_ov2640.power = NULL; | |
741 | } | |
742 | ||
afa77ef3 | 743 | mx31_3ds_init_camera(); |
1553a1ec FE |
744 | } |
745 | ||
11a332ad | 746 | static void __init mx31_3ds_timer_init(void) |
1553a1ec | 747 | { |
30c730f8 | 748 | mx31_clocks_init(26000000); |
1553a1ec FE |
749 | } |
750 | ||
11a332ad AP |
751 | static struct sys_timer mx31_3ds_timer = { |
752 | .init = mx31_3ds_timer_init, | |
1553a1ec FE |
753 | }; |
754 | ||
164f7b52 AP |
755 | static void __init mx31_3ds_reserve(void) |
756 | { | |
757 | /* reserve MX31_3DS_CAMERA_BUF_SIZE bytes for mx3-camera */ | |
716a3dc2 | 758 | mx3_camera_base = arm_memblock_steal(MX31_3DS_CAMERA_BUF_SIZE, |
164f7b52 | 759 | MX31_3DS_CAMERA_BUF_SIZE); |
164f7b52 AP |
760 | } |
761 | ||
1553a1ec FE |
762 | MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)") |
763 | /* Maintainer: Freescale Semiconductor, Inc. */ | |
dc8f1907 | 764 | .atag_offset = 0x100, |
97976e22 UKK |
765 | .map_io = mx31_map_io, |
766 | .init_early = imx31_init_early, | |
767 | .init_irq = mx31_init_irq, | |
ffa2ea3f | 768 | .handle_irq = imx31_handle_irq, |
97976e22 | 769 | .timer = &mx31_3ds_timer, |
e134fb2b | 770 | .init_machine = mx31_3ds_init, |
164f7b52 | 771 | .reserve = mx31_3ds_reserve, |
65ea7884 | 772 | .restart = mxc_restart, |
1553a1ec | 773 | MACHINE_END |