[deliverable/linux.git] / arch / arm / mach-imx / mach-mx31ads.c

/*
 *  Copyright (C) 2000 Deep Blue Solutions Ltd
 *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
 *  Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/types.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/serial_8250.h>
#include <linux/gpio.h>
#include <linux/i2c.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>

#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/memory.h>
#include <asm/mach/map.h>
#include <mach/common.h>

#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
#include <linux/mfd/wm8350/audio.h>
#include <linux/mfd/wm8350/core.h>
#include <linux/mfd/wm8350/pmic.h>
#endif

#include "devices-imx31.h"
#include "iomux-mx3.h"

/* Base address of PBC controller */
#define PBC_BASE_ADDRESS	MX31_CS4_BASE_ADDR_VIRT

/* PBC Board interrupt status register */
#define PBC_INTSTATUS           0x000016

/* PBC Board interrupt current status register */
#define PBC_INTCURR_STATUS      0x000018

/* PBC Interrupt mask register set address */
#define PBC_INTMASK_SET         0x00001A

/* PBC Interrupt mask register clear address */
#define PBC_INTMASK_CLEAR       0x00001C

/* External UART A */
#define PBC_SC16C652_UARTA      0x010000

/* External UART B */
#define PBC_SC16C652_UARTB      0x010010

#define PBC_INTSTATUS_REG	(PBC_INTSTATUS + PBC_BASE_ADDRESS)
#define PBC_INTMASK_SET_REG	(PBC_INTMASK_SET + PBC_BASE_ADDRESS)
#define PBC_INTMASK_CLEAR_REG	(PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)

#define EXPIO_INT_XUART_INTA	10
#define EXPIO_INT_XUART_INTB	11

#define MXC_MAX_EXP_IO_LINES	16

/* CS8900 */
#define EXPIO_INT_ENET_INT	8
#define CS4_CS8900_MMIO_START	0x20000

static struct irq_domain *domain;

/*
 * The serial port definition structure.
 */
static struct plat_serial8250_port serial_platform_data[] = {
	{
		.membase  = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA),
		.mapbase  = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTA),
		.uartclk  = 14745600,
		.regshift = 0,
		.iotype   = UPIO_MEM,
		.flags    = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
	}, {
		.membase  = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB),
		.mapbase  = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTB),
		.uartclk  = 14745600,
		.regshift = 0,
		.iotype   = UPIO_MEM,
		.flags    = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
	},
	{},
};

static struct platform_device serial_device = {
	.name	= "serial8250",
	.id	= 0,
	.dev	= {
		.platform_data = serial_platform_data,
	},
};

static struct resource mx31ads_cs8900_resources[] __initdata = {
	DEFINE_RES_MEM(MX31_CS4_BASE_ADDR + CS4_CS8900_MMIO_START, SZ_64K),
	DEFINE_RES_IRQ(-1),
};

static const struct platform_device_info mx31ads_cs8900_devinfo __initconst = {
	.name = "cs89x0",
	.id = 0,
	.res = mx31ads_cs8900_resources,
	.num_res = ARRAY_SIZE(mx31ads_cs8900_resources),
};

static int __init mxc_init_extuart(void)
{
	serial_platform_data[0].irq = irq_find_mapping(domain,
						       EXPIO_INT_XUART_INTA);
	serial_platform_data[1].irq = irq_find_mapping(domain,
						       EXPIO_INT_XUART_INTB);
	return platform_device_register(&serial_device);
}

static void __init mxc_init_ext_ethernet(void)
{
	mx31ads_cs8900_resources[1].start =
			irq_find_mapping(domain, EXPIO_INT_ENET_INT);
	mx31ads_cs8900_resources[1].end =
			irq_find_mapping(domain, EXPIO_INT_ENET_INT);
	platform_device_register_full(
		(struct platform_device_info *)&mx31ads_cs8900_devinfo);
}

static const struct imxuart_platform_data uart_pdata __initconst = {
	.flags = IMXUART_HAVE_RTSCTS,
};

static unsigned int uart_pins[] = {
	MX31_PIN_CTS1__CTS1,
	MX31_PIN_RTS1__RTS1,
	MX31_PIN_TXD1__TXD1,
	MX31_PIN_RXD1__RXD1
};

static inline void mxc_init_imx_uart(void)
{
	mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0");
	imx31_add_imx_uart0(&uart_pdata);
}

static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc)
{
	u32 imr_val;
	u32 int_valid;
	u32 expio_irq;

	imr_val = __raw_readw(PBC_INTMASK_SET_REG);
	int_valid = __raw_readw(PBC_INTSTATUS_REG) & imr_val;

	expio_irq = 0;
	for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
		if ((int_valid & 1) == 0)
			continue;

		generic_handle_irq(irq_find_mapping(domain, expio_irq));
	}
}

/*
 * Disable an expio pin's interrupt by setting the bit in the imr.
 * @param d	an expio virtual irq description
 */
static void expio_mask_irq(struct irq_data *d)
{
	u32 expio = d->hwirq;
	/* mask the interrupt */
	__raw_writew(1 << expio, PBC_INTMASK_CLEAR_REG);
	__raw_readw(PBC_INTMASK_CLEAR_REG);
}

/*
 * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
 * @param d	an expio virtual irq description
 */
static void expio_ack_irq(struct irq_data *d)
{
	u32 expio = d->hwirq;
	/* clear the interrupt status */
	__raw_writew(1 << expio, PBC_INTSTATUS_REG);
}

/*
 * Enable a expio pin's interrupt by clearing the bit in the imr.
 * @param d	an expio virtual irq description
 */
static void expio_unmask_irq(struct irq_data *d)
{
	u32 expio = d->hwirq;
	/* unmask the interrupt */
	__raw_writew(1 << expio, PBC_INTMASK_SET_REG);
}

static struct irq_chip expio_irq_chip = {
	.name = "EXPIO(CPLD)",
	.irq_ack = expio_ack_irq,
	.irq_mask = expio_mask_irq,
	.irq_unmask = expio_unmask_irq,
};

static void __init mx31ads_init_expio(void)
{
	int irq_base;
	int i, irq;

	printk(KERN_INFO "MX31ADS EXPIO(CPLD) hardware\n");

	/*
	 * Configure INT line as GPIO input
	 */
	mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio");

	/* disable the interrupt and clear the status */
	__raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG);
	__raw_writew(0xFFFF, PBC_INTSTATUS_REG);

	irq_base = irq_alloc_descs(-1, 0, MXC_MAX_EXP_IO_LINES, numa_node_id());
	WARN_ON(irq_base < 0);

	domain = irq_domain_add_legacy(NULL, MXC_MAX_EXP_IO_LINES, irq_base, 0,
				       &irq_domain_simple_ops, NULL);
	WARN_ON(!domain);

	for (i = irq_base; i < irq_base + MXC_MAX_EXP_IO_LINES; i++) {
		irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq);
		set_irq_flags(i, IRQF_VALID);
	}
	irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_4));
	irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
	irq_set_chained_handler(irq, mx31ads_expio_irq_handler);
}

#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
/* This section defines setup for the Wolfson Microelectronics
 * 1133-EV1 PMU/audio board.  When other PMU boards are supported the
 * regulator definitions may be shared with them, but for now they can
 * only be used with this board so would generate warnings about
 * unused statics and some of the configuration is specific to this
 * module.
 */

/* CPU */
static struct regulator_consumer_supply sw1a_consumers[] = {
	{
		.supply = "cpu_vcc",
	}
};

static struct regulator_init_data sw1a_data = {
	.constraints = {
		.name = "SW1A",
		.min_uV = 1275000,
		.max_uV = 1600000,
		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
				  REGULATOR_CHANGE_MODE,
		.valid_modes_mask = REGULATOR_MODE_NORMAL |
				    REGULATOR_MODE_FAST,
		.state_mem = {
			 .uV = 1400000,
			 .mode = REGULATOR_MODE_NORMAL,
			 .enabled = 1,
		 },
		.initial_state = PM_SUSPEND_MEM,
		.always_on = 1,
		.boot_on = 1,
	},
	.num_consumer_supplies = ARRAY_SIZE(sw1a_consumers),
	.consumer_supplies = sw1a_consumers,
};

/* System IO - High */
static struct regulator_init_data viohi_data = {
	.constraints = {
		.name = "VIOHO",
		.min_uV = 2800000,
		.max_uV = 2800000,
		.state_mem = {
			 .uV = 2800000,
			 .mode = REGULATOR_MODE_NORMAL,
			 .enabled = 1,
		 },
		.initial_state = PM_SUSPEND_MEM,
		.always_on = 1,
		.boot_on = 1,
	},
};

/* System IO - Low */
static struct regulator_init_data violo_data = {
	.constraints = {
		.name = "VIOLO",
		.min_uV = 1800000,
		.max_uV = 1800000,
		.state_mem = {
			 .uV = 1800000,
			 .mode = REGULATOR_MODE_NORMAL,
			 .enabled = 1,
		 },
		.initial_state = PM_SUSPEND_MEM,
		.always_on = 1,
		.boot_on = 1,
	},
};

/* DDR RAM */
static struct regulator_init_data sw2a_data = {
	.constraints = {
		.name = "SW2A",
		.min_uV = 1800000,
		.max_uV = 1800000,
		.valid_modes_mask = REGULATOR_MODE_NORMAL,
		.state_mem = {
			 .uV = 1800000,
			 .mode = REGULATOR_MODE_NORMAL,
			 .enabled = 1,
		 },
		.state_disk = {
			 .mode = REGULATOR_MODE_NORMAL,
			 .enabled = 0,
		 },
		.always_on = 1,
		.boot_on = 1,
		.initial_state = PM_SUSPEND_MEM,
	},
};

static struct regulator_init_data ldo1_data = {
	.constraints = {
		.name = "VCAM/VMMC1/VMMC2",
		.min_uV = 2800000,
		.max_uV = 2800000,
		.valid_modes_mask = REGULATOR_MODE_NORMAL,
		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
		.apply_uV = 1,
	},
};

static struct regulator_consumer_supply ldo2_consumers[] = {
	{ .supply = "AVDD", .dev_name = "1-001a" },
	{ .supply = "HPVDD", .dev_name = "1-001a" },
};

/* CODEC and SIM */
static struct regulator_init_data ldo2_data = {
	.constraints = {
		.name = "VESIM/VSIM/AVDD",
		.min_uV = 3300000,
		.max_uV = 3300000,
		.valid_modes_mask = REGULATOR_MODE_NORMAL,
		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
		.apply_uV = 1,
	},
	.num_consumer_supplies = ARRAY_SIZE(ldo2_consumers),
	.consumer_supplies = ldo2_consumers,
};

/* General */
static struct regulator_init_data vdig_data = {
	.constraints = {
		.name = "VDIG",
		.min_uV = 1500000,
		.max_uV = 1500000,
		.valid_modes_mask = REGULATOR_MODE_NORMAL,
		.apply_uV = 1,
		.always_on = 1,
		.boot_on = 1,
	},
};

/* Tranceivers */
static struct regulator_init_data ldo4_data = {
	.constraints = {
		.name = "VRF1/CVDD_2.775",
		.min_uV = 2500000,
		.max_uV = 2500000,
		.valid_modes_mask = REGULATOR_MODE_NORMAL,
		.apply_uV = 1,
		.always_on = 1,
		.boot_on = 1,
	},
};

static struct wm8350_led_platform_data wm8350_led_data = {
	.name            = "wm8350:white",
	.default_trigger = "heartbeat",
	.max_uA          = 27899,
};

static struct wm8350_audio_platform_data imx32ads_wm8350_setup = {
	.vmid_discharge_msecs = 1000,
	.drain_msecs = 30,
	.cap_discharge_msecs = 700,
	.vmid_charge_msecs = 700,
	.vmid_s_curve = WM8350_S_CURVE_SLOW,
	.dis_out4 = WM8350_DISCHARGE_SLOW,
	.dis_out3 = WM8350_DISCHARGE_SLOW,
	.dis_out2 = WM8350_DISCHARGE_SLOW,
	.dis_out1 = WM8350_DISCHARGE_SLOW,
	.vroi_out4 = WM8350_TIE_OFF_500R,
	.vroi_out3 = WM8350_TIE_OFF_500R,
	.vroi_out2 = WM8350_TIE_OFF_500R,
	.vroi_out1 = WM8350_TIE_OFF_500R,
	.vroi_enable = 0,
	.codec_current_on = WM8350_CODEC_ISEL_1_0,
	.codec_current_standby = WM8350_CODEC_ISEL_0_5,
	.codec_current_charge = WM8350_CODEC_ISEL_1_5,
};

static int mx31_wm8350_init(struct wm8350 *wm8350)
{
	wm8350_gpio_config(wm8350, 0, WM8350_GPIO_DIR_IN,
			   WM8350_GPIO0_PWR_ON_IN, WM8350_GPIO_ACTIVE_LOW,
			   WM8350_GPIO_PULL_UP, WM8350_GPIO_INVERT_OFF,
			   WM8350_GPIO_DEBOUNCE_ON);

	wm8350_gpio_config(wm8350, 3, WM8350_GPIO_DIR_IN,
			   WM8350_GPIO3_PWR_OFF_IN, WM8350_GPIO_ACTIVE_HIGH,
			   WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
			   WM8350_GPIO_DEBOUNCE_ON);

	wm8350_gpio_config(wm8350, 4, WM8350_GPIO_DIR_IN,
			   WM8350_GPIO4_MR_IN, WM8350_GPIO_ACTIVE_HIGH,
			   WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
			   WM8350_GPIO_DEBOUNCE_OFF);

	wm8350_gpio_config(wm8350, 7, WM8350_GPIO_DIR_IN,
			   WM8350_GPIO7_HIBERNATE_IN, WM8350_GPIO_ACTIVE_HIGH,
			   WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
			   WM8350_GPIO_DEBOUNCE_OFF);

	wm8350_gpio_config(wm8350, 6, WM8350_GPIO_DIR_OUT,
			   WM8350_GPIO6_SDOUT_OUT, WM8350_GPIO_ACTIVE_HIGH,
			   WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
			   WM8350_GPIO_DEBOUNCE_OFF);

	wm8350_gpio_config(wm8350, 8, WM8350_GPIO_DIR_OUT,
			   WM8350_GPIO8_VCC_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
			   WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
			   WM8350_GPIO_DEBOUNCE_OFF);

	wm8350_gpio_config(wm8350, 9, WM8350_GPIO_DIR_OUT,
			   WM8350_GPIO9_BATT_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
			   WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
			   WM8350_GPIO_DEBOUNCE_OFF);

	wm8350_register_regulator(wm8350, WM8350_DCDC_1, &sw1a_data);
	wm8350_register_regulator(wm8350, WM8350_DCDC_3, &viohi_data);
	wm8350_register_regulator(wm8350, WM8350_DCDC_4, &violo_data);
	wm8350_register_regulator(wm8350, WM8350_DCDC_6, &sw2a_data);
	wm8350_register_regulator(wm8350, WM8350_LDO_1, &ldo1_data);
	wm8350_register_regulator(wm8350, WM8350_LDO_2, &ldo2_data);
	wm8350_register_regulator(wm8350, WM8350_LDO_3, &vdig_data);
	wm8350_register_regulator(wm8350, WM8350_LDO_4, &ldo4_data);

	/* LEDs */
	wm8350_dcdc_set_slot(wm8350, WM8350_DCDC_5, 1, 1,
			     WM8350_DC5_ERRACT_SHUTDOWN_CONV);
	wm8350_isink_set_flash(wm8350, WM8350_ISINK_A,
			       WM8350_ISINK_FLASH_DISABLE,
			       WM8350_ISINK_FLASH_TRIG_BIT,
			       WM8350_ISINK_FLASH_DUR_32MS,
			       WM8350_ISINK_FLASH_ON_INSTANT,
			       WM8350_ISINK_FLASH_OFF_INSTANT,
			       WM8350_ISINK_FLASH_MODE_EN);
	wm8350_dcdc25_set_mode(wm8350, WM8350_DCDC_5,
			       WM8350_ISINK_MODE_BOOST,
			       WM8350_ISINK_ILIM_NORMAL,
			       WM8350_DC5_RMP_20V,
			       WM8350_DC5_FBSRC_ISINKA);
	wm8350_register_led(wm8350, 0, WM8350_DCDC_5, WM8350_ISINK_A,
			    &wm8350_led_data);

	wm8350->codec.platform_data = &imx32ads_wm8350_setup;

	regulator_has_full_constraints();

	return 0;
}

static struct wm8350_platform_data __initdata mx31_wm8350_pdata = {
	.init = mx31_wm8350_init,
};
#endif

static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = {
#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
	{
		I2C_BOARD_INFO("wm8350", 0x1a),
		.platform_data = &mx31_wm8350_pdata,
		/* irq number is run-time assigned */
	},
#endif
};

static void __init mxc_init_i2c(void)
{
#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
	mx31ads_i2c1_devices[0].irq =
			gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
#endif
	i2c_register_board_info(1, mx31ads_i2c1_devices,
				ARRAY_SIZE(mx31ads_i2c1_devices));

	mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1));
	mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1));

	imx31_add_imx_i2c1(NULL);
}

static unsigned int ssi_pins[] = {
	MX31_PIN_SFS5__SFS5,
	MX31_PIN_SCK5__SCK5,
	MX31_PIN_SRXD5__SRXD5,
	MX31_PIN_STXD5__STXD5,
};

static void __init mxc_init_audio(void)
{
	imx31_add_imx_ssi(0, NULL);
	mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi");
}

/*
 * Static mappings, starting from the CS4 start address up to the start address
 * of the CS8900.
 */
static struct map_desc mx31ads_io_desc[] __initdata = {
	{
		.virtual	= (unsigned long)MX31_CS4_BASE_ADDR_VIRT,
		.pfn		= __phys_to_pfn(MX31_CS4_BASE_ADDR),
		.length		= CS4_CS8900_MMIO_START,
		.type		= MT_DEVICE
	},
};

static void __init mx31ads_map_io(void)
{
	mx31_map_io();
	iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc));
}

static void __init mx31ads_init_irq(void)
{
	mx31_init_irq();
	mx31ads_init_expio();
}

static void __init mx31ads_init(void)
{
	imx31_soc_init();

	mxc_init_extuart();
	mxc_init_imx_uart();
	mxc_init_i2c();
	mxc_init_audio();
	mxc_init_ext_ethernet();
}

static void __init mx31ads_timer_init(void)
{
	mx31_clocks_init(26000000);
}

static struct sys_timer mx31ads_timer = {
	.init	= mx31ads_timer_init,
};

MACHINE_START(MX31ADS, "Freescale MX31ADS")
	/* Maintainer: Freescale Semiconductor, Inc. */
	.atag_offset = 0x100,
	.map_io = mx31ads_map_io,
	.init_early = imx31_init_early,
	.init_irq = mx31ads_init_irq,
	.handle_irq = imx31_handle_irq,
	.timer = &mx31ads_timer,
	.init_machine = mx31ads_init,
	.restart	= mxc_restart,
MACHINE_END
Commit	Line	Data
52c543f9 QJ	1	/*
	2	* Copyright (C) 2000 Deep Blue Solutions Ltd
	3	* Copyright (C) 2002 Shane Nay (shane@minirl.com)
	4	* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
52c543f9 QJ	15	*/
	16
	17	#include <linux/types.h>
	18	#include <linux/init.h>
	19	#include <linux/clk.h>
	20	#include <linux/serial_8250.h>
fe7316bf MB	21	#include <linux/gpio.h>
fe7316bf MB	22	#include <linux/i2c.h>
d7568f79	23	#include <linux/irq.h>
130d8bd7	24	#include <linux/irqdomain.h>
52c543f9	25
52c543f9 QJ	26	#include <asm/mach-types.h>
52c543f9 QJ	27	#include <asm/mach/arch.h>
d0f349fb	28	#include <asm/mach/time.h>
52c543f9 QJ	29	#include <asm/memory.h>
52c543f9 QJ	30	#include <asm/mach/map.h>
a09e64fb	31	#include <mach/common.h>
52c543f9	32
fe7316bf MB	33	#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
	34	#include <linux/mfd/wm8350/audio.h>
	35	#include <linux/mfd/wm8350/core.h>
	36	#include <linux/mfd/wm8350/pmic.h>
	37	#endif
	38
4a9b8b0b	39	#include "devices-imx31.h"
267dd34c	40	#include "iomux-mx3.h"
2eca047b	41
64a38516 JB	42	/* Base address of PBC controller */
	43	#define PBC_BASE_ADDRESS MX31_CS4_BASE_ADDR_VIRT
	44
ccfa7c26 UKK	45	/* PBC Board interrupt status register */
	46	#define PBC_INTSTATUS 0x000016
	47
	48	/* PBC Board interrupt current status register */
	49	#define PBC_INTCURR_STATUS 0x000018
	50
	51	/* PBC Interrupt mask register set address */
	52	#define PBC_INTMASK_SET 0x00001A
	53
	54	/* PBC Interrupt mask register clear address */
	55	#define PBC_INTMASK_CLEAR 0x00001C
	56
	57	/* External UART A */
	58	#define PBC_SC16C652_UARTA 0x010000
	59
	60	/* External UART B */
	61	#define PBC_SC16C652_UARTB 0x010010
	62
	63	#define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS)
	64	#define PBC_INTMASK_SET_REG (PBC_INTMASK_SET + PBC_BASE_ADDRESS)
	65	#define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
ccfa7c26	66
130d8bd7 SG	67	#define EXPIO_INT_XUART_INTA 10
130d8bd7 SG	68	#define EXPIO_INT_XUART_INTB 11
ccfa7c26 UKK	69
ccfa7c26 UKK	70	#define MXC_MAX_EXP_IO_LINES 16
52c543f9	71
64a38516	72	/* CS8900 */
130d8bd7	73	#define EXPIO_INT_ENET_INT 8
64a38516 JB	74	#define CS4_CS8900_MMIO_START 0x20000
64a38516 JB	75
130d8bd7 SG	76	static struct irq_domain *domain;
130d8bd7 SG	77
9f43e44b	78	/*
52c543f9 QJ	79	* The serial port definition structure.
	80	*/
	81	static struct plat_serial8250_port serial_platform_data[] = {
	82	{
	83	.membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA),
f568dd7f	84	.mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTA),
52c543f9 QJ	85	.uartclk = 14745600,
	86	.regshift = 0,
	87	.iotype = UPIO_MEM,
	88	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST \| UPF_AUTO_IRQ,
	89	}, {
	90	.membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB),
f568dd7f	91	.mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTB),
52c543f9 QJ	92	.uartclk = 14745600,
	93	.regshift = 0,
	94	.iotype = UPIO_MEM,
	95	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST \| UPF_AUTO_IRQ,
	96	},
	97	{},
	98	};
	99
	100	static struct platform_device serial_device = {
	101	.name = "serial8250",
	102	.id = 0,
	103	.dev = {
	104	.platform_data = serial_platform_data,
	105	},
	106	};
	107
130d8bd7	108	static struct resource mx31ads_cs8900_resources[] __initdata = {
64a38516	109	DEFINE_RES_MEM(MX31_CS4_BASE_ADDR + CS4_CS8900_MMIO_START, SZ_64K),
130d8bd7	110	DEFINE_RES_IRQ(-1),
64a38516 JB	111	};
	112
	113	static const struct platform_device_info mx31ads_cs8900_devinfo __initconst = {
	114	.name = "cs89x0",
	115	.id = 0,
	116	.res = mx31ads_cs8900_resources,
	117	.num_res = ARRAY_SIZE(mx31ads_cs8900_resources),
	118	};
	119
52c543f9 QJ	120	static int __init mxc_init_extuart(void)
52c543f9 QJ	121	{
130d8bd7 SG	122	serial_platform_data[0].irq = irq_find_mapping(domain,
	123	EXPIO_INT_XUART_INTA);
	124	serial_platform_data[1].irq = irq_find_mapping(domain,
	125	EXPIO_INT_XUART_INTB);
52c543f9 QJ	126	return platform_device_register(&serial_device);
52c543f9 QJ	127	}
52c543f9	128
64a38516 JB	129	static void __init mxc_init_ext_ethernet(void)
64a38516 JB	130	{
130d8bd7 SG	131	mx31ads_cs8900_resources[1].start =
	132	irq_find_mapping(domain, EXPIO_INT_ENET_INT);
	133	mx31ads_cs8900_resources[1].end =
	134	irq_find_mapping(domain, EXPIO_INT_ENET_INT);
64a38516 JB	135	platform_device_register_full(
	136	(struct platform_device_info *)&mx31ads_cs8900_devinfo);
	137	}
	138
16cf5c41	139	static const struct imxuart_platform_data uart_pdata __initconst = {
0741794c GC	140	.flags = IMXUART_HAVE_RTSCTS,
	141	};
	142
9070e7af	143	static unsigned int uart_pins[] = {
945c10b8 VL	144	MX31_PIN_CTS1__CTS1,
	145	MX31_PIN_RTS1__RTS1,
	146	MX31_PIN_TXD1__TXD1,
	147	MX31_PIN_RXD1__RXD1
	148	};
	149
0741794c GC	150	static inline void mxc_init_imx_uart(void)
0741794c GC	151	{
945c10b8	152	mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0");
16cf5c41	153	imx31_add_imx_uart0(&uart_pdata);
0741794c	154	}
0741794c	155
d7568f79 GC	156	static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc)
	157	{
	158	u32 imr_val;
	159	u32 int_valid;
	160	u32 expio_irq;
	161
	162	imr_val = __raw_readw(PBC_INTMASK_SET_REG);
	163	int_valid = __raw_readw(PBC_INTSTATUS_REG) & imr_val;
	164
130d8bd7	165	expio_irq = 0;
d7568f79 GC	166	for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
	167	if ((int_valid & 1) == 0)
	168	continue;
	169
130d8bd7	170	generic_handle_irq(irq_find_mapping(domain, expio_irq));
d7568f79 GC	171	}
	172	}
	173
	174	/*
	175	* Disable an expio pin's interrupt by setting the bit in the imr.
4e43d9fa	176	* @param d an expio virtual irq description
d7568f79	177	*/
e981a302	178	static void expio_mask_irq(struct irq_data *d)
d7568f79	179	{
130d8bd7	180	u32 expio = d->hwirq;
d7568f79 GC	181	/* mask the interrupt */
	182	__raw_writew(1 << expio, PBC_INTMASK_CLEAR_REG);
	183	__raw_readw(PBC_INTMASK_CLEAR_REG);
	184	}
	185
	186	/*
	187	* Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
4e43d9fa	188	* @param d an expio virtual irq description
d7568f79	189	*/
e981a302	190	static void expio_ack_irq(struct irq_data *d)
d7568f79	191	{
130d8bd7	192	u32 expio = d->hwirq;
d7568f79 GC	193	/* clear the interrupt status */
	194	__raw_writew(1 << expio, PBC_INTSTATUS_REG);
	195	}
	196
	197	/*
	198	* Enable a expio pin's interrupt by clearing the bit in the imr.
4e43d9fa	199	* @param d an expio virtual irq description
d7568f79	200	*/
e981a302	201	static void expio_unmask_irq(struct irq_data *d)
d7568f79	202	{
130d8bd7	203	u32 expio = d->hwirq;
d7568f79 GC	204	/* unmask the interrupt */
	205	__raw_writew(1 << expio, PBC_INTMASK_SET_REG);
	206	}
	207
	208	static struct irq_chip expio_irq_chip = {
bd02acdb	209	.name = "EXPIO(CPLD)",
e981a302 LB	210	.irq_ack = expio_ack_irq,
	211	.irq_mask = expio_mask_irq,
	212	.irq_unmask = expio_unmask_irq,
d7568f79 GC	213	};
	214
	215	static void __init mx31ads_init_expio(void)
	216	{
130d8bd7	217	int irq_base;
ed175343	218	int i, irq;
d7568f79 GC	219
	220	printk(KERN_INFO "MX31ADS EXPIO(CPLD) hardware\n");
	221
	222	/*
	223	* Configure INT line as GPIO input
	224	*/
4f163eb8	225	mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio");
d7568f79 GC	226
	227	/* disable the interrupt and clear the status */
	228	__raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG);
	229	__raw_writew(0xFFFF, PBC_INTSTATUS_REG);
130d8bd7 SG	230
	231	irq_base = irq_alloc_descs(-1, 0, MXC_MAX_EXP_IO_LINES, numa_node_id());
	232	WARN_ON(irq_base < 0);
	233
	234	domain = irq_domain_add_legacy(NULL, MXC_MAX_EXP_IO_LINES, irq_base, 0,
	235	&irq_domain_simple_ops, NULL);
	236	WARN_ON(!domain);
	237
	238	for (i = irq_base; i < irq_base + MXC_MAX_EXP_IO_LINES; i++) {
f38c02f3	239	irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq);
d7568f79 GC	240	set_irq_flags(i, IRQF_VALID);
d7568f79 GC	241	}
ed175343 SG	242	irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_4));
	243	irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
	244	irq_set_chained_handler(irq, mx31ads_expio_irq_handler);
d7568f79 GC	245	}
d7568f79 GC	246
fe7316bf MB	247	#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
	248	/* This section defines setup for the Wolfson Microelectronics
	249	* 1133-EV1 PMU/audio board. When other PMU boards are supported the
	250	* regulator definitions may be shared with them, but for now they can
	251	* only be used with this board so would generate warnings about
	252	* unused statics and some of the configuration is specific to this
	253	* module.
	254	*/
	255
	256	/* CPU */
	257	static struct regulator_consumer_supply sw1a_consumers[] = {
	258	{
	259	.supply = "cpu_vcc",
	260	}
	261	};
	262
	263	static struct regulator_init_data sw1a_data = {
	264	.constraints = {
	265	.name = "SW1A",
	266	.min_uV = 1275000,
	267	.max_uV = 1600000,
	268	.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE \|
	269	REGULATOR_CHANGE_MODE,
	270	.valid_modes_mask = REGULATOR_MODE_NORMAL \|
	271	REGULATOR_MODE_FAST,
	272	.state_mem = {
	273	.uV = 1400000,
	274	.mode = REGULATOR_MODE_NORMAL,
	275	.enabled = 1,
	276	},
	277	.initial_state = PM_SUSPEND_MEM,
	278	.always_on = 1,
	279	.boot_on = 1,
	280	},
	281	.num_consumer_supplies = ARRAY_SIZE(sw1a_consumers),
	282	.consumer_supplies = sw1a_consumers,
	283	};
	284
	285	/* System IO - High */
	286	static struct regulator_init_data viohi_data = {
	287	.constraints = {
	288	.name = "VIOHO",
	289	.min_uV = 2800000,
	290	.max_uV = 2800000,
	291	.state_mem = {
	292	.uV = 2800000,
	293	.mode = REGULATOR_MODE_NORMAL,
	294	.enabled = 1,
	295	},
	296	.initial_state = PM_SUSPEND_MEM,
	297	.always_on = 1,
	298	.boot_on = 1,
	299	},
	300	};
	301
	302	/* System IO - Low */
	303	static struct regulator_init_data violo_data = {
	304	.constraints = {
	305	.name = "VIOLO",
	306	.min_uV = 1800000,
	307	.max_uV = 1800000,
	308	.state_mem = {
	309	.uV = 1800000,
	310	.mode = REGULATOR_MODE_NORMAL,
311	.enabled = 1,
312	},
313	.initial_state = PM_SUSPEND_MEM,
314	.always_on = 1,
315	.boot_on = 1,
316	},
317	};
318
319	/* DDR RAM */
320	static struct regulator_init_data sw2a_data = {
321	.constraints = {
322	.name = "SW2A",
323	.min_uV = 1800000,
324	.max_uV = 1800000,
325	.valid_modes_mask = REGULATOR_MODE_NORMAL,
326	.state_mem = {
327	.uV = 1800000,
328	.mode = REGULATOR_MODE_NORMAL,
329	.enabled = 1,
330	},
331	.state_disk = {
332	.mode = REGULATOR_MODE_NORMAL,
333	.enabled = 0,
334	},
335	.always_on = 1,
336	.boot_on = 1,
337	.initial_state = PM_SUSPEND_MEM,
338	},
339	};
340
341	static struct regulator_init_data ldo1_data = {
342	.constraints = {
343	.name = "VCAM/VMMC1/VMMC2",
344	.min_uV = 2800000,
345	.max_uV = 2800000,
346	.valid_modes_mask = REGULATOR_MODE_NORMAL,
becc670a	347	.valid_ops_mask = REGULATOR_CHANGE_STATUS,
fe7316bf MB	348	.apply_uV = 1,
	349	},
	350	};
	351
	352	static struct regulator_consumer_supply ldo2_consumers[] = {
edc34a90 MB	353	{ .supply = "AVDD", .dev_name = "1-001a" },
edc34a90 MB	354	{ .supply = "HPVDD", .dev_name = "1-001a" },
fe7316bf MB	355	};
	356
	357	/* CODEC and SIM */
	358	static struct regulator_init_data ldo2_data = {
	359	.constraints = {
	360	.name = "VESIM/VSIM/AVDD",
	361	.min_uV = 3300000,
	362	.max_uV = 3300000,
	363	.valid_modes_mask = REGULATOR_MODE_NORMAL,
becc670a	364	.valid_ops_mask = REGULATOR_CHANGE_STATUS,
fe7316bf MB	365	.apply_uV = 1,
	366	},
	367	.num_consumer_supplies = ARRAY_SIZE(ldo2_consumers),
	368	.consumer_supplies = ldo2_consumers,
	369	};
	370
	371	/* General */
	372	static struct regulator_init_data vdig_data = {
	373	.constraints = {
	374	.name = "VDIG",
	375	.min_uV = 1500000,
	376	.max_uV = 1500000,
	377	.valid_modes_mask = REGULATOR_MODE_NORMAL,
	378	.apply_uV = 1,
	379	.always_on = 1,
	380	.boot_on = 1,
	381	},
	382	};
	383
	384	/* Tranceivers */
	385	static struct regulator_init_data ldo4_data = {
	386	.constraints = {
	387	.name = "VRF1/CVDD_2.775",
	388	.min_uV = 2500000,
	389	.max_uV = 2500000,
	390	.valid_modes_mask = REGULATOR_MODE_NORMAL,
	391	.apply_uV = 1,
	392	.always_on = 1,
	393	.boot_on = 1,
	394	},
	395	};
	396
	397	static struct wm8350_led_platform_data wm8350_led_data = {
	398	.name = "wm8350:white",
	399	.default_trigger = "heartbeat",
	400	.max_uA = 27899,
	401	};
	402
	403	static struct wm8350_audio_platform_data imx32ads_wm8350_setup = {
	404	.vmid_discharge_msecs = 1000,
	405	.drain_msecs = 30,
	406	.cap_discharge_msecs = 700,
	407	.vmid_charge_msecs = 700,
	408	.vmid_s_curve = WM8350_S_CURVE_SLOW,
	409	.dis_out4 = WM8350_DISCHARGE_SLOW,
	410	.dis_out3 = WM8350_DISCHARGE_SLOW,
	411	.dis_out2 = WM8350_DISCHARGE_SLOW,
	412	.dis_out1 = WM8350_DISCHARGE_SLOW,
	413	.vroi_out4 = WM8350_TIE_OFF_500R,
	414	.vroi_out3 = WM8350_TIE_OFF_500R,
	415	.vroi_out2 = WM8350_TIE_OFF_500R,
	416	.vroi_out1 = WM8350_TIE_OFF_500R,
	417	.vroi_enable = 0,
	418	.codec_current_on = WM8350_CODEC_ISEL_1_0,
	419	.codec_current_standby = WM8350_CODEC_ISEL_0_5,
	420	.codec_current_charge = WM8350_CODEC_ISEL_1_5,
	421	};
	422
	423	static int mx31_wm8350_init(struct wm8350 *wm8350)
	424	{
fe7316bf MB	425	wm8350_gpio_config(wm8350, 0, WM8350_GPIO_DIR_IN,
	426	WM8350_GPIO0_PWR_ON_IN, WM8350_GPIO_ACTIVE_LOW,
	427	WM8350_GPIO_PULL_UP, WM8350_GPIO_INVERT_OFF,
	428	WM8350_GPIO_DEBOUNCE_ON);
	429
	430	wm8350_gpio_config(wm8350, 3, WM8350_GPIO_DIR_IN,
	431	WM8350_GPIO3_PWR_OFF_IN, WM8350_GPIO_ACTIVE_HIGH,
	432	WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
	433	WM8350_GPIO_DEBOUNCE_ON);
	434
	435	wm8350_gpio_config(wm8350, 4, WM8350_GPIO_DIR_IN,
	436	WM8350_GPIO4_MR_IN, WM8350_GPIO_ACTIVE_HIGH,
	437	WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
	438	WM8350_GPIO_DEBOUNCE_OFF);
	439
	440	wm8350_gpio_config(wm8350, 7, WM8350_GPIO_DIR_IN,
	441	WM8350_GPIO7_HIBERNATE_IN, WM8350_GPIO_ACTIVE_HIGH,
	442	WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
	443	WM8350_GPIO_DEBOUNCE_OFF);
	444
	445	wm8350_gpio_config(wm8350, 6, WM8350_GPIO_DIR_OUT,
	446	WM8350_GPIO6_SDOUT_OUT, WM8350_GPIO_ACTIVE_HIGH,
	447	WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
	448	WM8350_GPIO_DEBOUNCE_OFF);
	449
	450	wm8350_gpio_config(wm8350, 8, WM8350_GPIO_DIR_OUT,
	451	WM8350_GPIO8_VCC_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
	452	WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
	453	WM8350_GPIO_DEBOUNCE_OFF);
	454
	455	wm8350_gpio_config(wm8350, 9, WM8350_GPIO_DIR_OUT,
	456	WM8350_GPIO9_BATT_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
	457	WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
	458	WM8350_GPIO_DEBOUNCE_OFF);
	459
fe7316bf MB	460	wm8350_register_regulator(wm8350, WM8350_DCDC_1, &sw1a_data);
	461	wm8350_register_regulator(wm8350, WM8350_DCDC_3, &viohi_data);
	462	wm8350_register_regulator(wm8350, WM8350_DCDC_4, &violo_data);
	463	wm8350_register_regulator(wm8350, WM8350_DCDC_6, &sw2a_data);
	464	wm8350_register_regulator(wm8350, WM8350_LDO_1, &ldo1_data);
	465	wm8350_register_regulator(wm8350, WM8350_LDO_2, &ldo2_data);
	466	wm8350_register_regulator(wm8350, WM8350_LDO_3, &vdig_data);
	467	wm8350_register_regulator(wm8350, WM8350_LDO_4, &ldo4_data);
	468
	469	/* LEDs */
	470	wm8350_dcdc_set_slot(wm8350, WM8350_DCDC_5, 1, 1,
	471	WM8350_DC5_ERRACT_SHUTDOWN_CONV);
	472	wm8350_isink_set_flash(wm8350, WM8350_ISINK_A,
	473	WM8350_ISINK_FLASH_DISABLE,
	474	WM8350_ISINK_FLASH_TRIG_BIT,
	475	WM8350_ISINK_FLASH_DUR_32MS,
	476	WM8350_ISINK_FLASH_ON_INSTANT,
	477	WM8350_ISINK_FLASH_OFF_INSTANT,
	478	WM8350_ISINK_FLASH_MODE_EN);
	479	wm8350_dcdc25_set_mode(wm8350, WM8350_DCDC_5,
	480	WM8350_ISINK_MODE_BOOST,
	481	WM8350_ISINK_ILIM_NORMAL,
	482	WM8350_DC5_RMP_20V,
	483	WM8350_DC5_FBSRC_ISINKA);
	484	wm8350_register_led(wm8350, 0, WM8350_DCDC_5, WM8350_ISINK_A,
	485	&wm8350_led_data);
	486
	487	wm8350->codec.platform_data = &imx32ads_wm8350_setup;
	488
0ac402fd MB	489	regulator_has_full_constraints();
0ac402fd MB	490
fe7316bf MB	491	return 0;
	492	}
	493
	494	static struct wm8350_platform_data __initdata mx31_wm8350_pdata = {
	495	.init = mx31_wm8350_init,
	496	};
	497	#endif
	498
fe7316bf MB	499	static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = {
	500	#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
	501	{
	502	I2C_BOARD_INFO("wm8350", 0x1a),
	503	.platform_data = &mx31_wm8350_pdata,
ed175343	504	/* irq number is run-time assigned */
fe7316bf MB	505	},
	506	#endif
	507	};
	508
ea7aed6b	509	static void __init mxc_init_i2c(void)
fe7316bf	510	{
ed175343 SG	511	#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
	512	mx31ads_i2c1_devices[0].irq =
	513	gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
	514	#endif
fe7316bf MB	515	i2c_register_board_info(1, mx31ads_i2c1_devices,
	516	ARRAY_SIZE(mx31ads_i2c1_devices));
	517
	518	mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1));
	519	mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1));
	520
4a9b8b0b	521	imx31_add_imx_i2c1(NULL);
fe7316bf	522	}
fe7316bf	523
cd6eb980 MB	524	static unsigned int ssi_pins[] = {
	525	MX31_PIN_SFS5__SFS5,
	526	MX31_PIN_SCK5__SCK5,
	527	MX31_PIN_SRXD5__SRXD5,
	528	MX31_PIN_STXD5__STXD5,
	529	};
	530
ea7aed6b	531	static void __init mxc_init_audio(void)
cd6eb980	532	{
4697bb92	533	imx31_add_imx_ssi(0, NULL);
cd6eb980 MB	534	mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi");
	535	}
	536
64a38516 JB	537	/*
	538	* Static mappings, starting from the CS4 start address up to the start address
	539	* of the CS8900.
	540	*/
52c543f9 QJ	541	static struct map_desc mx31ads_io_desc[] __initdata = {
52c543f9 QJ	542	{
f25d696a	543	.virtual = (unsigned long)MX31_CS4_BASE_ADDR_VIRT,
f568dd7f	544	.pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
64a38516	545	.length = CS4_CS8900_MMIO_START,
52c543f9 QJ	546	.type = MT_DEVICE
	547	},
	548	};
	549
8b785b9d	550	static void __init mx31ads_map_io(void)
52c543f9	551	{
cd4a05f9	552	mx31_map_io();
52c543f9 QJ	553	iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc));
	554	}
	555
8b785b9d	556	static void __init mx31ads_init_irq(void)
d7568f79	557	{
c5aa0ad0	558	mx31_init_irq();
d7568f79 GC	559	mx31ads_init_expio();
	560	}
	561
e134fb2b	562	static void __init mx31ads_init(void)
52c543f9	563	{
b78d8e59 SG	564	imx31_soc_init();
b78d8e59 SG	565
52c543f9	566	mxc_init_extuart();
0741794c	567	mxc_init_imx_uart();
fe7316bf	568	mxc_init_i2c();
cd6eb980	569	mxc_init_audio();
64a38516	570	mxc_init_ext_ethernet();
52c543f9 QJ	571	}
52c543f9 QJ	572
d0f349fb JB	573	static void __init mx31ads_timer_init(void)
d0f349fb JB	574	{
30c730f8	575	mx31_clocks_init(26000000);
d0f349fb JB	576	}
d0f349fb JB	577
8b785b9d	578	static struct sys_timer mx31ads_timer = {
d0f349fb JB	579	.init = mx31ads_timer_init,
	580	};
	581
52c543f9 QJ	582	MACHINE_START(MX31ADS, "Freescale MX31ADS")
52c543f9 QJ	583	/* Maintainer: Freescale Semiconductor, Inc. */
dc8f1907	584	.atag_offset = 0x100,
97976e22 UKK	585	.map_io = mx31ads_map_io,
	586	.init_early = imx31_init_early,
	587	.init_irq = mx31ads_init_irq,
ffa2ea3f	588	.handle_irq = imx31_handle_irq,
97976e22	589	.timer = &mx31ads_timer,
e134fb2b	590	.init_machine = mx31ads_init,
65ea7884	591	.restart = mxc_restart,
52c543f9	592	MACHINE_END