projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'pm+acpi-3.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael...
[deliverable/linux.git] / arch / arm / mach-imx / mach-pcm037.c
CommitLineData
ce8ffef0
SH		 1/*
2 * Copyright (C) 2008 Sascha Hauer, Pengutronix
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
ce8ffef0
SH		 13 */
14
15#include <linux/types.h>
16#include <linux/init.h>
32c1ad9a 17#include <linux/dma-mapping.h>
ce8ffef0
SH		 18#include <linux/platform_device.h>
19#include <linux/mtd/physmap.h>
3dad21a9 20#include <linux/mtd/plat-ram.h>
ce8ffef0 21#include <linux/memory.h>
ba54b958 22#include <linux/gpio.h>
4353318e 23#include <linux/smsc911x.h>
ba54b958 24#include <linux/interrupt.h>
79206750 25#include <linux/i2c.h>
25f73ed5 26#include <linux/platform_data/at24.h>
dddd4a49
SH		 27#include <linux/delay.h>
28#include <linux/spi/spi.h>
29#include <linux/irq.h>
91bf9a25 30#include <linux/can/platform/sja1000.h>
ee14373c
SH		 31#include <linux/usb/otg.h>
32#include <linux/usb/ulpi.h>
5a0e3ad6 33#include <linux/gfp.h>
dca7c0b4 34#include <linux/memblock.h>
7dc3a6a5
SH		 35#include <linux/regulator/machine.h>
36#include <linux/regulator/fixed.h>
ce8ffef0 37
32c1ad9a
GL		 38#include <media/soc_camera.h>
39
ce8ffef0
SH		 40#include <asm/mach-types.h>
41#include <asm/mach/arch.h>
42#include <asm/mach/time.h>
43#include <asm/mach/map.h>
716a3dc2 44#include <asm/memblock.h>
ce8ffef0 45
e3372474 46#include "common.h"
a2ceeef5 47#include "devices-imx31.h"
50f2de61 48#include "hardware.h"
267dd34c 49#include "iomux-mx3.h"
574ec547 50#include "pcm037.h"
39ef6340 51#include "ulpi.h"
574ec547
GL		 52
53static enum pcm037_board_variant pcm037_instance = PCM037_PCM970;
54
55static int __init pcm037_variant_setup(char *str)
56{
57 if (!strcmp("eet", str))
58 pcm037_instance = PCM037_EET;
59 else if (strcmp("pcm970", str))
60 pr_warning("Unknown pcm037 baseboard variant %s\n", str);
61
62 return 1;
63}
64
65/* Supported values: "pcm970" (default) and "eet" */
66__setup("pcm037_variant=", pcm037_variant_setup);
67
68enum pcm037_board_variant pcm037_variant(void)
69{
70 return pcm037_instance;
71}
72
73/* UART1 with RTS/CTS handshake signals */
74static unsigned int pcm037_uart1_handshake_pins[] = {
75 MX31_PIN_CTS1__CTS1,
76 MX31_PIN_RTS1__RTS1,
77 MX31_PIN_TXD1__TXD1,
78 MX31_PIN_RXD1__RXD1,
79};
80
81/* UART1 without RTS/CTS handshake signals */
82static unsigned int pcm037_uart1_pins[] = {
83 MX31_PIN_TXD1__TXD1,
84 MX31_PIN_RXD1__RXD1,
85};
5cf09421 86
01ac7d58
SH		 87static unsigned int pcm037_pins[] = {
88 /* I2C */
89 MX31_PIN_CSPI2_MOSI__SCL,
90 MX31_PIN_CSPI2_MISO__SDA,
32c1ad9a
GL		 91 MX31_PIN_CSPI2_SS2__I2C3_SDA,
92 MX31_PIN_CSPI2_SCLK__I2C3_SCL,
01ac7d58
SH		 93 /* SDHC1 */
94 MX31_PIN_SD1_DATA3__SD1_DATA3,
95 MX31_PIN_SD1_DATA2__SD1_DATA2,
96 MX31_PIN_SD1_DATA1__SD1_DATA1,
97 MX31_PIN_SD1_DATA0__SD1_DATA0,
98 MX31_PIN_SD1_CLK__SD1_CLK,
99 MX31_PIN_SD1_CMD__SD1_CMD,
100 IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO), /* card detect */
101 IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO), /* write protect */
102 /* SPI1 */
103 MX31_PIN_CSPI1_MOSI__MOSI,
104 MX31_PIN_CSPI1_MISO__MISO,
105 MX31_PIN_CSPI1_SCLK__SCLK,
106 MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
107 MX31_PIN_CSPI1_SS0__SS0,
108 MX31_PIN_CSPI1_SS1__SS1,
109 MX31_PIN_CSPI1_SS2__SS2,
01ac7d58
SH		 110 /* UART2 */
111 MX31_PIN_TXD2__TXD2,
112 MX31_PIN_RXD2__RXD2,
113 MX31_PIN_CTS2__CTS2,
114 MX31_PIN_RTS2__RTS2,
115 /* UART3 */
116 MX31_PIN_CSPI3_MOSI__RXD3,
117 MX31_PIN_CSPI3_MISO__TXD3,
118 MX31_PIN_CSPI3_SCLK__RTS3,
119 MX31_PIN_CSPI3_SPI_RDY__CTS3,
120 /* LAN9217 irq pin */
121 IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO),
122 /* Onewire */
123 MX31_PIN_BATT_LINE__OWIRE,
124 /* Framebuffer */
125 MX31_PIN_LD0__LD0,
126 MX31_PIN_LD1__LD1,
127 MX31_PIN_LD2__LD2,
128 MX31_PIN_LD3__LD3,
129 MX31_PIN_LD4__LD4,
130 MX31_PIN_LD5__LD5,
131 MX31_PIN_LD6__LD6,
132 MX31_PIN_LD7__LD7,
133 MX31_PIN_LD8__LD8,
134 MX31_PIN_LD9__LD9,
135 MX31_PIN_LD10__LD10,
136 MX31_PIN_LD11__LD11,
137 MX31_PIN_LD12__LD12,
138 MX31_PIN_LD13__LD13,
139 MX31_PIN_LD14__LD14,
140 MX31_PIN_LD15__LD15,
141 MX31_PIN_LD16__LD16,
142 MX31_PIN_LD17__LD17,
143 MX31_PIN_VSYNC3__VSYNC3,
144 MX31_PIN_HSYNC__HSYNC,
145 MX31_PIN_FPSHIFT__FPSHIFT,
146 MX31_PIN_DRDY0__DRDY0,
147 MX31_PIN_D3_REV__D3_REV,
148 MX31_PIN_CONTRAST__CONTRAST,
149 MX31_PIN_D3_SPL__D3_SPL,
150 MX31_PIN_D3_CLS__D3_CLS,
151 MX31_PIN_LCS0__GPI03_23,
32c1ad9a
GL		 152 /* CSI */
153 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_GPIO),
154 MX31_PIN_CSI_D6__CSI_D6,
155 MX31_PIN_CSI_D7__CSI_D7,
156 MX31_PIN_CSI_D8__CSI_D8,
157 MX31_PIN_CSI_D9__CSI_D9,
158 MX31_PIN_CSI_D10__CSI_D10,
159 MX31_PIN_CSI_D11__CSI_D11,
160 MX31_PIN_CSI_D12__CSI_D12,
161 MX31_PIN_CSI_D13__CSI_D13,
162 MX31_PIN_CSI_D14__CSI_D14,
163 MX31_PIN_CSI_D15__CSI_D15,
164 MX31_PIN_CSI_HSYNC__CSI_HSYNC,
165 MX31_PIN_CSI_MCLK__CSI_MCLK,
166 MX31_PIN_CSI_PIXCLK__CSI_PIXCLK,
167 MX31_PIN_CSI_VSYNC__CSI_VSYNC,
e0fd4db3
LF		 168 /* GPIO */
169 IOMUX_MODE(MX31_PIN_ATA_DMACK, IOMUX_CONFIG_GPIO),
ee14373c 170 /* OTG */
eb05bbeb
GL		 171 MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
172 MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
173 MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
174 MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
175 MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
176 MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
177 MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
178 MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
179 MX31_PIN_USBOTG_CLK__USBOTG_CLK,
180 MX31_PIN_USBOTG_DIR__USBOTG_DIR,
181 MX31_PIN_USBOTG_NXT__USBOTG_NXT,
182 MX31_PIN_USBOTG_STP__USBOTG_STP,
ee14373c
SH		 183 /* USB host 2 */
184 IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
185 IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
186 IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
187 IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
188 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
189 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
190 IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC),
191 IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC),
192 IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC),
193 IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC),
194 IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC),
195 IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC),
eb05bbeb
GL		 196};
197
ee14373c
SH		 198static struct physmap_flash_data pcm037_flash_data = {
199 .width = 2,
200};
eb05bbeb 201
ee14373c
SH		 202static struct resource pcm037_flash_resource = {
203 .start = 0xa0000000,
204 .end = 0xa1ffffff,
205 .flags = IORESOURCE_MEM,
eb05bbeb
GL		 206};
207
ce8ffef0
SH		 208static struct platform_device pcm037_flash = {
209 .name = "physmap-flash",
210 .id = 0,
211 .dev = {
212 .platform_data = &pcm037_flash_data,
213 },
214 .resource = &pcm037_flash_resource,
215 .num_resources = 1,
216};
217
16cf5c41 218static const struct imxuart_platform_data uart_pdata __initconst = {
a9b06233 219 .flags = IMXUART_HAVE_RTSCTS,
ce8ffef0
SH		 220};
221
4353318e 222static struct resource smsc911x_resources[] = {
3f4f54b4 223 {
f568dd7f
UKK		 224 .start = MX31_CS1_BASE_ADDR + 0x300,
225 .end = MX31_CS1_BASE_ADDR + 0x300 + SZ_64K - 1,
ba54b958 226 .flags = IORESOURCE_MEM,
3f4f54b4 227 }, {
ed175343 228 /* irq number is run-time assigned */
4353318e 229 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
ba54b958
GL		 230 },
231};
232
4353318e
SG		 233static struct smsc911x_platform_config smsc911x_info = {
234 .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY |
235 SMSC911X_SAVE_MAC_ADDRESS,
236 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
237 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
238 .phy_interface = PHY_INTERFACE_MODE_MII,
ba54b958
GL		 239};
240
241static struct platform_device pcm037_eth = {
4353318e 242 .name = "smsc911x",
ba54b958 243 .id = -1,
4353318e
SG		 244 .num_resources = ARRAY_SIZE(smsc911x_resources),
245 .resource = smsc911x_resources,
ba54b958 246 .dev = {
4353318e 247 .platform_data = &smsc911x_info,
ba54b958
GL		 248 },
249};
250
3dad21a9
SH		 251static struct platdata_mtd_ram pcm038_sram_data = {
252 .bankwidth = 2,
253};
254
255static struct resource pcm038_sram_resource = {
f568dd7f
UKK		 256 .start = MX31_CS4_BASE_ADDR,
257 .end = MX31_CS4_BASE_ADDR + 512 * 1024 - 1,
3dad21a9
SH		 258 .flags = IORESOURCE_MEM,
259};
260
261static struct platform_device pcm037_sram_device = {
262 .name = "mtd-ram",
263 .id = 0,
264 .dev = {
265 .platform_data = &pcm038_sram_data,
266 },
267 .num_resources = 1,
268 .resource = &pcm038_sram_resource,
269};
270
a2ceeef5
UKK		 271static const struct mxc_nand_platform_data
272pcm037_nand_board_info __initconst = {
3287abbd
SH		 273 .width = 1,
274 .hw_ecc = 1,
275};
276
4a9b8b0b 277static const struct imxi2c_platform_data pcm037_i2c1_data __initconst = {
79206750 278 .bitrate = 100000,
79206750
SH		 279};
280
4a9b8b0b 281static const struct imxi2c_platform_data pcm037_i2c2_data __initconst = {
32c1ad9a
GL		 282 .bitrate = 20000,
283};
284
79206750
SH		 285static struct at24_platform_data board_eeprom = {
286 .byte_len = 4096,
287 .page_size = 32,
288 .flags = AT24_FLAG_ADDR16,
289};
290
32c1ad9a
GL		 291static int pcm037_camera_power(struct device *dev, int on)
292{
293 /* disable or enable the camera in X7 or X8 PCM970 connector */
294 gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), !on);
295 return 0;
296}
297
9d00278d 298static struct i2c_board_info pcm037_i2c_camera[] = {
32c1ad9a
GL		 299 {
300 I2C_BOARD_INFO("mt9t031", 0x5d),
9d00278d
GL		 301 }, {
302 I2C_BOARD_INFO("mt9v022", 0x48),
32c1ad9a
GL		 303 },
304};
305
9d00278d
GL		 306static struct soc_camera_link iclink_mt9v022 = {
307 .bus_id = 0, /* Must match with the camera ID */
308 .board_info = &pcm037_i2c_camera[1],
309 .i2c_adapter_id = 2,
9d00278d
GL		 310};
311
312static struct soc_camera_link iclink_mt9t031 = {
32c1ad9a
GL		 313 .bus_id = 0, /* Must match with the camera ID */
314 .power = pcm037_camera_power,
9d00278d 315 .board_info = &pcm037_i2c_camera[0],
32c1ad9a 316 .i2c_adapter_id = 2,
32c1ad9a
GL		 317};
318
79206750 319static struct i2c_board_info pcm037_i2c_devices[] = {
32c1ad9a 320 {
79206750
SH		 321 I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
322 .platform_data = &board_eeprom,
323 }, {
cf87a6e2 324 I2C_BOARD_INFO("pcf8563", 0x51),
79206750
SH		 325 }
326};
32c1ad9a 327
9d00278d 328static struct platform_device pcm037_mt9t031 = {
32c1ad9a
GL		 329 .name = "soc-camera-pdrv",
330 .id = 0,
331 .dev = {
9d00278d
GL		 332 .platform_data = &iclink_mt9t031,
333 },
334};
335
336static struct platform_device pcm037_mt9v022 = {
337 .name = "soc-camera-pdrv",
338 .id = 1,
339 .dev = {
340 .platform_data = &iclink_mt9v022,
32c1ad9a
GL		 341 },
342};
79206750 343
dddd4a49
SH		 344/* Not connected by default */
345#ifdef PCM970_SDHC_RW_SWITCH
346static int pcm970_sdhc1_get_ro(struct device *dev)
f2cb641f 347{
dddd4a49
SH		 348 return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_SFS6));
349}
350#endif
351
4f163eb8
SH		 352#define SDHC1_GPIO_WP IOMUX_TO_GPIO(MX31_PIN_SFS6)
353#define SDHC1_GPIO_DET IOMUX_TO_GPIO(MX31_PIN_SCK6)
354
dddd4a49
SH		 355static int pcm970_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
356 void *data)
357{
358 int ret;
dddd4a49 359
4f163eb8
SH		 360 ret = gpio_request(SDHC1_GPIO_DET, "sdhc-detect");
361 if (ret)
362 return ret;
363
364 gpio_direction_input(SDHC1_GPIO_DET);
dddd4a49 365
4f163eb8
SH		 366#ifdef PCM970_SDHC_RW_SWITCH
367 ret = gpio_request(SDHC1_GPIO_WP, "sdhc-wp");
368 if (ret)
369 goto err_gpio_free;
370 gpio_direction_input(SDHC1_GPIO_WP);
371#endif
dddd4a49 372
ed175343 373 ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SCK6)), detect_irq,
4c1dd3e5 374 IRQF_TRIGGER_FALLING, "sdhc-detect", data);
4f163eb8
SH		 375 if (ret)
376 goto err_gpio_free_2;
377
378 return 0;
379
380err_gpio_free_2:
381#ifdef PCM970_SDHC_RW_SWITCH
382 gpio_free(SDHC1_GPIO_WP);
383err_gpio_free:
384#endif
385 gpio_free(SDHC1_GPIO_DET);
386
dddd4a49 387 return ret;
f2cb641f
SH		 388}
389
390static void pcm970_sdhc1_exit(struct device *dev, void *data)
391{
ed175343 392 free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SCK6)), data);
4f163eb8
SH		 393 gpio_free(SDHC1_GPIO_DET);
394 gpio_free(SDHC1_GPIO_WP);
f2cb641f
SH		 395}
396
6a697e3d 397static const struct imxmmc_platform_data sdhc_pdata __initconst = {
dddd4a49
SH		 398#ifdef PCM970_SDHC_RW_SWITCH
399 .get_ro = pcm970_sdhc1_get_ro,
400#endif
f2cb641f
SH		 401 .init = pcm970_sdhc1_init,
402 .exit = pcm970_sdhc1_exit,
403};
404
afa77ef3 405struct mx3_camera_pdata camera_pdata __initdata = {
32c1ad9a
GL		 406 .flags = MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10,
407 .mclk_10khz = 2000,
408};
409
dca7c0b4
UKK		 410static phys_addr_t mx3_camera_base __initdata;
411#define MX3_CAMERA_BUF_SIZE SZ_4M
412
afa77ef3 413static int __init pcm037_init_camera(void)
32c1ad9a 414{
afa77ef3
UKK		 415 int dma, ret = -ENOMEM;
416 struct platform_device *pdev = imx31_alloc_mx3_camera(&camera_pdata);
32c1ad9a 417
afa77ef3
UKK		 418 if (IS_ERR(pdev))
419 return PTR_ERR(pdev);
420
421 dma = dma_declare_coherent_memory(&pdev->dev,
dca7c0b4
UKK		 422 mx3_camera_base, mx3_camera_base,
423 MX3_CAMERA_BUF_SIZE,
32c1ad9a 424 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
afa77ef3
UKK		 425 if (!(dma & DMA_MEMORY_MAP))
426 goto err;
427
428 ret = platform_device_add(pdev);
429 if (ret)
430err:
431 platform_device_put(pdev);
32c1ad9a 432
afa77ef3 433 return ret;
32c1ad9a
GL		 434}
435
ce8ffef0
SH		 436static struct platform_device *devices[] __initdata = {
437 &pcm037_flash,
3dad21a9 438 &pcm037_sram_device,
9d00278d
GL		 439 &pcm037_mt9t031,
440 &pcm037_mt9v022,
ce8ffef0
SH		 441};
442
a8df0ee8
GL		 443static const struct fb_videomode fb_modedb[] = {
444 {
445 /* 240x320 @ 60 Hz Sharp */
446 .name = "Sharp-LQ035Q7DH06-QVGA",
447 .refresh = 60,
448 .xres = 240,
449 .yres = 320,
450 .pixclock = 185925,
451 .left_margin = 9,
452 .right_margin = 16,
453 .upper_margin = 7,
454 .lower_margin = 9,
455 .hsync_len = 1,
456 .vsync_len = 1,
457 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE |
458 FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN,
459 .vmode = FB_VMODE_NONINTERLACED,
460 .flag = 0,
461 }, {
462 /* 240x320 @ 60 Hz */
463 .name = "TX090",
464 .refresh = 60,
465 .xres = 240,
466 .yres = 320,
467 .pixclock = 38255,
468 .left_margin = 144,
469 .right_margin = 0,
470 .upper_margin = 7,
471 .lower_margin = 40,
472 .hsync_len = 96,
473 .vsync_len = 1,
474 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
475 .vmode = FB_VMODE_NONINTERLACED,
476 .flag = 0,
574ec547
GL		 477 }, {
478 /* 240x320 @ 60 Hz */
479 .name = "CMEL-OLED",
480 .refresh = 60,
481 .xres = 240,
482 .yres = 320,
483 .pixclock = 185925,
484 .left_margin = 9,
485 .right_margin = 16,
486 .upper_margin = 7,
487 .lower_margin = 9,
488 .hsync_len = 1,
489 .vsync_len = 1,
490 .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
491 .vmode = FB_VMODE_NONINTERLACED,
492 .flag = 0,
a8df0ee8
GL		 493 },
494};
495
496static struct mx3fb_platform_data mx3fb_pdata = {
a8df0ee8
GL		 497 .name = "Sharp-LQ035Q7DH06-QVGA",
498 .mode = fb_modedb,
499 .num_modes = ARRAY_SIZE(fb_modedb),
500};
501
91bf9a25
SH		 502static struct resource pcm970_sja1000_resources[] = {
503 {
f568dd7f
UKK		 504 .start = MX31_CS5_BASE_ADDR,
505 .end = MX31_CS5_BASE_ADDR + 0x100 - 1,
91bf9a25
SH		 506 .flags = IORESOURCE_MEM,
507 }, {
ed175343 508 /* irq number is run-time assigned */
91bf9a25
SH		 509 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
510 },
511};
512
513struct sja1000_platform_data pcm970_sja1000_platform_data = {
56e6943b
WG		 514 .osc_freq = 16000000,
515 .ocr = OCR_TX1_PULLDOWN | OCR_TX0_PUSHPULL,
516 .cdr = CDR_CBP,
91bf9a25
SH		 517};
518
519static struct platform_device pcm970_sja1000 = {
520 .name = "sja1000_platform",
521 .dev = {
522 .platform_data = &pcm970_sja1000_platform_data,
523 },
524 .resource = pcm970_sja1000_resources,
525 .num_resources = ARRAY_SIZE(pcm970_sja1000_resources),
526};
527
4bd597b6
SH		 528static int pcm037_otg_init(struct platform_device *pdev)
529{
530 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
531}
532
2d58de28 533static struct mxc_usbh_platform_data otg_pdata __initdata = {
4bd597b6 534 .init = pcm037_otg_init,
ee14373c 535 .portsc = MXC_EHCI_MODE_ULPI,
ee14373c
SH		 536};
537
4bd597b6
SH		 538static int pcm037_usbh2_init(struct platform_device *pdev)
539{
540 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
541}
542
2d58de28 543static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
4bd597b6 544 .init = pcm037_usbh2_init,
ee14373c 545 .portsc = MXC_EHCI_MODE_ULPI,
ee14373c
SH		 546};
547
9e1dde33 548static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
ee14373c
SH		 549 .operating_mode = FSL_USB2_DR_DEVICE,
550 .phy_mode = FSL_USB2_PHY_ULPI,
551};
552
33a264dd 553static bool otg_mode_host __initdata;
ee14373c
SH		 554
555static int __init pcm037_otg_mode(char *options)
556{
557 if (!strcmp(options, "host"))
33a264dd 558 otg_mode_host = true;
ee14373c 559 else if (!strcmp(options, "device"))
33a264dd 560 otg_mode_host = false;
ee14373c
SH		 561 else
562 pr_info("otg_mode neither \"host\" nor \"device\". "
563 "Defaulting to device\n");
33a264dd 564 return 1;
ee14373c
SH		 565}
566__setup("otg_mode=", pcm037_otg_mode);
567
7dc3a6a5
SH		 568static struct regulator_consumer_supply dummy_supplies[] = {
569 REGULATOR_SUPPLY("vdd33a", "smsc911x"),
570 REGULATOR_SUPPLY("vddvario", "smsc911x"),
571};
572
ce8ffef0
SH		 573/*
574 * Board specific initialization.
575 */
e134fb2b 576static void __init pcm037_init(void)
ce8ffef0 577{
4f163eb8 578 int ret;
ee14373c 579
b78d8e59
SG		 580 imx31_soc_init();
581
7dc3a6a5
SH		 582 regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
583
ee14373c 584 mxc_iomux_set_gpr(MUX_PGP_UH2, 1);
4f163eb8 585
01ac7d58
SH		 586 mxc_iomux_setup_multiple_pins(pcm037_pins, ARRAY_SIZE(pcm037_pins),
587 "pcm037");
588
ee14373c
SH		 589#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS \
590 | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
591
592 mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG);
593 mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG);
594 mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG);
595 mxc_iomux_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG);
596 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */
597 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */
598 mxc_iomux_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */
599 mxc_iomux_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */
600 mxc_iomux_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */
601 mxc_iomux_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */
602 mxc_iomux_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */
603 mxc_iomux_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */
604
574ec547
GL		 605 if (pcm037_variant() == PCM037_EET)
606 mxc_iomux_setup_multiple_pins(pcm037_uart1_pins,
607 ARRAY_SIZE(pcm037_uart1_pins), "pcm037_uart1");
608 else
609 mxc_iomux_setup_multiple_pins(pcm037_uart1_handshake_pins,
610 ARRAY_SIZE(pcm037_uart1_handshake_pins),
611 "pcm037_uart1");
612
ce8ffef0
SH		 613 platform_add_devices(devices, ARRAY_SIZE(devices));
614
bec31a85 615 imx31_add_imx2_wdt();
16cf5c41
UKK		 616 imx31_add_imx_uart0(&uart_pdata);
617 /* XXX: should't this have .flags = 0 (i.e. no RTSCTS) on PCM037_EET? */
618 imx31_add_imx_uart1(&uart_pdata);
619 imx31_add_imx_uart2(&uart_pdata);
d517cab1 620
bec31a85 621 imx31_add_mxc_w1();
ba54b958 622
f8e5143b 623 /* LAN9217 IRQ pin */
4f163eb8
SH		 624 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq");
625 if (ret)
626 pr_warning("could not get LAN irq gpio\n");
627 else {
628 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
ed175343
SG		 629 smsc911x_resources[1].start =
630 gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
631 smsc911x_resources[1].end =
632 gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
4f163eb8
SH		 633 platform_device_register(&pcm037_eth);
634 }
635
3287abbd 636
32c1ad9a 637 /* I2C adapters and devices */
79206750
SH		 638 i2c_register_board_info(1, pcm037_i2c_devices,
639 ARRAY_SIZE(pcm037_i2c_devices));
640
4a9b8b0b
UKK		 641 imx31_add_imx_i2c1(&pcm037_i2c1_data);
642 imx31_add_imx_i2c2(&pcm037_i2c2_data);
32c1ad9a 643
a2ceeef5 644 imx31_add_mxc_nand(&pcm037_nand_board_info);
6a697e3d 645 imx31_add_mxc_mmc(0, &sdhc_pdata);
88289c80 646 imx31_add_ipu_core();
afa77ef3 647 imx31_add_mx3_sdc_fb(&mx3fb_pdata);
32c1ad9a
GL		 648
649 /* CSI */
650 /* Camera power: default - off */
651 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), "mt9t031-power");
652 if (!ret)
653 gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), 1);
654 else
9d00278d 655 iclink_mt9t031.power = NULL;
32c1ad9a 656
afa77ef3 657 pcm037_init_camera();
91bf9a25 658
ed175343
SG		 659 pcm970_sja1000_resources[1].start =
660 gpio_to_irq(IOMUX_TO_GPIO(IOMUX_PIN(48, 105)));
661 pcm970_sja1000_resources[1].end =
662 gpio_to_irq(IOMUX_TO_GPIO(IOMUX_PIN(48, 105)));
91bf9a25 663 platform_device_register(&pcm970_sja1000);
ee14373c 664
ee14373c 665 if (otg_mode_host) {
48f6b099
SH		 666 otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
667 ULPI_OTG_DRVVBUS_EXT);
668 if (otg_pdata.otg)
669 imx31_add_mxc_ehci_otg(&otg_pdata);
ee14373c
SH		 670 }
671
48f6b099
SH		 672 usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
673 ULPI_OTG_DRVVBUS_EXT);
674 if (usbh2_pdata.otg)
675 imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
ee14373c 676
ee14373c 677 if (!otg_mode_host)
9e1dde33 678 imx31_add_fsl_usb2_udc(&otg_device_pdata);
ee14373c 679
ce8ffef0
SH		 680}
681
ce8ffef0
SH		 682static void __init pcm037_timer_init(void)
683{
30c730f8 684 mx31_clocks_init(26000000);
ce8ffef0
SH		 685}
686
dca7c0b4
UKK		 687static void __init pcm037_reserve(void)
688{
689 /* reserve 4 MiB for mx3-camera */
716a3dc2 690 mx3_camera_base = arm_memblock_steal(MX3_CAMERA_BUF_SIZE,
dca7c0b4 691 MX3_CAMERA_BUF_SIZE);
dca7c0b4
UKK		 692}
693
8321b758
SG		 694static void __init pcm037_init_late(void)
695{
696 pcm037_eet_init_devices();
697}
698
ce8ffef0
SH		 699MACHINE_START(PCM037, "Phytec Phycore pcm037")
700 /* Maintainer: Pengutronix */
dc8f1907 701 .atag_offset = 0x100,
dca7c0b4 702 .reserve = pcm037_reserve,
97976e22
UKK		 703 .map_io = mx31_map_io,
704 .init_early = imx31_init_early,
705 .init_irq = mx31_init_irq,
6bb27d73 706 .init_time = pcm037_timer_init,
e134fb2b 707 .init_machine = pcm037_init,
8321b758 708 .init_late = pcm037_init_late,
65ea7884 709 .restart = mxc_restart,
ce8ffef0 710MACHINE_END
Linux kernel - Deliverables
This page took 0.353235 seconds and 5 git commands to generate.