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8c25c36f SH |
1 | /* |
2 | * Copyright (C) 1999,2000 Arm Limited | |
3 | * Copyright (C) 2000 Deep Blue Solutions Ltd | |
4 | * Copyright (C) 2002 Shane Nay (shane@minirl.com) | |
5 | * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
6 | * - add MX31 specific definitions | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
8c25c36f SH |
17 | */ |
18 | ||
19 | #include <linux/mm.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/err.h> | |
22 | ||
23 | #include <asm/pgtable.h> | |
24 | #include <asm/mach/map.h> | |
25 | ||
26 | #include <mach/common.h> | |
27 | #include <mach/hardware.h> | |
28 | #include <mach/mx25.h> | |
29 | #include <mach/iomux-v3.h> | |
5ae30b47 | 30 | #include <mach/irqs.h> |
8c25c36f SH |
31 | |
32 | /* | |
33 | * This table defines static virtual address mappings for I/O regions. | |
08ff97b5 | 34 | * These are the mappings common across all MX25 boards. |
8c25c36f | 35 | */ |
08ff97b5 UKK |
36 | static struct map_desc mx25_io_desc[] __initdata = { |
37 | imx_map_entry(MX25, AVIC, MT_DEVICE_NONSHARED), | |
38 | imx_map_entry(MX25, AIPS1, MT_DEVICE_NONSHARED), | |
39 | imx_map_entry(MX25, AIPS2, MT_DEVICE_NONSHARED), | |
8c25c36f SH |
40 | }; |
41 | ||
42 | /* | |
43 | * This function initializes the memory map. It is called during the | |
44 | * system startup to create static physical to virtual memory mappings | |
45 | * for the IO modules. | |
46 | */ | |
47 | void __init mx25_map_io(void) | |
3dac2196 UKK |
48 | { |
49 | iotable_init(mx25_io_desc, ARRAY_SIZE(mx25_io_desc)); | |
50 | } | |
51 | ||
52 | void __init imx25_init_early(void) | |
8c25c36f SH |
53 | { |
54 | mxc_set_cpu_type(MXC_CPU_MX25); | |
55 | mxc_iomux_v3_init(MX25_IO_ADDRESS(MX25_IOMUXC_BASE_ADDR)); | |
56 | mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR)); | |
8c25c36f SH |
57 | } |
58 | ||
59 | void __init mx25_init_irq(void) | |
60 | { | |
cf3a6aba | 61 | mxc_init_irq(MX25_IO_ADDRESS(MX25_AVIC_BASE_ADDR)); |
8c25c36f SH |
62 | } |
63 | ||
b78d8e59 SG |
64 | void __init imx25_soc_init(void) |
65 | { | |
66 | mxc_register_gpio(0, MX25_GPIO1_BASE_ADDR, SZ_16K, MX25_INT_GPIO1, 0); | |
67 | mxc_register_gpio(1, MX25_GPIO2_BASE_ADDR, SZ_16K, MX25_INT_GPIO2, 0); | |
68 | mxc_register_gpio(2, MX25_GPIO3_BASE_ADDR, SZ_16K, MX25_INT_GPIO3, 0); | |
69 | mxc_register_gpio(3, MX25_GPIO4_BASE_ADDR, SZ_16K, MX25_INT_GPIO4, 0); | |
70 | } |