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27ad4bf7 UKK |
1 | /* |
2 | * Copyright (C) 1999,2000 Arm Limited | |
3 | * Copyright (C) 2000 Deep Blue Solutions Ltd | |
4 | * Copyright (C) 2002 Shane Nay (shane@minirl.com) | |
5 | * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
6 | * - add MX31 specific definitions | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | */ | |
18 | ||
19 | #include <linux/mm.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/err.h> | |
a2aa65a3 | 22 | #include <linux/pinctrl/machine.h> |
27ad4bf7 UKK |
23 | |
24 | #include <asm/pgtable.h> | |
86dfe446 | 25 | #include <asm/system_misc.h> |
ddd5f51b | 26 | #include <asm/hardware/cache-l2x0.h> |
27ad4bf7 UKK |
27 | #include <asm/mach/map.h> |
28 | ||
29 | #include <mach/common.h> | |
36223604 | 30 | #include <mach/devices-common.h> |
27ad4bf7 UKK |
31 | #include <mach/hardware.h> |
32 | #include <mach/iomux-v3.h> | |
27ad4bf7 | 33 | |
eb92044e SH |
34 | #include "crmregs-imx3.h" |
35 | ||
36 | void __iomem *mx3_ccm_base; | |
37 | ||
41e7daf2 SG |
38 | static void imx3_idle(void) |
39 | { | |
40 | unsigned long reg = 0; | |
8c6d8319 | 41 | |
3ac804e3 FE |
42 | mx3_cpu_lp_set(MX3_WAIT); |
43 | ||
4a3ea244 NP |
44 | __asm__ __volatile__( |
45 | /* disable I and D cache */ | |
46 | "mrc p15, 0, %0, c1, c0, 0\n" | |
47 | "bic %0, %0, #0x00001000\n" | |
48 | "bic %0, %0, #0x00000004\n" | |
49 | "mcr p15, 0, %0, c1, c0, 0\n" | |
50 | /* invalidate I cache */ | |
51 | "mov %0, #0\n" | |
52 | "mcr p15, 0, %0, c7, c5, 0\n" | |
53 | /* clear and invalidate D cache */ | |
54 | "mov %0, #0\n" | |
55 | "mcr p15, 0, %0, c7, c14, 0\n" | |
56 | /* WFI */ | |
57 | "mov %0, #0\n" | |
58 | "mcr p15, 0, %0, c7, c0, 4\n" | |
59 | "nop\n" "nop\n" "nop\n" "nop\n" | |
60 | "nop\n" "nop\n" "nop\n" | |
61 | /* enable I and D cache */ | |
62 | "mrc p15, 0, %0, c1, c0, 0\n" | |
63 | "orr %0, %0, #0x00001000\n" | |
64 | "orr %0, %0, #0x00000004\n" | |
65 | "mcr p15, 0, %0, c1, c0, 0\n" | |
66 | : "=r" (reg)); | |
41e7daf2 SG |
67 | } |
68 | ||
c177aa98 RH |
69 | static void __iomem *imx3_ioremap_caller(unsigned long phys_addr, size_t size, |
70 | unsigned int mtype, void *caller) | |
f548897f SG |
71 | { |
72 | if (mtype == MT_DEVICE) { | |
73 | /* | |
74 | * Access all peripherals below 0x80000000 as nonshared device | |
75 | * on mx3, but leave l2cc alone. Otherwise cache corruptions | |
76 | * can occur. | |
77 | */ | |
78 | if (phys_addr < 0x80000000 && | |
79 | !addr_in_module(phys_addr, MX3x_L2CC)) | |
80 | mtype = MT_DEVICE_NONSHARED; | |
81 | } | |
82 | ||
c177aa98 | 83 | return __arm_ioremap_caller(phys_addr, size, mtype, caller); |
f548897f SG |
84 | } |
85 | ||
9418ba30 | 86 | void __init imx3_init_l2x0(void) |
ddd5f51b | 87 | { |
f90da3c7 | 88 | #ifdef CONFIG_CACHE_L2X0 |
ddd5f51b SG |
89 | void __iomem *l2x0_base; |
90 | void __iomem *clkctl_base; | |
91 | ||
92 | /* | |
93 | * First of all, we must repair broken chip settings. There are some | |
94 | * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These | |
95 | * misconfigured CPUs will run amok immediately when the L2 cache gets enabled. | |
96 | * Workaraound is to setup the correct register setting prior enabling the | |
97 | * L2 cache. This should not hurt already working CPUs, as they are using the | |
98 | * same value. | |
99 | */ | |
100 | #define L2_MEM_VAL 0x10 | |
101 | ||
102 | clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096); | |
103 | if (clkctl_base != NULL) { | |
104 | writel(0x00000515, clkctl_base + L2_MEM_VAL); | |
105 | iounmap(clkctl_base); | |
106 | } else { | |
107 | pr_err("L2 cache: Cannot fix timing. Trying to continue without\n"); | |
108 | } | |
109 | ||
110 | l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096); | |
111 | if (IS_ERR(l2x0_base)) { | |
112 | printk(KERN_ERR "remapping L2 cache area failed with %ld\n", | |
113 | PTR_ERR(l2x0_base)); | |
114 | return; | |
115 | } | |
116 | ||
117 | l2x0_init(l2x0_base, 0x00030024, 0x00000000); | |
f90da3c7 | 118 | #endif |
ddd5f51b SG |
119 | } |
120 | ||
87514fce | 121 | #ifdef CONFIG_SOC_IMX31 |
27ad4bf7 UKK |
122 | static struct map_desc mx31_io_desc[] __initdata = { |
123 | imx_map_entry(MX31, X_MEMC, MT_DEVICE), | |
124 | imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED), | |
125 | imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED), | |
126 | imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED), | |
127 | imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED), | |
128 | }; | |
129 | ||
130 | /* | |
131 | * This function initializes the memory map. It is called during the | |
132 | * system startup to create static physical to virtual memory mappings | |
133 | * for the IO modules. | |
134 | */ | |
135 | void __init mx31_map_io(void) | |
136 | { | |
137 | iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc)); | |
138 | } | |
139 | ||
140 | void __init imx31_init_early(void) | |
141 | { | |
142 | mxc_set_cpu_type(MXC_CPU_MX31); | |
143 | mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR)); | |
c177aa98 | 144 | arch_ioremap_caller = imx3_ioremap_caller; |
4a3ea244 | 145 | arm_pm_idle = imx3_idle; |
eb92044e | 146 | mx3_ccm_base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR); |
27ad4bf7 UKK |
147 | } |
148 | ||
27ad4bf7 UKK |
149 | void __init mx31_init_irq(void) |
150 | { | |
151 | mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR)); | |
b78d8e59 SG |
152 | } |
153 | ||
36223604 SG |
154 | static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = { |
155 | .per_2_per_addr = 1677, | |
156 | }; | |
157 | ||
158 | static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata = { | |
159 | .ap_2_ap_addr = 423, | |
160 | .ap_2_bp_addr = 829, | |
161 | .bp_2_ap_addr = 1029, | |
162 | }; | |
163 | ||
164 | static struct sdma_platform_data imx31_sdma_pdata __initdata = { | |
2e534b21 | 165 | .fw_name = "sdma-imx31-to2.bin", |
36223604 SG |
166 | .script_addrs = &imx31_to2_sdma_script, |
167 | }; | |
168 | ||
3bc34a61 RZ |
169 | static const struct resource imx31_audmux_res[] __initconst = { |
170 | DEFINE_RES_MEM(MX31_AUDMUX_BASE_ADDR, SZ_16K), | |
171 | }; | |
172 | ||
b78d8e59 SG |
173 | void __init imx31_soc_init(void) |
174 | { | |
36223604 SG |
175 | int to_version = mx31_revision() >> 4; |
176 | ||
ddd5f51b SG |
177 | imx3_init_l2x0(); |
178 | ||
e7fc6ae7 SG |
179 | mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0); |
180 | mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0); | |
181 | mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0); | |
36223604 | 182 | |
aa29cab3 FE |
183 | pinctrl_provide_dummies(); |
184 | ||
2e534b21 SG |
185 | if (to_version == 1) { |
186 | strncpy(imx31_sdma_pdata.fw_name, "sdma-imx31-to1.bin", | |
187 | strlen(imx31_sdma_pdata.fw_name)); | |
36223604 | 188 | imx31_sdma_pdata.script_addrs = &imx31_to1_sdma_script; |
2e534b21 SG |
189 | } |
190 | ||
62550cd7 | 191 | imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata); |
bb07d751 FE |
192 | |
193 | imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS1_BASE_ADDR)); | |
194 | imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS2_BASE_ADDR)); | |
281b0539 | 195 | |
3bc34a61 RZ |
196 | platform_device_register_simple("imx31-audmux", 0, imx31_audmux_res, |
197 | ARRAY_SIZE(imx31_audmux_res)); | |
27ad4bf7 | 198 | } |
87514fce UKK |
199 | #endif /* ifdef CONFIG_SOC_IMX31 */ |
200 | ||
201 | #ifdef CONFIG_SOC_IMX35 | |
202 | static struct map_desc mx35_io_desc[] __initdata = { | |
203 | imx_map_entry(MX35, X_MEMC, MT_DEVICE), | |
204 | imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED), | |
205 | imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED), | |
206 | imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED), | |
207 | imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED), | |
208 | }; | |
209 | ||
210 | void __init mx35_map_io(void) | |
211 | { | |
212 | iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc)); | |
213 | } | |
214 | ||
215 | void __init imx35_init_early(void) | |
216 | { | |
217 | mxc_set_cpu_type(MXC_CPU_MX35); | |
218 | mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR)); | |
219 | mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR)); | |
4a3ea244 | 220 | arm_pm_idle = imx3_idle; |
c177aa98 | 221 | arch_ioremap_caller = imx3_ioremap_caller; |
eb92044e | 222 | mx3_ccm_base = MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR); |
87514fce UKK |
223 | } |
224 | ||
225 | void __init mx35_init_irq(void) | |
226 | { | |
227 | mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR)); | |
228 | } | |
f1263de2 SG |
229 | |
230 | static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = { | |
231 | .ap_2_ap_addr = 642, | |
232 | .uart_2_mcu_addr = 817, | |
233 | .mcu_2_app_addr = 747, | |
234 | .uartsh_2_mcu_addr = 1183, | |
235 | .per_2_shp_addr = 1033, | |
236 | .mcu_2_shp_addr = 961, | |
237 | .ata_2_mcu_addr = 1333, | |
238 | .mcu_2_ata_addr = 1252, | |
239 | .app_2_mcu_addr = 683, | |
240 | .shp_2_per_addr = 1111, | |
241 | .shp_2_mcu_addr = 892, | |
242 | }; | |
243 | ||
244 | static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata = { | |
245 | .ap_2_ap_addr = 729, | |
246 | .uart_2_mcu_addr = 904, | |
247 | .per_2_app_addr = 1597, | |
248 | .mcu_2_app_addr = 834, | |
249 | .uartsh_2_mcu_addr = 1270, | |
250 | .per_2_shp_addr = 1120, | |
251 | .mcu_2_shp_addr = 1048, | |
252 | .ata_2_mcu_addr = 1429, | |
253 | .mcu_2_ata_addr = 1339, | |
254 | .app_2_per_addr = 1531, | |
255 | .app_2_mcu_addr = 770, | |
256 | .shp_2_per_addr = 1198, | |
257 | .shp_2_mcu_addr = 979, | |
258 | }; | |
259 | ||
260 | static struct sdma_platform_data imx35_sdma_pdata __initdata = { | |
261 | .fw_name = "sdma-imx35-to2.bin", | |
262 | .script_addrs = &imx35_to2_sdma_script, | |
263 | }; | |
264 | ||
3bc34a61 RZ |
265 | static const struct resource imx35_audmux_res[] __initconst = { |
266 | DEFINE_RES_MEM(MX35_AUDMUX_BASE_ADDR, SZ_16K), | |
267 | }; | |
268 | ||
f1263de2 SG |
269 | void __init imx35_soc_init(void) |
270 | { | |
271 | int to_version = mx35_revision() >> 4; | |
272 | ||
ddd5f51b SG |
273 | imx3_init_l2x0(); |
274 | ||
aeb27748 BT |
275 | mxc_register_gpio("imx35-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0); |
276 | mxc_register_gpio("imx35-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0); | |
277 | mxc_register_gpio("imx35-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0); | |
f1263de2 | 278 | |
a2aa65a3 | 279 | pinctrl_provide_dummies(); |
f1263de2 SG |
280 | if (to_version == 1) { |
281 | strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin", | |
282 | strlen(imx35_sdma_pdata.fw_name)); | |
283 | imx35_sdma_pdata.script_addrs = &imx35_to1_sdma_script; | |
284 | } | |
285 | ||
286 | imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata); | |
38bb3630 FE |
287 | |
288 | /* Setup AIPS registers */ | |
289 | imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS1_BASE_ADDR)); | |
290 | imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS2_BASE_ADDR)); | |
281b0539 | 291 | |
3bc34a61 RZ |
292 | /* i.mx35 has the i.mx31 type audmux */ |
293 | platform_device_register_simple("imx31-audmux", 0, imx35_audmux_res, | |
294 | ARRAY_SIZE(imx35_audmux_res)); | |
f1263de2 | 295 | } |
87514fce | 296 | #endif /* ifdef CONFIG_SOC_IMX35 */ |