Commit | Line | Data |
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a329b48c | 1 | /* |
b66ff7a2 | 2 | * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. |
a329b48c AK |
3 | * |
4 | * The code contained herein is licensed under the GNU General Public | |
5 | * License. You may obtain a copy of the GNU General Public License | |
6 | * Version 2 or later at the following locations: | |
7 | * | |
8 | * http://www.opensource.org/licenses/gpl-license.html | |
9 | * http://www.gnu.org/copyleft/gpl.html | |
10 | * | |
11 | * Create static mapping between physical to virtual memory. | |
12 | */ | |
13 | ||
14 | #include <linux/mm.h> | |
15 | #include <linux/init.h> | |
010dc8af | 16 | #include <linux/clk.h> |
a2aa65a3 | 17 | #include <linux/pinctrl/machine.h> |
a329b48c AK |
18 | |
19 | #include <asm/mach/map.h> | |
20 | ||
21 | #include <mach/hardware.h> | |
22 | #include <mach/common.h> | |
36223604 | 23 | #include <mach/devices-common.h> |
a329b48c AK |
24 | #include <mach/iomux-v3.h> |
25 | ||
abca2e10 JL |
26 | /* |
27 | * Define the MX50 memory map. | |
28 | */ | |
29 | static struct map_desc mx50_io_desc[] __initdata = { | |
30 | imx_map_entry(MX50, TZIC, MT_DEVICE), | |
31 | imx_map_entry(MX50, SPBA0, MT_DEVICE), | |
32 | imx_map_entry(MX50, AIPS1, MT_DEVICE), | |
33 | imx_map_entry(MX50, AIPS2, MT_DEVICE), | |
34 | }; | |
35 | ||
a329b48c AK |
36 | /* |
37 | * Define the MX51 memory map. | |
38 | */ | |
08ff97b5 | 39 | static struct map_desc mx51_io_desc[] __initdata = { |
4c542390 | 40 | imx_map_entry(MX51, TZIC, MT_DEVICE), |
08ff97b5 | 41 | imx_map_entry(MX51, IRAM, MT_DEVICE), |
08ff97b5 UKK |
42 | imx_map_entry(MX51, AIPS1, MT_DEVICE), |
43 | imx_map_entry(MX51, SPBA0, MT_DEVICE), | |
44 | imx_map_entry(MX51, AIPS2, MT_DEVICE), | |
a329b48c AK |
45 | }; |
46 | ||
b66ff7a2 DN |
47 | /* |
48 | * Define the MX53 memory map. | |
49 | */ | |
50 | static struct map_desc mx53_io_desc[] __initdata = { | |
4c542390 | 51 | imx_map_entry(MX53, TZIC, MT_DEVICE), |
b66ff7a2 DN |
52 | imx_map_entry(MX53, AIPS1, MT_DEVICE), |
53 | imx_map_entry(MX53, SPBA0, MT_DEVICE), | |
54 | imx_map_entry(MX53, AIPS2, MT_DEVICE), | |
55 | }; | |
56 | ||
a329b48c AK |
57 | /* |
58 | * This function initializes the memory map. It is called during the | |
59 | * system startup to create static physical to virtual memory mappings | |
60 | * for the IO modules. | |
61 | */ | |
abca2e10 JL |
62 | void __init mx50_map_io(void) |
63 | { | |
64 | iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc)); | |
65 | } | |
66 | ||
a329b48c | 67 | void __init mx51_map_io(void) |
ab130421 UKK |
68 | { |
69 | iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc)); | |
70 | } | |
71 | ||
abca2e10 JL |
72 | void __init mx53_map_io(void) |
73 | { | |
74 | iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc)); | |
75 | } | |
76 | ||
77 | void __init imx50_init_early(void) | |
78 | { | |
79 | mxc_set_cpu_type(MXC_CPU_MX50); | |
80 | mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR)); | |
81 | mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR)); | |
82 | } | |
83 | ||
ab130421 | 84 | void __init imx51_init_early(void) |
a329b48c | 85 | { |
a329b48c AK |
86 | mxc_set_cpu_type(MXC_CPU_MX51); |
87 | mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR)); | |
8c2efec3 | 88 | mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR)); |
a329b48c AK |
89 | } |
90 | ||
ab130421 | 91 | void __init imx53_init_early(void) |
b66ff7a2 DN |
92 | { |
93 | mxc_set_cpu_type(MXC_CPU_MX53); | |
94 | mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR)); | |
78c73591 | 95 | mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR)); |
b66ff7a2 DN |
96 | } |
97 | ||
abca2e10 | 98 | void __init mx50_init_irq(void) |
a329b48c | 99 | { |
abca2e10 JL |
100 | tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR)); |
101 | } | |
3d1bc862 | 102 | |
a329b48c AK |
103 | void __init mx51_init_irq(void) |
104 | { | |
4c542390 | 105 | tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR)); |
a329b48c | 106 | } |
c0abefd3 | 107 | |
c0abefd3 DN |
108 | void __init mx53_init_irq(void) |
109 | { | |
4c542390 | 110 | tzic_init_irq(MX53_IO_ADDRESS(MX53_TZIC_BASE_ADDR)); |
b78d8e59 SG |
111 | } |
112 | ||
36223604 SG |
113 | static struct sdma_script_start_addrs imx51_sdma_script __initdata = { |
114 | .ap_2_ap_addr = 642, | |
115 | .uart_2_mcu_addr = 817, | |
116 | .mcu_2_app_addr = 747, | |
117 | .mcu_2_shp_addr = 961, | |
118 | .ata_2_mcu_addr = 1473, | |
119 | .mcu_2_ata_addr = 1392, | |
120 | .app_2_per_addr = 1033, | |
121 | .app_2_mcu_addr = 683, | |
122 | .shp_2_per_addr = 1251, | |
123 | .shp_2_mcu_addr = 892, | |
124 | }; | |
125 | ||
126 | static struct sdma_platform_data imx51_sdma_pdata __initdata = { | |
2e534b21 | 127 | .fw_name = "sdma-imx51.bin", |
36223604 SG |
128 | .script_addrs = &imx51_sdma_script, |
129 | }; | |
130 | ||
3bc34a61 RZ |
131 | static const struct resource imx50_audmux_res[] __initconst = { |
132 | DEFINE_RES_MEM(MX50_AUDMUX_BASE_ADDR, SZ_16K), | |
133 | }; | |
134 | ||
135 | static const struct resource imx51_audmux_res[] __initconst = { | |
136 | DEFINE_RES_MEM(MX51_AUDMUX_BASE_ADDR, SZ_16K), | |
137 | }; | |
138 | ||
abca2e10 JL |
139 | void __init imx50_soc_init(void) |
140 | { | |
aeb27748 BT |
141 | /* i.mx50 has the i.mx35 type gpio */ |
142 | mxc_register_gpio("imx35-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH); | |
143 | mxc_register_gpio("imx35-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH); | |
144 | mxc_register_gpio("imx35-gpio", 2, MX50_GPIO3_BASE_ADDR, SZ_16K, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH); | |
145 | mxc_register_gpio("imx35-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH); | |
146 | mxc_register_gpio("imx35-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH); | |
147 | mxc_register_gpio("imx35-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH); | |
3bc34a61 RZ |
148 | |
149 | /* i.mx50 has the i.mx31 type audmux */ | |
150 | platform_device_register_simple("imx31-audmux", 0, imx50_audmux_res, | |
151 | ARRAY_SIZE(imx50_audmux_res)); | |
abca2e10 JL |
152 | } |
153 | ||
b78d8e59 SG |
154 | void __init imx51_soc_init(void) |
155 | { | |
aeb27748 BT |
156 | /* i.mx51 has the i.mx35 type gpio */ |
157 | mxc_register_gpio("imx35-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_INT_GPIO1_LOW, MX51_INT_GPIO1_HIGH); | |
158 | mxc_register_gpio("imx35-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_INT_GPIO2_LOW, MX51_INT_GPIO2_HIGH); | |
159 | mxc_register_gpio("imx35-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_INT_GPIO3_LOW, MX51_INT_GPIO3_HIGH); | |
160 | mxc_register_gpio("imx35-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_INT_GPIO4_LOW, MX51_INT_GPIO4_HIGH); | |
36223604 | 161 | |
eb5558dd FE |
162 | pinctrl_provide_dummies(); |
163 | ||
62550cd7 SG |
164 | /* i.mx51 has the i.mx35 type sdma */ |
165 | imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata); | |
aa6a9fa1 FE |
166 | |
167 | /* Setup AIPS registers */ | |
168 | imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR)); | |
169 | imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR)); | |
281b0539 | 170 | |
3bc34a61 RZ |
171 | /* i.mx51 has the i.mx31 type audmux */ |
172 | platform_device_register_simple("imx31-audmux", 0, imx51_audmux_res, | |
173 | ARRAY_SIZE(imx51_audmux_res)); | |
b78d8e59 SG |
174 | } |
175 | ||
8321b758 SG |
176 | void __init imx51_init_late(void) |
177 | { | |
178 | mx51_neon_fixup(); | |
565fa91f | 179 | imx51_pm_init(); |
8321b758 | 180 | } |
aa96a18d RL |
181 | |
182 | void __init imx53_init_late(void) | |
183 | { | |
184 | imx53_pm_init(); | |
8321b758 | 185 | } |