Commit | Line | Data |
---|---|---|
a329b48c | 1 | /* |
b66ff7a2 | 2 | * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. |
a329b48c AK |
3 | * |
4 | * The code contained herein is licensed under the GNU General Public | |
5 | * License. You may obtain a copy of the GNU General Public License | |
6 | * Version 2 or later at the following locations: | |
7 | * | |
8 | * http://www.opensource.org/licenses/gpl-license.html | |
9 | * http://www.gnu.org/copyleft/gpl.html | |
10 | * | |
11 | * Create static mapping between physical to virtual memory. | |
12 | */ | |
13 | ||
14 | #include <linux/mm.h> | |
15 | #include <linux/init.h> | |
010dc8af | 16 | #include <linux/clk.h> |
a2aa65a3 | 17 | #include <linux/pinctrl/machine.h> |
a329b48c | 18 | |
86dfe446 | 19 | #include <asm/system_misc.h> |
a329b48c AK |
20 | #include <asm/mach/map.h> |
21 | ||
22 | #include <mach/hardware.h> | |
23 | #include <mach/common.h> | |
36223604 | 24 | #include <mach/devices-common.h> |
a329b48c AK |
25 | #include <mach/iomux-v3.h> |
26 | ||
010dc8af HW |
27 | static struct clk *gpc_dvfs_clk; |
28 | ||
41e7daf2 SG |
29 | static void imx5_idle(void) |
30 | { | |
4a3ea244 NP |
31 | /* gpc clock is needed for SRPG */ |
32 | if (gpc_dvfs_clk == NULL) { | |
33 | gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs"); | |
34 | if (IS_ERR(gpc_dvfs_clk)) | |
35 | return; | |
096c19c3 | 36 | clk_prepare(gpc_dvfs_clk); |
010dc8af | 37 | } |
4a3ea244 NP |
38 | clk_enable(gpc_dvfs_clk); |
39 | mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF); | |
4659b7f1 | 40 | if (!tzic_enable_wake()) |
4a3ea244 NP |
41 | cpu_do_idle(); |
42 | clk_disable(gpc_dvfs_clk); | |
41e7daf2 SG |
43 | } |
44 | ||
abca2e10 JL |
45 | /* |
46 | * Define the MX50 memory map. | |
47 | */ | |
48 | static struct map_desc mx50_io_desc[] __initdata = { | |
49 | imx_map_entry(MX50, TZIC, MT_DEVICE), | |
50 | imx_map_entry(MX50, SPBA0, MT_DEVICE), | |
51 | imx_map_entry(MX50, AIPS1, MT_DEVICE), | |
52 | imx_map_entry(MX50, AIPS2, MT_DEVICE), | |
53 | }; | |
54 | ||
a329b48c AK |
55 | /* |
56 | * Define the MX51 memory map. | |
57 | */ | |
08ff97b5 | 58 | static struct map_desc mx51_io_desc[] __initdata = { |
4c542390 | 59 | imx_map_entry(MX51, TZIC, MT_DEVICE), |
08ff97b5 | 60 | imx_map_entry(MX51, IRAM, MT_DEVICE), |
08ff97b5 UKK |
61 | imx_map_entry(MX51, AIPS1, MT_DEVICE), |
62 | imx_map_entry(MX51, SPBA0, MT_DEVICE), | |
63 | imx_map_entry(MX51, AIPS2, MT_DEVICE), | |
a329b48c AK |
64 | }; |
65 | ||
b66ff7a2 DN |
66 | /* |
67 | * Define the MX53 memory map. | |
68 | */ | |
69 | static struct map_desc mx53_io_desc[] __initdata = { | |
4c542390 | 70 | imx_map_entry(MX53, TZIC, MT_DEVICE), |
b66ff7a2 DN |
71 | imx_map_entry(MX53, AIPS1, MT_DEVICE), |
72 | imx_map_entry(MX53, SPBA0, MT_DEVICE), | |
73 | imx_map_entry(MX53, AIPS2, MT_DEVICE), | |
74 | }; | |
75 | ||
a329b48c AK |
76 | /* |
77 | * This function initializes the memory map. It is called during the | |
78 | * system startup to create static physical to virtual memory mappings | |
79 | * for the IO modules. | |
80 | */ | |
abca2e10 JL |
81 | void __init mx50_map_io(void) |
82 | { | |
83 | iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc)); | |
84 | } | |
85 | ||
a329b48c | 86 | void __init mx51_map_io(void) |
ab130421 UKK |
87 | { |
88 | iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc)); | |
89 | } | |
90 | ||
abca2e10 JL |
91 | void __init mx53_map_io(void) |
92 | { | |
93 | iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc)); | |
94 | } | |
95 | ||
96 | void __init imx50_init_early(void) | |
97 | { | |
98 | mxc_set_cpu_type(MXC_CPU_MX50); | |
99 | mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR)); | |
100 | mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR)); | |
101 | } | |
102 | ||
ab130421 | 103 | void __init imx51_init_early(void) |
a329b48c | 104 | { |
a329b48c AK |
105 | mxc_set_cpu_type(MXC_CPU_MX51); |
106 | mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR)); | |
8c2efec3 | 107 | mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR)); |
4a3ea244 | 108 | arm_pm_idle = imx5_idle; |
a329b48c AK |
109 | } |
110 | ||
ab130421 | 111 | void __init imx53_init_early(void) |
b66ff7a2 DN |
112 | { |
113 | mxc_set_cpu_type(MXC_CPU_MX53); | |
114 | mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR)); | |
78c73591 | 115 | mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR)); |
b66ff7a2 DN |
116 | } |
117 | ||
abca2e10 | 118 | void __init mx50_init_irq(void) |
a329b48c | 119 | { |
abca2e10 JL |
120 | tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR)); |
121 | } | |
3d1bc862 | 122 | |
a329b48c AK |
123 | void __init mx51_init_irq(void) |
124 | { | |
4c542390 | 125 | tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR)); |
a329b48c | 126 | } |
c0abefd3 | 127 | |
c0abefd3 DN |
128 | void __init mx53_init_irq(void) |
129 | { | |
4c542390 | 130 | tzic_init_irq(MX53_IO_ADDRESS(MX53_TZIC_BASE_ADDR)); |
b78d8e59 SG |
131 | } |
132 | ||
36223604 SG |
133 | static struct sdma_script_start_addrs imx51_sdma_script __initdata = { |
134 | .ap_2_ap_addr = 642, | |
135 | .uart_2_mcu_addr = 817, | |
136 | .mcu_2_app_addr = 747, | |
137 | .mcu_2_shp_addr = 961, | |
138 | .ata_2_mcu_addr = 1473, | |
139 | .mcu_2_ata_addr = 1392, | |
140 | .app_2_per_addr = 1033, | |
141 | .app_2_mcu_addr = 683, | |
142 | .shp_2_per_addr = 1251, | |
143 | .shp_2_mcu_addr = 892, | |
144 | }; | |
145 | ||
146 | static struct sdma_platform_data imx51_sdma_pdata __initdata = { | |
2e534b21 | 147 | .fw_name = "sdma-imx51.bin", |
36223604 SG |
148 | .script_addrs = &imx51_sdma_script, |
149 | }; | |
150 | ||
151 | static struct sdma_script_start_addrs imx53_sdma_script __initdata = { | |
152 | .ap_2_ap_addr = 642, | |
153 | .app_2_mcu_addr = 683, | |
154 | .mcu_2_app_addr = 747, | |
155 | .uart_2_mcu_addr = 817, | |
156 | .shp_2_mcu_addr = 891, | |
157 | .mcu_2_shp_addr = 960, | |
158 | .uartsh_2_mcu_addr = 1032, | |
159 | .spdif_2_mcu_addr = 1100, | |
160 | .mcu_2_spdif_addr = 1134, | |
161 | .firi_2_mcu_addr = 1193, | |
162 | .mcu_2_firi_addr = 1290, | |
163 | }; | |
164 | ||
165 | static struct sdma_platform_data imx53_sdma_pdata __initdata = { | |
2e534b21 | 166 | .fw_name = "sdma-imx53.bin", |
36223604 SG |
167 | .script_addrs = &imx53_sdma_script, |
168 | }; | |
169 | ||
3bc34a61 RZ |
170 | static const struct resource imx50_audmux_res[] __initconst = { |
171 | DEFINE_RES_MEM(MX50_AUDMUX_BASE_ADDR, SZ_16K), | |
172 | }; | |
173 | ||
174 | static const struct resource imx51_audmux_res[] __initconst = { | |
175 | DEFINE_RES_MEM(MX51_AUDMUX_BASE_ADDR, SZ_16K), | |
176 | }; | |
177 | ||
178 | static const struct resource imx53_audmux_res[] __initconst = { | |
179 | DEFINE_RES_MEM(MX53_AUDMUX_BASE_ADDR, SZ_16K), | |
180 | }; | |
181 | ||
abca2e10 JL |
182 | void __init imx50_soc_init(void) |
183 | { | |
184 | /* i.mx50 has the i.mx31 type gpio */ | |
185 | mxc_register_gpio("imx31-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH); | |
186 | mxc_register_gpio("imx31-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH); | |
187 | mxc_register_gpio("imx31-gpio", 2, MX50_GPIO3_BASE_ADDR, SZ_16K, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH); | |
188 | mxc_register_gpio("imx31-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH); | |
189 | mxc_register_gpio("imx31-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH); | |
190 | mxc_register_gpio("imx31-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH); | |
3bc34a61 RZ |
191 | |
192 | /* i.mx50 has the i.mx31 type audmux */ | |
193 | platform_device_register_simple("imx31-audmux", 0, imx50_audmux_res, | |
194 | ARRAY_SIZE(imx50_audmux_res)); | |
abca2e10 JL |
195 | } |
196 | ||
b78d8e59 SG |
197 | void __init imx51_soc_init(void) |
198 | { | |
e7fc6ae7 | 199 | /* i.mx51 has the i.mx31 type gpio */ |
1a195277 UKK |
200 | mxc_register_gpio("imx31-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_INT_GPIO1_LOW, MX51_INT_GPIO1_HIGH); |
201 | mxc_register_gpio("imx31-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_INT_GPIO2_LOW, MX51_INT_GPIO2_HIGH); | |
202 | mxc_register_gpio("imx31-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_INT_GPIO3_LOW, MX51_INT_GPIO3_HIGH); | |
203 | mxc_register_gpio("imx31-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_INT_GPIO4_LOW, MX51_INT_GPIO4_HIGH); | |
36223604 | 204 | |
eb5558dd FE |
205 | pinctrl_provide_dummies(); |
206 | ||
62550cd7 SG |
207 | /* i.mx51 has the i.mx35 type sdma */ |
208 | imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata); | |
aa6a9fa1 FE |
209 | |
210 | /* Setup AIPS registers */ | |
211 | imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR)); | |
212 | imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR)); | |
281b0539 | 213 | |
3bc34a61 RZ |
214 | /* i.mx51 has the i.mx31 type audmux */ |
215 | platform_device_register_simple("imx31-audmux", 0, imx51_audmux_res, | |
216 | ARRAY_SIZE(imx51_audmux_res)); | |
b78d8e59 SG |
217 | } |
218 | ||
219 | void __init imx53_soc_init(void) | |
220 | { | |
e7fc6ae7 SG |
221 | /* i.mx53 has the i.mx31 type gpio */ |
222 | mxc_register_gpio("imx31-gpio", 0, MX53_GPIO1_BASE_ADDR, SZ_16K, MX53_INT_GPIO1_LOW, MX53_INT_GPIO1_HIGH); | |
223 | mxc_register_gpio("imx31-gpio", 1, MX53_GPIO2_BASE_ADDR, SZ_16K, MX53_INT_GPIO2_LOW, MX53_INT_GPIO2_HIGH); | |
224 | mxc_register_gpio("imx31-gpio", 2, MX53_GPIO3_BASE_ADDR, SZ_16K, MX53_INT_GPIO3_LOW, MX53_INT_GPIO3_HIGH); | |
225 | mxc_register_gpio("imx31-gpio", 3, MX53_GPIO4_BASE_ADDR, SZ_16K, MX53_INT_GPIO4_LOW, MX53_INT_GPIO4_HIGH); | |
226 | mxc_register_gpio("imx31-gpio", 4, MX53_GPIO5_BASE_ADDR, SZ_16K, MX53_INT_GPIO5_LOW, MX53_INT_GPIO5_HIGH); | |
227 | mxc_register_gpio("imx31-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH); | |
228 | mxc_register_gpio("imx31-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH); | |
36223604 | 229 | |
a2aa65a3 | 230 | pinctrl_provide_dummies(); |
62550cd7 SG |
231 | /* i.mx53 has the i.mx35 type sdma */ |
232 | imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata); | |
aa6a9fa1 FE |
233 | |
234 | /* Setup AIPS registers */ | |
235 | imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR)); | |
236 | imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR)); | |
281b0539 | 237 | |
3bc34a61 RZ |
238 | /* i.mx53 has the i.mx31 type audmux */ |
239 | platform_device_register_simple("imx31-audmux", 0, imx53_audmux_res, | |
240 | ARRAY_SIZE(imx53_audmux_res)); | |
c0abefd3 | 241 | } |
8321b758 SG |
242 | |
243 | void __init imx51_init_late(void) | |
244 | { | |
245 | mx51_neon_fixup(); | |
246 | } |