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52c543f9 | 1 | /* |
64f102b6 | 2 | * Copyright 2004-2007, 2010 Freescale Semiconductor, Inc. All Rights Reserved. |
d0f349fb JB |
3 | * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | |
17 | * MA 02110-1301, USA. | |
52c543f9 QJ |
18 | */ |
19 | ||
20 | #ifndef __ASM_ARCH_MXC_H__ | |
21 | #define __ASM_ARCH_MXC_H__ | |
22 | ||
64f102b6 YS |
23 | #include <linux/types.h> |
24 | ||
52c543f9 QJ |
25 | #ifndef __ASM_ARCH_MXC_HARDWARE_H__ |
26 | #error "Do not include directly." | |
27 | #endif | |
28 | ||
198016e1 SH |
29 | #define MXC_CPU_MX1 1 |
30 | #define MXC_CPU_MX21 21 | |
8c25c36f | 31 | #define MXC_CPU_MX25 25 |
198016e1 SH |
32 | #define MXC_CPU_MX27 27 |
33 | #define MXC_CPU_MX31 31 | |
34 | #define MXC_CPU_MX35 35 | |
438caa3f | 35 | #define MXC_CPU_MX51 51 |
c0abefd3 | 36 | #define MXC_CPU_MX53 53 |
a2887546 | 37 | #define MXC_CPU_IMX6SL 0x60 |
3c03a2fe | 38 | #define MXC_CPU_IMX6DL 0x61 |
d9654dce | 39 | #define MXC_CPU_IMX6SX 0x62 |
3c03a2fe | 40 | #define MXC_CPU_IMX6Q 0x63 |
198016e1 | 41 | |
9ab4650f DN |
42 | #define IMX_CHIP_REVISION_1_0 0x10 |
43 | #define IMX_CHIP_REVISION_1_1 0x11 | |
44 | #define IMX_CHIP_REVISION_1_2 0x12 | |
45 | #define IMX_CHIP_REVISION_1_3 0x13 | |
46 | #define IMX_CHIP_REVISION_2_0 0x20 | |
47 | #define IMX_CHIP_REVISION_2_1 0x21 | |
48 | #define IMX_CHIP_REVISION_2_2 0x22 | |
49 | #define IMX_CHIP_REVISION_2_3 0x23 | |
50 | #define IMX_CHIP_REVISION_3_0 0x30 | |
51 | #define IMX_CHIP_REVISION_3_1 0x31 | |
52 | #define IMX_CHIP_REVISION_3_2 0x32 | |
53 | #define IMX_CHIP_REVISION_3_3 0x33 | |
54 | #define IMX_CHIP_REVISION_UNKNOWN 0xff | |
55 | ||
198016e1 SH |
56 | #ifndef __ASSEMBLY__ |
57 | extern unsigned int __mxc_cpu_type; | |
58 | #endif | |
59 | ||
7bce7e8c | 60 | #ifdef CONFIG_SOC_IMX1 |
198016e1 SH |
61 | # ifdef mxc_cpu_type |
62 | # undef mxc_cpu_type | |
63 | # define mxc_cpu_type __mxc_cpu_type | |
64 | # else | |
65 | # define mxc_cpu_type MXC_CPU_MX1 | |
66 | # endif | |
67 | # define cpu_is_mx1() (mxc_cpu_type == MXC_CPU_MX1) | |
68 | #else | |
69 | # define cpu_is_mx1() (0) | |
d2db9aaa RS |
70 | #endif |
71 | ||
7bce7e8c | 72 | #ifdef CONFIG_SOC_IMX21 |
198016e1 SH |
73 | # ifdef mxc_cpu_type |
74 | # undef mxc_cpu_type | |
75 | # define mxc_cpu_type __mxc_cpu_type | |
76 | # else | |
77 | # define mxc_cpu_type MXC_CPU_MX21 | |
78 | # endif | |
79 | # define cpu_is_mx21() (mxc_cpu_type == MXC_CPU_MX21) | |
80 | #else | |
81 | # define cpu_is_mx21() (0) | |
5512e88f HS |
82 | #endif |
83 | ||
7bce7e8c | 84 | #ifdef CONFIG_SOC_IMX25 |
8c25c36f SH |
85 | # ifdef mxc_cpu_type |
86 | # undef mxc_cpu_type | |
87 | # define mxc_cpu_type __mxc_cpu_type | |
88 | # else | |
89 | # define mxc_cpu_type MXC_CPU_MX25 | |
90 | # endif | |
91 | # define cpu_is_mx25() (mxc_cpu_type == MXC_CPU_MX25) | |
92 | #else | |
93 | # define cpu_is_mx25() (0) | |
94 | #endif | |
95 | ||
7bce7e8c | 96 | #ifdef CONFIG_SOC_IMX27 |
198016e1 SH |
97 | # ifdef mxc_cpu_type |
98 | # undef mxc_cpu_type | |
99 | # define mxc_cpu_type __mxc_cpu_type | |
100 | # else | |
101 | # define mxc_cpu_type MXC_CPU_MX27 | |
102 | # endif | |
103 | # define cpu_is_mx27() (mxc_cpu_type == MXC_CPU_MX27) | |
104 | #else | |
105 | # define cpu_is_mx27() (0) | |
f31405cc JB |
106 | #endif |
107 | ||
c23eb89e | 108 | #ifdef CONFIG_SOC_IMX31 |
198016e1 SH |
109 | # ifdef mxc_cpu_type |
110 | # undef mxc_cpu_type | |
111 | # define mxc_cpu_type __mxc_cpu_type | |
112 | # else | |
113 | # define mxc_cpu_type MXC_CPU_MX31 | |
114 | # endif | |
115 | # define cpu_is_mx31() (mxc_cpu_type == MXC_CPU_MX31) | |
116 | #else | |
117 | # define cpu_is_mx31() (0) | |
118 | #endif | |
119 | ||
c23eb89e | 120 | #ifdef CONFIG_SOC_IMX35 |
198016e1 SH |
121 | # ifdef mxc_cpu_type |
122 | # undef mxc_cpu_type | |
123 | # define mxc_cpu_type __mxc_cpu_type | |
124 | # else | |
125 | # define mxc_cpu_type MXC_CPU_MX35 | |
126 | # endif | |
127 | # define cpu_is_mx35() (mxc_cpu_type == MXC_CPU_MX35) | |
128 | #else | |
129 | # define cpu_is_mx35() (0) | |
260a1fd2 HS |
130 | #endif |
131 | ||
76851671 | 132 | #ifdef CONFIG_SOC_IMX51 |
438caa3f AK |
133 | # ifdef mxc_cpu_type |
134 | # undef mxc_cpu_type | |
135 | # define mxc_cpu_type __mxc_cpu_type | |
136 | # else | |
137 | # define mxc_cpu_type MXC_CPU_MX51 | |
138 | # endif | |
139 | # define cpu_is_mx51() (mxc_cpu_type == MXC_CPU_MX51) | |
140 | #else | |
141 | # define cpu_is_mx51() (0) | |
142 | #endif | |
143 | ||
76851671 | 144 | #ifdef CONFIG_SOC_IMX53 |
02226a20 RZ |
145 | # ifdef mxc_cpu_type |
146 | # undef mxc_cpu_type | |
147 | # define mxc_cpu_type __mxc_cpu_type | |
148 | # else | |
149 | # define mxc_cpu_type MXC_CPU_MX53 | |
150 | # endif | |
151 | # define cpu_is_mx53() (mxc_cpu_type == MXC_CPU_MX53) | |
152 | #else | |
153 | # define cpu_is_mx53() (0) | |
154 | #endif | |
155 | ||
64f102b6 | 156 | #ifndef __ASSEMBLY__ |
a82eb09f | 157 | #ifdef CONFIG_SOC_IMX6SL |
9ba64fe3 SG |
158 | static inline bool cpu_is_imx6sl(void) |
159 | { | |
160 | return __mxc_cpu_type == MXC_CPU_IMX6SL; | |
161 | } | |
a82eb09f AB |
162 | #else |
163 | static inline bool cpu_is_imx6sl(void) | |
164 | { | |
165 | return false; | |
166 | } | |
167 | #endif | |
9ba64fe3 | 168 | |
3c03a2fe SG |
169 | static inline bool cpu_is_imx6dl(void) |
170 | { | |
171 | return __mxc_cpu_type == MXC_CPU_IMX6DL; | |
172 | } | |
173 | ||
d9654dce SG |
174 | static inline bool cpu_is_imx6sx(void) |
175 | { | |
176 | return __mxc_cpu_type == MXC_CPU_IMX6SX; | |
177 | } | |
178 | ||
3c03a2fe SG |
179 | static inline bool cpu_is_imx6q(void) |
180 | { | |
181 | return __mxc_cpu_type == MXC_CPU_IMX6Q; | |
182 | } | |
64f102b6 YS |
183 | |
184 | struct cpu_op { | |
185 | u32 cpu_rate; | |
186 | }; | |
187 | ||
010dc8af | 188 | int tzic_enable_wake(void); |
0adf882b | 189 | |
64f102b6 YS |
190 | extern struct cpu_op *(*get_cpu_op)(int *op); |
191 | #endif | |
192 | ||
13cf8df9 | 193 | #define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35()) |
198016e1 SH |
194 | #define cpu_is_mx2() (cpu_is_mx21() || cpu_is_mx27()) |
195 | ||
f304fc42 | 196 | #endif /* __ASM_ARCH_MXC_H__ */ |