[deliverable/linux.git] / arch / arm / mach-imx / pm-imx6.c

/*
 * Copyright 2011-2014 Freescale Semiconductor, Inc.
 * Copyright 2011 Linaro Ltd.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <linux/delay.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/genalloc.h>
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/regmap.h>
#include <linux/suspend.h>
#include <asm/cacheflush.h>
#include <asm/fncpy.h>
#include <asm/proc-fns.h>
#include <asm/suspend.h>
#include <asm/tlb.h>

#include "common.h"
#include "hardware.h"

#define CCR				0x0
#define BM_CCR_WB_COUNT			(0x7 << 16)
#define BM_CCR_RBC_BYPASS_COUNT		(0x3f << 21)
#define BM_CCR_RBC_EN			(0x1 << 27)

#define CLPCR				0x54
#define BP_CLPCR_LPM			0
#define BM_CLPCR_LPM			(0x3 << 0)
#define BM_CLPCR_BYPASS_PMIC_READY	(0x1 << 2)
#define BM_CLPCR_ARM_CLK_DIS_ON_LPM	(0x1 << 5)
#define BM_CLPCR_SBYOS			(0x1 << 6)
#define BM_CLPCR_DIS_REF_OSC		(0x1 << 7)
#define BM_CLPCR_VSTBY			(0x1 << 8)
#define BP_CLPCR_STBY_COUNT		9
#define BM_CLPCR_STBY_COUNT		(0x3 << 9)
#define BM_CLPCR_COSC_PWRDOWN		(0x1 << 11)
#define BM_CLPCR_WB_PER_AT_LPM		(0x1 << 16)
#define BM_CLPCR_WB_CORE_AT_LPM		(0x1 << 17)
#define BM_CLPCR_BYP_MMDC_CH0_LPM_HS	(0x1 << 19)
#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS	(0x1 << 21)
#define BM_CLPCR_MASK_CORE0_WFI		(0x1 << 22)
#define BM_CLPCR_MASK_CORE1_WFI		(0x1 << 23)
#define BM_CLPCR_MASK_CORE2_WFI		(0x1 << 24)
#define BM_CLPCR_MASK_CORE3_WFI		(0x1 << 25)
#define BM_CLPCR_MASK_SCU_IDLE		(0x1 << 26)
#define BM_CLPCR_MASK_L2CC_IDLE		(0x1 << 27)

#define CGPR				0x64
#define BM_CGPR_INT_MEM_CLK_LPM		(0x1 << 17)

#define MX6Q_SUSPEND_OCRAM_SIZE		0x1000
#define MX6_MAX_MMDC_IO_NUM		33

static void __iomem *ccm_base;
static void __iomem *suspend_ocram_base;
static void (*imx6_suspend_in_ocram_fn)(void __iomem *ocram_vbase);

/*
 * suspend ocram space layout:
 * ======================== high address ======================
 *                              .
 *                              .
 *                              .
 *                              ^
 *                              ^
 *                              ^
 *                      imx6_suspend code
 *              PM_INFO structure(imx6_cpu_pm_info)
 * ======================== low address =======================
 */

struct imx6_pm_base {
	phys_addr_t pbase;
	void __iomem *vbase;
};

struct imx6_pm_socdata {
	u32 cpu_type;
	const char *mmdc_compat;
	const char *src_compat;
	const char *iomuxc_compat;
	const char *gpc_compat;
	const u32 mmdc_io_num;
	const u32 *mmdc_io_offset;
};

static const u32 imx6q_mmdc_io_offset[] __initconst = {
	0x5ac, 0x5b4, 0x528, 0x520, /* DQM0 ~ DQM3 */
	0x514, 0x510, 0x5bc, 0x5c4, /* DQM4 ~ DQM7 */
	0x56c, 0x578, 0x588, 0x594, /* CAS, RAS, SDCLK_0, SDCLK_1 */
	0x5a8, 0x5b0, 0x524, 0x51c, /* SDQS0 ~ SDQS3 */
	0x518, 0x50c, 0x5b8, 0x5c0, /* SDQS4 ~ SDQS7 */
	0x784, 0x788, 0x794, 0x79c, /* GPR_B0DS ~ GPR_B3DS */
	0x7a0, 0x7a4, 0x7a8, 0x748, /* GPR_B4DS ~ GPR_B7DS */
	0x59c, 0x5a0, 0x750, 0x774, /* SODT0, SODT1, MODE_CTL, MODE */
	0x74c,			    /* GPR_ADDS */
};

static const u32 imx6dl_mmdc_io_offset[] __initconst = {
	0x470, 0x474, 0x478, 0x47c, /* DQM0 ~ DQM3 */
	0x480, 0x484, 0x488, 0x48c, /* DQM4 ~ DQM7 */
	0x464, 0x490, 0x4ac, 0x4b0, /* CAS, RAS, SDCLK_0, SDCLK_1 */
	0x4bc, 0x4c0, 0x4c4, 0x4c8, /* DRAM_SDQS0 ~ DRAM_SDQS3 */
	0x4cc, 0x4d0, 0x4d4, 0x4d8, /* DRAM_SDQS4 ~ DRAM_SDQS7 */
	0x764, 0x770, 0x778, 0x77c, /* GPR_B0DS ~ GPR_B3DS */
	0x780, 0x784, 0x78c, 0x748, /* GPR_B4DS ~ GPR_B7DS */
	0x4b4, 0x4b8, 0x750, 0x760, /* SODT0, SODT1, MODE_CTL, MODE */
	0x74c,			    /* GPR_ADDS */
};

static const u32 imx6sl_mmdc_io_offset[] __initconst = {
	0x30c, 0x310, 0x314, 0x318, /* DQM0 ~ DQM3 */
	0x5c4, 0x5cc, 0x5d4, 0x5d8, /* GPR_B0DS ~ GPR_B3DS */
	0x300, 0x31c, 0x338, 0x5ac, /* CAS, RAS, SDCLK_0, GPR_ADDS */
	0x33c, 0x340, 0x5b0, 0x5c0, /* SODT0, SODT1, MODE_CTL, MODE */
	0x330, 0x334, 0x320,        /* SDCKE0, SDCKE1, RESET */
};

static const u32 imx6sx_mmdc_io_offset[] __initconst = {
	0x2ec, 0x2f0, 0x2f4, 0x2f8, /* DQM0 ~ DQM3 */
	0x60c, 0x610, 0x61c, 0x620, /* GPR_B0DS ~ GPR_B3DS */
	0x300, 0x2fc, 0x32c, 0x5f4, /* CAS, RAS, SDCLK_0, GPR_ADDS */
	0x310, 0x314, 0x5f8, 0x608, /* SODT0, SODT1, MODE_CTL, MODE */
	0x330, 0x334, 0x338, 0x33c, /* SDQS0 ~ SDQS3 */
};

static const struct imx6_pm_socdata imx6q_pm_data __initconst = {
	.cpu_type = MXC_CPU_IMX6Q,
	.mmdc_compat = "fsl,imx6q-mmdc",
	.src_compat = "fsl,imx6q-src",
	.iomuxc_compat = "fsl,imx6q-iomuxc",
	.gpc_compat = "fsl,imx6q-gpc",
	.mmdc_io_num = ARRAY_SIZE(imx6q_mmdc_io_offset),
	.mmdc_io_offset = imx6q_mmdc_io_offset,
};

static const struct imx6_pm_socdata imx6dl_pm_data __initconst = {
	.cpu_type = MXC_CPU_IMX6DL,
	.mmdc_compat = "fsl,imx6q-mmdc",
	.src_compat = "fsl,imx6q-src",
	.iomuxc_compat = "fsl,imx6dl-iomuxc",
	.gpc_compat = "fsl,imx6q-gpc",
	.mmdc_io_num = ARRAY_SIZE(imx6dl_mmdc_io_offset),
	.mmdc_io_offset = imx6dl_mmdc_io_offset,
};

static const struct imx6_pm_socdata imx6sl_pm_data __initconst = {
	.cpu_type = MXC_CPU_IMX6SL,
	.mmdc_compat = "fsl,imx6sl-mmdc",
	.src_compat = "fsl,imx6sl-src",
	.iomuxc_compat = "fsl,imx6sl-iomuxc",
	.gpc_compat = "fsl,imx6sl-gpc",
	.mmdc_io_num = ARRAY_SIZE(imx6sl_mmdc_io_offset),
	.mmdc_io_offset = imx6sl_mmdc_io_offset,
};

static const struct imx6_pm_socdata imx6sx_pm_data __initconst = {
	.cpu_type = MXC_CPU_IMX6SX,
	.mmdc_compat = "fsl,imx6sx-mmdc",
	.src_compat = "fsl,imx6sx-src",
	.iomuxc_compat = "fsl,imx6sx-iomuxc",
	.gpc_compat = "fsl,imx6sx-gpc",
	.mmdc_io_num = ARRAY_SIZE(imx6sx_mmdc_io_offset),
	.mmdc_io_offset = imx6sx_mmdc_io_offset,
};

/*
 * This structure is for passing necessary data for low level ocram
 * suspend code(arch/arm/mach-imx/suspend-imx6.S), if this struct
 * definition is changed, the offset definition in
 * arch/arm/mach-imx/suspend-imx6.S must be also changed accordingly,
 * otherwise, the suspend to ocram function will be broken!
 */
struct imx6_cpu_pm_info {
	phys_addr_t pbase; /* The physical address of pm_info. */
	phys_addr_t resume_addr; /* The physical resume address for asm code */
	u32 cpu_type;
	u32 pm_info_size; /* Size of pm_info. */
	struct imx6_pm_base mmdc_base;
	struct imx6_pm_base src_base;
	struct imx6_pm_base iomuxc_base;
	struct imx6_pm_base ccm_base;
	struct imx6_pm_base gpc_base;
	struct imx6_pm_base l2_base;
	u32 mmdc_io_num; /* Number of MMDC IOs which need saved/restored. */
	u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */
} __aligned(8);

void imx6q_set_int_mem_clk_lpm(bool enable)
{
	u32 val = readl_relaxed(ccm_base + CGPR);

	val &= ~BM_CGPR_INT_MEM_CLK_LPM;
	if (enable)
		val |= BM_CGPR_INT_MEM_CLK_LPM;
	writel_relaxed(val, ccm_base + CGPR);
}

static void imx6q_enable_rbc(bool enable)
{
	u32 val;

	/*
	 * need to mask all interrupts in GPC before
	 * operating RBC configurations
	 */
	imx_gpc_mask_all();

	/* configure RBC enable bit */
	val = readl_relaxed(ccm_base + CCR);
	val &= ~BM_CCR_RBC_EN;
	val |= enable ? BM_CCR_RBC_EN : 0;
	writel_relaxed(val, ccm_base + CCR);

	/* configure RBC count */
	val = readl_relaxed(ccm_base + CCR);
	val &= ~BM_CCR_RBC_BYPASS_COUNT;
	val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0;
	writel(val, ccm_base + CCR);

	/*
	 * need to delay at least 2 cycles of CKIL(32K)
	 * due to hardware design requirement, which is
	 * ~61us, here we use 65us for safe
	 */
	udelay(65);

	/* restore GPC interrupt mask settings */
	imx_gpc_restore_all();
}

static void imx6q_enable_wb(bool enable)
{
	u32 val;

	/* configure well bias enable bit */
	val = readl_relaxed(ccm_base + CLPCR);
	val &= ~BM_CLPCR_WB_PER_AT_LPM;
	val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0;
	writel_relaxed(val, ccm_base + CLPCR);

	/* configure well bias count */
	val = readl_relaxed(ccm_base + CCR);
	val &= ~BM_CCR_WB_COUNT;
	val |= enable ? BM_CCR_WB_COUNT : 0;
	writel_relaxed(val, ccm_base + CCR);
}

int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
{
	struct irq_data *iomuxc_irq_data = irq_get_irq_data(32);
	u32 val = readl_relaxed(ccm_base + CLPCR);

	val &= ~BM_CLPCR_LPM;
	switch (mode) {
	case WAIT_CLOCKED:
		break;
	case WAIT_UNCLOCKED:
		val |= 0x1 << BP_CLPCR_LPM;
		val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM;
		break;
	case STOP_POWER_ON:
		val |= 0x2 << BP_CLPCR_LPM;
		val &= ~BM_CLPCR_VSTBY;
		val &= ~BM_CLPCR_SBYOS;
		if (cpu_is_imx6sl())
			val |= BM_CLPCR_BYPASS_PMIC_READY;
		if (cpu_is_imx6sl() || cpu_is_imx6sx())
			val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
		else
			val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
		break;
	case WAIT_UNCLOCKED_POWER_OFF:
		val |= 0x1 << BP_CLPCR_LPM;
		val &= ~BM_CLPCR_VSTBY;
		val &= ~BM_CLPCR_SBYOS;
		break;
	case STOP_POWER_OFF:
		val |= 0x2 << BP_CLPCR_LPM;
		val |= 0x3 << BP_CLPCR_STBY_COUNT;
		val |= BM_CLPCR_VSTBY;
		val |= BM_CLPCR_SBYOS;
		if (cpu_is_imx6sl())
			val |= BM_CLPCR_BYPASS_PMIC_READY;
		if (cpu_is_imx6sl() || cpu_is_imx6sx())
			val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
		else
			val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
		break;
	default:
		return -EINVAL;
	}

	/*
	 * ERR007265: CCM: When improper low-power sequence is used,
	 * the SoC enters low power mode before the ARM core executes WFI.
	 *
	 * Software workaround:
	 * 1) Software should trigger IRQ #32 (IOMUX) to be always pending
	 *    by setting IOMUX_GPR1_GINT.
	 * 2) Software should then unmask IRQ #32 in GPC before setting CCM
	 *    Low-Power mode.
	 * 3) Software should mask IRQ #32 right after CCM Low-Power mode
	 *    is set (set bits 0-1 of CCM_CLPCR).
	 */
	imx_gpc_irq_unmask(iomuxc_irq_data);
	writel_relaxed(val, ccm_base + CLPCR);
	imx_gpc_irq_mask(iomuxc_irq_data);

	return 0;
}

static int imx6q_suspend_finish(unsigned long val)
{
	if (!imx6_suspend_in_ocram_fn) {
		cpu_do_idle();
	} else {
		/*
		 * call low level suspend function in ocram,
		 * as we need to float DDR IO.
		 */
		local_flush_tlb_all();
		imx6_suspend_in_ocram_fn(suspend_ocram_base);
	}

	return 0;
}

static int imx6q_pm_enter(suspend_state_t state)
{
	switch (state) {
	case PM_SUSPEND_STANDBY:
		imx6q_set_lpm(STOP_POWER_ON);
		imx6q_set_int_mem_clk_lpm(true);
		imx_gpc_pre_suspend(false);
		if (cpu_is_imx6sl())
			imx6sl_set_wait_clk(true);
		/* Zzz ... */
		cpu_do_idle();
		if (cpu_is_imx6sl())
			imx6sl_set_wait_clk(false);
		imx_gpc_post_resume();
		imx6q_set_lpm(WAIT_CLOCKED);
		break;
	case PM_SUSPEND_MEM:
		imx6q_set_lpm(STOP_POWER_OFF);
		imx6q_set_int_mem_clk_lpm(false);
		imx6q_enable_wb(true);
		/*
		 * For suspend into ocram, asm code already take care of
		 * RBC setting, so we do NOT need to do that here.
		 */
		if (!imx6_suspend_in_ocram_fn)
			imx6q_enable_rbc(true);
		imx_gpc_pre_suspend(true);
		imx_anatop_pre_suspend();
		imx_set_cpu_jump(0, v7_cpu_resume);
		/* Zzz ... */
		cpu_suspend(0, imx6q_suspend_finish);
		if (cpu_is_imx6q() || cpu_is_imx6dl())
			imx_smp_prepare();
		imx_anatop_post_resume();
		imx_gpc_post_resume();
		imx6q_enable_rbc(false);
		imx6q_enable_wb(false);
		imx6q_set_int_mem_clk_lpm(true);
		imx6q_set_lpm(WAIT_CLOCKED);
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

static int imx6q_pm_valid(suspend_state_t state)
{
	return (state == PM_SUSPEND_STANDBY || state == PM_SUSPEND_MEM);
}

static const struct platform_suspend_ops imx6q_pm_ops = {
	.enter = imx6q_pm_enter,
	.valid = imx6q_pm_valid,
};

void __init imx6q_pm_set_ccm_base(void __iomem *base)
{
	ccm_base = base;
}

static int __init imx6_pm_get_base(struct imx6_pm_base *base,
				const char *compat)
{
	struct device_node *node;
	struct resource res;
	int ret = 0;

	node = of_find_compatible_node(NULL, NULL, compat);
	if (!node) {
		ret = -ENODEV;
		goto out;
	}

	ret = of_address_to_resource(node, 0, &res);
	if (ret)
		goto put_node;

	base->pbase = res.start;
	base->vbase = ioremap(res.start, resource_size(&res));
	if (!base->vbase)
		ret = -ENOMEM;

put_node:
	of_node_put(node);
out:
	return ret;
}

static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata)
{
	phys_addr_t ocram_pbase;
	struct device_node *node;
	struct platform_device *pdev;
	struct imx6_cpu_pm_info *pm_info;
	struct gen_pool *ocram_pool;
	unsigned long ocram_base;
	int i, ret = 0;
	const u32 *mmdc_offset_array;

	suspend_set_ops(&imx6q_pm_ops);

	if (!socdata) {
		pr_warn("%s: invalid argument!\n", __func__);
		return -EINVAL;
	}

	node = of_find_compatible_node(NULL, NULL, "mmio-sram");
	if (!node) {
		pr_warn("%s: failed to find ocram node!\n", __func__);
		return -ENODEV;
	}

	pdev = of_find_device_by_node(node);
	if (!pdev) {
		pr_warn("%s: failed to find ocram device!\n", __func__);
		ret = -ENODEV;
		goto put_node;
	}

	ocram_pool = dev_get_gen_pool(&pdev->dev);
	if (!ocram_pool) {
		pr_warn("%s: ocram pool unavailable!\n", __func__);
		ret = -ENODEV;
		goto put_node;
	}

	ocram_base = gen_pool_alloc(ocram_pool, MX6Q_SUSPEND_OCRAM_SIZE);
	if (!ocram_base) {
		pr_warn("%s: unable to alloc ocram!\n", __func__);
		ret = -ENOMEM;
		goto put_node;
	}

	ocram_pbase = gen_pool_virt_to_phys(ocram_pool, ocram_base);

	suspend_ocram_base = __arm_ioremap_exec(ocram_pbase,
		MX6Q_SUSPEND_OCRAM_SIZE, false);

	pm_info = suspend_ocram_base;
	pm_info->pbase = ocram_pbase;
	pm_info->resume_addr = virt_to_phys(v7_cpu_resume);
	pm_info->pm_info_size = sizeof(*pm_info);

	/*
	 * ccm physical address is not used by asm code currently,
	 * so get ccm virtual address directly, as we already have
	 * it from ccm driver.
	 */
	pm_info->ccm_base.vbase = ccm_base;

	ret = imx6_pm_get_base(&pm_info->mmdc_base, socdata->mmdc_compat);
	if (ret) {
		pr_warn("%s: failed to get mmdc base %d!\n", __func__, ret);
		goto put_node;
	}

	ret = imx6_pm_get_base(&pm_info->src_base, socdata->src_compat);
	if (ret) {
		pr_warn("%s: failed to get src base %d!\n", __func__, ret);
		goto src_map_failed;
	}

	ret = imx6_pm_get_base(&pm_info->iomuxc_base, socdata->iomuxc_compat);
	if (ret) {
		pr_warn("%s: failed to get iomuxc base %d!\n", __func__, ret);
		goto iomuxc_map_failed;
	}

	ret = imx6_pm_get_base(&pm_info->gpc_base, socdata->gpc_compat);
	if (ret) {
		pr_warn("%s: failed to get gpc base %d!\n", __func__, ret);
		goto gpc_map_failed;
	}

	ret = imx6_pm_get_base(&pm_info->l2_base, "arm,pl310-cache");
	if (ret) {
		pr_warn("%s: failed to get pl310-cache base %d!\n",
			__func__, ret);
		goto pl310_cache_map_failed;
	}

	pm_info->cpu_type = socdata->cpu_type;
	pm_info->mmdc_io_num = socdata->mmdc_io_num;
	mmdc_offset_array = socdata->mmdc_io_offset;

	for (i = 0; i < pm_info->mmdc_io_num; i++) {
		pm_info->mmdc_io_val[i][0] =
			mmdc_offset_array[i];
		pm_info->mmdc_io_val[i][1] =
			readl_relaxed(pm_info->iomuxc_base.vbase +
			mmdc_offset_array[i]);
	}

	imx6_suspend_in_ocram_fn = fncpy(
		suspend_ocram_base + sizeof(*pm_info),
		&imx6_suspend,
		MX6Q_SUSPEND_OCRAM_SIZE - sizeof(*pm_info));

	goto put_node;

pl310_cache_map_failed:
	iounmap(&pm_info->gpc_base.vbase);
gpc_map_failed:
	iounmap(&pm_info->iomuxc_base.vbase);
iomuxc_map_failed:
	iounmap(&pm_info->src_base.vbase);
src_map_failed:
	iounmap(&pm_info->mmdc_base.vbase);
put_node:
	of_node_put(node);

	return ret;
}

static void __init imx6_pm_common_init(const struct imx6_pm_socdata
					*socdata)
{
	struct regmap *gpr;
	int ret;

	WARN_ON(!ccm_base);

	if (IS_ENABLED(CONFIG_SUSPEND)) {
		ret = imx6q_suspend_init(socdata);
		if (ret)
			pr_warn("%s: No DDR LPM support with suspend %d!\n",
				__func__, ret);
	}

	/*
	 * This is for SW workaround step #1 of ERR007265, see comments
	 * in imx6q_set_lpm for details of this errata.
	 * Force IOMUXC irq pending, so that the interrupt to GPC can be
	 * used to deassert dsm_request signal when the signal gets
	 * asserted unexpectedly.
	 */
	gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
	if (!IS_ERR(gpr))
		regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_GINT,
				   IMX6Q_GPR1_GINT);
}

void __init imx6q_pm_init(void)
{
	imx6_pm_common_init(&imx6q_pm_data);
}

void __init imx6dl_pm_init(void)
{
	imx6_pm_common_init(&imx6dl_pm_data);
}

void __init imx6sl_pm_init(void)
{
	imx6_pm_common_init(&imx6sl_pm_data);
}

void __init imx6sx_pm_init(void)
{
	imx6_pm_common_init(&imx6sx_pm_data);
}
Commit	Line	Data
a1f1c7ef	1	/*
df595746	2	* Copyright 2011-2014 Freescale Semiconductor, Inc.
a1f1c7ef SG	3	* Copyright 2011 Linaro Ltd.
	4	*
	5	* The code contained herein is licensed under the GNU General Public
	6	* License. You may obtain a copy of the GNU General Public License
	7	* Version 2 or later at the following locations:
	8	*
	9	* http://www.opensource.org/licenses/gpl-license.html
	10	* http://www.gnu.org/copyleft/gpl.html
	11	*/
	12
9e8147bb	13	#include <linux/delay.h>
a1f1c7ef SG	14	#include <linux/init.h>
a1f1c7ef SG	15	#include <linux/io.h>
d48866fe	16	#include <linux/irq.h>
df595746	17	#include <linux/genalloc.h>
d48866fe SG	18	#include <linux/mfd/syscon.h>
d48866fe SG	19	#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
a1f1c7ef	20	#include <linux/of.h>
9e8147bb	21	#include <linux/of_address.h>
df595746	22	#include <linux/of_platform.h>
d48866fe	23	#include <linux/regmap.h>
a1f1c7ef SG	24	#include <linux/suspend.h>
a1f1c7ef SG	25	#include <asm/cacheflush.h>
df595746	26	#include <asm/fncpy.h>
a1f1c7ef SG	27	#include <asm/proc-fns.h>
a1f1c7ef SG	28	#include <asm/suspend.h>
df595746	29	#include <asm/tlb.h>
a1f1c7ef	30
e3372474	31	#include "common.h"
50f2de61	32	#include "hardware.h"
e3372474	33
9e8147bb SG	34	#define CCR 0x0
	35	#define BM_CCR_WB_COUNT (0x7 << 16)
	36	#define BM_CCR_RBC_BYPASS_COUNT (0x3f << 21)
	37	#define BM_CCR_RBC_EN (0x1 << 27)
	38
	39	#define CLPCR 0x54
	40	#define BP_CLPCR_LPM 0
	41	#define BM_CLPCR_LPM (0x3 << 0)
	42	#define BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2)
	43	#define BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
	44	#define BM_CLPCR_SBYOS (0x1 << 6)
	45	#define BM_CLPCR_DIS_REF_OSC (0x1 << 7)
	46	#define BM_CLPCR_VSTBY (0x1 << 8)
	47	#define BP_CLPCR_STBY_COUNT 9
	48	#define BM_CLPCR_STBY_COUNT (0x3 << 9)
	49	#define BM_CLPCR_COSC_PWRDOWN (0x1 << 11)
	50	#define BM_CLPCR_WB_PER_AT_LPM (0x1 << 16)
	51	#define BM_CLPCR_WB_CORE_AT_LPM (0x1 << 17)
	52	#define BM_CLPCR_BYP_MMDC_CH0_LPM_HS (0x1 << 19)
	53	#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS (0x1 << 21)
	54	#define BM_CLPCR_MASK_CORE0_WFI (0x1 << 22)
	55	#define BM_CLPCR_MASK_CORE1_WFI (0x1 << 23)
	56	#define BM_CLPCR_MASK_CORE2_WFI (0x1 << 24)
	57	#define BM_CLPCR_MASK_CORE3_WFI (0x1 << 25)
	58	#define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26)
	59	#define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27)
	60
	61	#define CGPR 0x64
fa6be65e	62	#define BM_CGPR_INT_MEM_CLK_LPM (0x1 << 17)
9e8147bb	63
df595746 AH	64	#define MX6Q_SUSPEND_OCRAM_SIZE 0x1000
	65	#define MX6_MAX_MMDC_IO_NUM 33
	66
9e8147bb	67	static void __iomem *ccm_base;
df595746 AH	68	static void __iomem *suspend_ocram_base;
	69	static void (imx6_suspend_in_ocram_fn)(void __iomem ocram_vbase);
	70
	71	/*
	72	* suspend ocram space layout:
	73	* ======================== high address ======================
	74	* .
	75	* .
	76	* .
	77	* ^
	78	* ^
	79	* ^
	80	* imx6_suspend code
	81	* PM_INFO structure(imx6_cpu_pm_info)
	82	* ======================== low address =======================
	83	*/
	84
	85	struct imx6_pm_base {
	86	phys_addr_t pbase;
	87	void __iomem *vbase;
	88	};
	89
	90	struct imx6_pm_socdata {
	91	u32 cpu_type;
	92	const char *mmdc_compat;
	93	const char *src_compat;
	94	const char *iomuxc_compat;
	95	const char *gpc_compat;
	96	const u32 mmdc_io_num;
	97	const u32 *mmdc_io_offset;
	98	};
	99
	100	static const u32 imx6q_mmdc_io_offset[] __initconst = {
	101	0x5ac, 0x5b4, 0x528, 0x520, /* DQM0 ~ DQM3 */
	102	0x514, 0x510, 0x5bc, 0x5c4, /* DQM4 ~ DQM7 */
	103	0x56c, 0x578, 0x588, 0x594, /* CAS, RAS, SDCLK_0, SDCLK_1 */
	104	0x5a8, 0x5b0, 0x524, 0x51c, /* SDQS0 ~ SDQS3 */
	105	0x518, 0x50c, 0x5b8, 0x5c0, /* SDQS4 ~ SDQS7 */
	106	0x784, 0x788, 0x794, 0x79c, /* GPR_B0DS ~ GPR_B3DS */
	107	0x7a0, 0x7a4, 0x7a8, 0x748, /* GPR_B4DS ~ GPR_B7DS */
	108	0x59c, 0x5a0, 0x750, 0x774, /* SODT0, SODT1, MODE_CTL, MODE */
	109	0x74c, /* GPR_ADDS */
	110	};
	111
da9e9261 AH	112	static const u32 imx6dl_mmdc_io_offset[] __initconst = {
	113	0x470, 0x474, 0x478, 0x47c, /* DQM0 ~ DQM3 */
	114	0x480, 0x484, 0x488, 0x48c, /* DQM4 ~ DQM7 */
	115	0x464, 0x490, 0x4ac, 0x4b0, /* CAS, RAS, SDCLK_0, SDCLK_1 */
	116	0x4bc, 0x4c0, 0x4c4, 0x4c8, /* DRAM_SDQS0 ~ DRAM_SDQS3 */
	117	0x4cc, 0x4d0, 0x4d4, 0x4d8, /* DRAM_SDQS4 ~ DRAM_SDQS7 */
	118	0x764, 0x770, 0x778, 0x77c, /* GPR_B0DS ~ GPR_B3DS */
	119	0x780, 0x784, 0x78c, 0x748, /* GPR_B4DS ~ GPR_B7DS */
	120	0x4b4, 0x4b8, 0x750, 0x760, /* SODT0, SODT1, MODE_CTL, MODE */
	121	0x74c, /* GPR_ADDS */
	122	};
	123
64b08681 AH	124	static const u32 imx6sl_mmdc_io_offset[] __initconst = {
	125	0x30c, 0x310, 0x314, 0x318, /* DQM0 ~ DQM3 */
	126	0x5c4, 0x5cc, 0x5d4, 0x5d8, /* GPR_B0DS ~ GPR_B3DS */
	127	0x300, 0x31c, 0x338, 0x5ac, /* CAS, RAS, SDCLK_0, GPR_ADDS */
	128	0x33c, 0x340, 0x5b0, 0x5c0, /* SODT0, SODT1, MODE_CTL, MODE */
	129	0x330, 0x334, 0x320, /* SDCKE0, SDCKE1, RESET */
	130	};
	131
ff843d62 AH	132	static const u32 imx6sx_mmdc_io_offset[] __initconst = {
	133	0x2ec, 0x2f0, 0x2f4, 0x2f8, /* DQM0 ~ DQM3 */
	134	0x60c, 0x610, 0x61c, 0x620, /* GPR_B0DS ~ GPR_B3DS */
	135	0x300, 0x2fc, 0x32c, 0x5f4, /* CAS, RAS, SDCLK_0, GPR_ADDS */
	136	0x310, 0x314, 0x5f8, 0x608, /* SODT0, SODT1, MODE_CTL, MODE */
	137	0x330, 0x334, 0x338, 0x33c, /* SDQS0 ~ SDQS3 */
	138	};
	139
df595746 AH	140	static const struct imx6_pm_socdata imx6q_pm_data __initconst = {
	141	.cpu_type = MXC_CPU_IMX6Q,
	142	.mmdc_compat = "fsl,imx6q-mmdc",
	143	.src_compat = "fsl,imx6q-src",
	144	.iomuxc_compat = "fsl,imx6q-iomuxc",
	145	.gpc_compat = "fsl,imx6q-gpc",
	146	.mmdc_io_num = ARRAY_SIZE(imx6q_mmdc_io_offset),
	147	.mmdc_io_offset = imx6q_mmdc_io_offset,
	148	};
	149
da9e9261 AH	150	static const struct imx6_pm_socdata imx6dl_pm_data __initconst = {
	151	.cpu_type = MXC_CPU_IMX6DL,
	152	.mmdc_compat = "fsl,imx6q-mmdc",
	153	.src_compat = "fsl,imx6q-src",
	154	.iomuxc_compat = "fsl,imx6dl-iomuxc",
	155	.gpc_compat = "fsl,imx6q-gpc",
	156	.mmdc_io_num = ARRAY_SIZE(imx6dl_mmdc_io_offset),
	157	.mmdc_io_offset = imx6dl_mmdc_io_offset,
	158	};
	159
64b08681 AH	160	static const struct imx6_pm_socdata imx6sl_pm_data __initconst = {
	161	.cpu_type = MXC_CPU_IMX6SL,
	162	.mmdc_compat = "fsl,imx6sl-mmdc",
	163	.src_compat = "fsl,imx6sl-src",
	164	.iomuxc_compat = "fsl,imx6sl-iomuxc",
	165	.gpc_compat = "fsl,imx6sl-gpc",
	166	.mmdc_io_num = ARRAY_SIZE(imx6sl_mmdc_io_offset),
	167	.mmdc_io_offset = imx6sl_mmdc_io_offset,
	168	};
	169
ff843d62 AH	170	static const struct imx6_pm_socdata imx6sx_pm_data __initconst = {
	171	.cpu_type = MXC_CPU_IMX6SX,
	172	.mmdc_compat = "fsl,imx6sx-mmdc",
	173	.src_compat = "fsl,imx6sx-src",
	174	.iomuxc_compat = "fsl,imx6sx-iomuxc",
	175	.gpc_compat = "fsl,imx6sx-gpc",
	176	.mmdc_io_num = ARRAY_SIZE(imx6sx_mmdc_io_offset),
	177	.mmdc_io_offset = imx6sx_mmdc_io_offset,
	178	};
	179
df595746 AH	180	/*
	181	* This structure is for passing necessary data for low level ocram
	182	* suspend code(arch/arm/mach-imx/suspend-imx6.S), if this struct
	183	* definition is changed, the offset definition in
	184	* arch/arm/mach-imx/suspend-imx6.S must be also changed accordingly,
	185	* otherwise, the suspend to ocram function will be broken!
	186	*/
	187	struct imx6_cpu_pm_info {
	188	phys_addr_t pbase; /* The physical address of pm_info. */
	189	phys_addr_t resume_addr; /* The physical resume address for asm code */
	190	u32 cpu_type;
	191	u32 pm_info_size; /* Size of pm_info. */
	192	struct imx6_pm_base mmdc_base;
	193	struct imx6_pm_base src_base;
	194	struct imx6_pm_base iomuxc_base;
	195	struct imx6_pm_base ccm_base;
	196	struct imx6_pm_base gpc_base;
	197	struct imx6_pm_base l2_base;
	198	u32 mmdc_io_num; /* Number of MMDC IOs which need saved/restored. */
	199	u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */
	200	} __aligned(8);
9e8147bb	201
dfea953a	202	void imx6q_set_int_mem_clk_lpm(bool enable)
9e8147bb SG	203	{
	204	u32 val = readl_relaxed(ccm_base + CGPR);
	205
dfea953a AH	206	val &= ~BM_CGPR_INT_MEM_CLK_LPM;
	207	if (enable)
	208	val \|= BM_CGPR_INT_MEM_CLK_LPM;
9e8147bb SG	209	writel_relaxed(val, ccm_base + CGPR);
	210	}
	211
	212	static void imx6q_enable_rbc(bool enable)
	213	{
	214	u32 val;
9e8147bb	215
9e8147bb SG	216	/*
	217	* need to mask all interrupts in GPC before
	218	* operating RBC configurations
	219	*/
	220	imx_gpc_mask_all();
	221
	222	/* configure RBC enable bit */
	223	val = readl_relaxed(ccm_base + CCR);
	224	val &= ~BM_CCR_RBC_EN;
	225	val \|= enable ? BM_CCR_RBC_EN : 0;
	226	writel_relaxed(val, ccm_base + CCR);
	227
	228	/* configure RBC count */
	229	val = readl_relaxed(ccm_base + CCR);
	230	val &= ~BM_CCR_RBC_BYPASS_COUNT;
	231	val \|= enable ? BM_CCR_RBC_BYPASS_COUNT : 0;
	232	writel(val, ccm_base + CCR);
	233
	234	/*
	235	* need to delay at least 2 cycles of CKIL(32K)
	236	* due to hardware design requirement, which is
	237	* ~61us, here we use 65us for safe
	238	*/
	239	udelay(65);
	240
	241	/* restore GPC interrupt mask settings */
	242	imx_gpc_restore_all();
9e8147bb SG	243	}
	244
	245	static void imx6q_enable_wb(bool enable)
	246	{
	247	u32 val;
9e8147bb SG	248
	249	/* configure well bias enable bit */
	250	val = readl_relaxed(ccm_base + CLPCR);
	251	val &= ~BM_CLPCR_WB_PER_AT_LPM;
	252	val \|= enable ? BM_CLPCR_WB_PER_AT_LPM : 0;
	253	writel_relaxed(val, ccm_base + CLPCR);
	254
	255	/* configure well bias count */
	256	val = readl_relaxed(ccm_base + CCR);
	257	val &= ~BM_CCR_WB_COUNT;
	258	val \|= enable ? BM_CCR_WB_COUNT : 0;
	259	writel_relaxed(val, ccm_base + CCR);
9e8147bb SG	260	}
	261
	262	int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
	263	{
ff050ad1	264	struct irq_data *iomuxc_irq_data = irq_get_irq_data(32);
9e8147bb SG	265	u32 val = readl_relaxed(ccm_base + CLPCR);
	266
	267	val &= ~BM_CLPCR_LPM;
	268	switch (mode) {
	269	case WAIT_CLOCKED:
9e8147bb SG	270	break;
	271	case WAIT_UNCLOCKED:
	272	val \|= 0x1 << BP_CLPCR_LPM;
	273	val \|= BM_CLPCR_ARM_CLK_DIS_ON_LPM;
	274	break;
	275	case STOP_POWER_ON:
	276	val \|= 0x2 << BP_CLPCR_LPM;
80c0ecdc AH	277	val &= ~BM_CLPCR_VSTBY;
	278	val &= ~BM_CLPCR_SBYOS;
	279	if (cpu_is_imx6sl())
	280	val \|= BM_CLPCR_BYPASS_PMIC_READY;
	281	if (cpu_is_imx6sl() \|\| cpu_is_imx6sx())
	282	val \|= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
	283	else
	284	val \|= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
9e8147bb SG	285	break;
	286	case WAIT_UNCLOCKED_POWER_OFF:
	287	val \|= 0x1 << BP_CLPCR_LPM;
	288	val &= ~BM_CLPCR_VSTBY;
	289	val &= ~BM_CLPCR_SBYOS;
	290	break;
	291	case STOP_POWER_OFF:
	292	val \|= 0x2 << BP_CLPCR_LPM;
	293	val \|= 0x3 << BP_CLPCR_STBY_COUNT;
	294	val \|= BM_CLPCR_VSTBY;
	295	val \|= BM_CLPCR_SBYOS;
ff843d62	296	if (cpu_is_imx6sl())
9ba64fe3	297	val \|= BM_CLPCR_BYPASS_PMIC_READY;
ff843d62	298	if (cpu_is_imx6sl() \|\| cpu_is_imx6sx())
9ba64fe3	299	val \|= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
ff843d62	300	else
9ba64fe3	301	val \|= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
9e8147bb SG	302	break;
	303	default:
	304	return -EINVAL;
	305	}
	306
d48866fe	307	/*
48c95841 AH	308	* ERR007265: CCM: When improper low-power sequence is used,
	309	* the SoC enters low power mode before the ARM core executes WFI.
	310	*
	311	* Software workaround:
	312	* 1) Software should trigger IRQ #32 (IOMUX) to be always pending
	313	* by setting IOMUX_GPR1_GINT.
	314	* 2) Software should then unmask IRQ #32 in GPC before setting CCM
	315	* Low-Power mode.
	316	* 3) Software should mask IRQ #32 right after CCM Low-Power mode
	317	* is set (set bits 0-1 of CCM_CLPCR).
d48866fe	318	*/
ff050ad1	319	imx_gpc_irq_unmask(iomuxc_irq_data);
9e8147bb	320	writel_relaxed(val, ccm_base + CLPCR);
ff050ad1	321	imx_gpc_irq_mask(iomuxc_irq_data);
9e8147bb SG	322
	323	return 0;
	324	}
	325
a1f1c7ef SG	326	static int imx6q_suspend_finish(unsigned long val)
a1f1c7ef SG	327	{
df595746 AH	328	if (!imx6_suspend_in_ocram_fn) {
	329	cpu_do_idle();
	330	} else {
	331	/*
	332	* call low level suspend function in ocram,
	333	* as we need to float DDR IO.
	334	*/
	335	local_flush_tlb_all();
	336	imx6_suspend_in_ocram_fn(suspend_ocram_base);
	337	}
	338
a1f1c7ef SG	339	return 0;
	340	}
	341
	342	static int imx6q_pm_enter(suspend_state_t state)
	343	{
	344	switch (state) {
80c0ecdc AH	345	case PM_SUSPEND_STANDBY:
	346	imx6q_set_lpm(STOP_POWER_ON);
	347	imx6q_set_int_mem_clk_lpm(true);
	348	imx_gpc_pre_suspend(false);
	349	if (cpu_is_imx6sl())
	350	imx6sl_set_wait_clk(true);
	351	/* Zzz ... */
	352	cpu_do_idle();
	353	if (cpu_is_imx6sl())
	354	imx6sl_set_wait_clk(false);
	355	imx_gpc_post_resume();
	356	imx6q_set_lpm(WAIT_CLOCKED);
	357	break;
a1f1c7ef SG	358	case PM_SUSPEND_MEM:
a1f1c7ef SG	359	imx6q_set_lpm(STOP_POWER_OFF);
dfea953a	360	imx6q_set_int_mem_clk_lpm(false);
1d674a73	361	imx6q_enable_wb(true);
df595746 AH	362	/*
	363	* For suspend into ocram, asm code already take care of
	364	* RBC setting, so we do NOT need to do that here.
	365	*/
	366	if (!imx6_suspend_in_ocram_fn)
	367	imx6q_enable_rbc(true);
80c0ecdc	368	imx_gpc_pre_suspend(true);
e95dddb3	369	imx_anatop_pre_suspend();
a1f1c7ef SG	370	imx_set_cpu_jump(0, v7_cpu_resume);
	371	/* Zzz ... */
	372	cpu_suspend(0, imx6q_suspend_finish);
9ba64fe3 SG	373	if (cpu_is_imx6q() \|\| cpu_is_imx6dl())
9ba64fe3 SG	374	imx_smp_prepare();
e95dddb3	375	imx_anatop_post_resume();
a1f1c7ef	376	imx_gpc_post_resume();
1d674a73 SG	377	imx6q_enable_rbc(false);
1d674a73 SG	378	imx6q_enable_wb(false);
dfea953a	379	imx6q_set_int_mem_clk_lpm(true);
83ae2098	380	imx6q_set_lpm(WAIT_CLOCKED);
a1f1c7ef SG	381	break;
	382	default:
	383	return -EINVAL;
	384	}
	385
	386	return 0;
	387	}
	388
80c0ecdc AH	389	static int imx6q_pm_valid(suspend_state_t state)
	390	{
	391	return (state == PM_SUSPEND_STANDBY \|\| state == PM_SUSPEND_MEM);
	392	}
	393
a1f1c7ef SG	394	static const struct platform_suspend_ops imx6q_pm_ops = {
a1f1c7ef SG	395	.enter = imx6q_pm_enter,
80c0ecdc	396	.valid = imx6q_pm_valid,
a1f1c7ef SG	397	};
a1f1c7ef SG	398
9e8147bb SG	399	void __init imx6q_pm_set_ccm_base(void __iomem *base)
	400	{
	401	ccm_base = base;
	402	}
	403
df595746 AH	404	static int __init imx6_pm_get_base(struct imx6_pm_base *base,
	405	const char *compat)
	406	{
	407	struct device_node *node;
	408	struct resource res;
	409	int ret = 0;
	410
	411	node = of_find_compatible_node(NULL, NULL, compat);
	412	if (!node) {
	413	ret = -ENODEV;
	414	goto out;
	415	}
	416
	417	ret = of_address_to_resource(node, 0, &res);
	418	if (ret)
	419	goto put_node;
	420
	421	base->pbase = res.start;
	422	base->vbase = ioremap(res.start, resource_size(&res));
	423	if (!base->vbase)
	424	ret = -ENOMEM;
	425
	426	put_node:
	427	of_node_put(node);
	428	out:
	429	return ret;
	430	}
	431
afc51f46	432	static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata)
df595746 AH	433	{
	434	phys_addr_t ocram_pbase;
	435	struct device_node *node;
	436	struct platform_device *pdev;
	437	struct imx6_cpu_pm_info *pm_info;
	438	struct gen_pool *ocram_pool;
	439	unsigned long ocram_base;
	440	int i, ret = 0;
	441	const u32 *mmdc_offset_array;
	442
afc51f46 SG	443	suspend_set_ops(&imx6q_pm_ops);
afc51f46 SG	444
df595746 AH	445	if (!socdata) {
	446	pr_warn("%s: invalid argument!\n", __func__);
	447	return -EINVAL;
	448	}
	449
	450	node = of_find_compatible_node(NULL, NULL, "mmio-sram");
	451	if (!node) {
	452	pr_warn("%s: failed to find ocram node!\n", __func__);
	453	return -ENODEV;
	454	}
	455
	456	pdev = of_find_device_by_node(node);
	457	if (!pdev) {
	458	pr_warn("%s: failed to find ocram device!\n", __func__);
	459	ret = -ENODEV;
	460	goto put_node;
	461	}
	462
	463	ocram_pool = dev_get_gen_pool(&pdev->dev);
	464	if (!ocram_pool) {
	465	pr_warn("%s: ocram pool unavailable!\n", __func__);
	466	ret = -ENODEV;
	467	goto put_node;
	468	}
	469
	470	ocram_base = gen_pool_alloc(ocram_pool, MX6Q_SUSPEND_OCRAM_SIZE);
	471	if (!ocram_base) {
	472	pr_warn("%s: unable to alloc ocram!\n", __func__);
	473	ret = -ENOMEM;
	474	goto put_node;
	475	}
	476
	477	ocram_pbase = gen_pool_virt_to_phys(ocram_pool, ocram_base);
	478
	479	suspend_ocram_base = __arm_ioremap_exec(ocram_pbase,
	480	MX6Q_SUSPEND_OCRAM_SIZE, false);
	481
	482	pm_info = suspend_ocram_base;
	483	pm_info->pbase = ocram_pbase;
	484	pm_info->resume_addr = virt_to_phys(v7_cpu_resume);
	485	pm_info->pm_info_size = sizeof(*pm_info);
	486
	487	/*
	488	* ccm physical address is not used by asm code currently,
	489	* so get ccm virtual address directly, as we already have
	490	* it from ccm driver.
	491	*/
	492	pm_info->ccm_base.vbase = ccm_base;
	493
	494	ret = imx6_pm_get_base(&pm_info->mmdc_base, socdata->mmdc_compat);
	495	if (ret) {
	496	pr_warn("%s: failed to get mmdc base %d!\n", __func__, ret);
	497	goto put_node;
	498	}
	499
	500	ret = imx6_pm_get_base(&pm_info->src_base, socdata->src_compat);
	501	if (ret) {
	502	pr_warn("%s: failed to get src base %d!\n", __func__, ret);
	503	goto src_map_failed;
	504	}
	505
	506	ret = imx6_pm_get_base(&pm_info->iomuxc_base, socdata->iomuxc_compat);
	507	if (ret) {
	508	pr_warn("%s: failed to get iomuxc base %d!\n", __func__, ret);
509	goto iomuxc_map_failed;
510	}
511
512	ret = imx6_pm_get_base(&pm_info->gpc_base, socdata->gpc_compat);
513	if (ret) {
514	pr_warn("%s: failed to get gpc base %d!\n", __func__, ret);
515	goto gpc_map_failed;
516	}
517
518	ret = imx6_pm_get_base(&pm_info->l2_base, "arm,pl310-cache");
519	if (ret) {
520	pr_warn("%s: failed to get pl310-cache base %d!\n",
521	__func__, ret);
522	goto pl310_cache_map_failed;
523	}
524
525	pm_info->cpu_type = socdata->cpu_type;
526	pm_info->mmdc_io_num = socdata->mmdc_io_num;
527	mmdc_offset_array = socdata->mmdc_io_offset;
528
529	for (i = 0; i < pm_info->mmdc_io_num; i++) {
530	pm_info->mmdc_io_val[i][0] =
531	mmdc_offset_array[i];
532	pm_info->mmdc_io_val[i][1] =
533	readl_relaxed(pm_info->iomuxc_base.vbase +
534	mmdc_offset_array[i]);
535	}
536
537	imx6_suspend_in_ocram_fn = fncpy(
538	suspend_ocram_base + sizeof(*pm_info),
539	&imx6_suspend,
540	MX6Q_SUSPEND_OCRAM_SIZE - sizeof(*pm_info));
541
542	goto put_node;
543
544	pl310_cache_map_failed:
545	iounmap(&pm_info->gpc_base.vbase);
546	gpc_map_failed:
547	iounmap(&pm_info->iomuxc_base.vbase);
548	iomuxc_map_failed:
549	iounmap(&pm_info->src_base.vbase);
550	src_map_failed:
551	iounmap(&pm_info->mmdc_base.vbase);
552	put_node:
553	of_node_put(node);
554
555	return ret;
556	}
557
558	static void __init imx6_pm_common_init(const struct imx6_pm_socdata
559	*socdata)
a1f1c7ef	560	{
d48866fe	561	struct regmap *gpr;
df595746	562	int ret;
d48866fe	563
9e8147bb SG	564	WARN_ON(!ccm_base);
9e8147bb SG	565
110666dc SG	566	if (IS_ENABLED(CONFIG_SUSPEND)) {
	567	ret = imx6q_suspend_init(socdata);
	568	if (ret)
	569	pr_warn("%s: No DDR LPM support with suspend %d!\n",
	570	__func__, ret);
	571	}
df595746	572
d48866fe	573	/*
48c95841 AH	574	* This is for SW workaround step #1 of ERR007265, see comments
48c95841 AH	575	* in imx6q_set_lpm for details of this errata.
d48866fe SG	576	* Force IOMUXC irq pending, so that the interrupt to GPC can be
	577	* used to deassert dsm_request signal when the signal gets
	578	* asserted unexpectedly.
	579	*/
	580	gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
	581	if (!IS_ERR(gpr))
	582	regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_GINT,
	583	IMX6Q_GPR1_GINT);
a1f1c7ef	584	}
df595746 AH	585
	586	void __init imx6q_pm_init(void)
	587	{
	588	imx6_pm_common_init(&imx6q_pm_data);
	589	}
	590
	591	void __init imx6dl_pm_init(void)
	592	{
da9e9261	593	imx6_pm_common_init(&imx6dl_pm_data);
df595746 AH	594	}
	595
	596	void __init imx6sl_pm_init(void)
	597	{
64b08681	598	imx6_pm_common_init(&imx6sl_pm_data);
df595746	599	}
ff843d62 AH	600
	601	void __init imx6sx_pm_init(void)
	602	{
	603	imx6_pm_common_init(&imx6sx_pm_data);
	604	}