[deliverable/linux.git] / arch / arm / mach-imx / pm-imx6q.c

/*
 * Copyright 2011-2013 Freescale Semiconductor, Inc.
 * Copyright 2011 Linaro Ltd.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <linux/delay.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/regmap.h>
#include <linux/suspend.h>
#include <asm/cacheflush.h>
#include <asm/proc-fns.h>
#include <asm/suspend.h>
#include <asm/hardware/cache-l2x0.h>

#include "common.h"
#include "hardware.h"

#define CCR				0x0
#define BM_CCR_WB_COUNT			(0x7 << 16)
#define BM_CCR_RBC_BYPASS_COUNT		(0x3f << 21)
#define BM_CCR_RBC_EN			(0x1 << 27)

#define CLPCR				0x54
#define BP_CLPCR_LPM			0
#define BM_CLPCR_LPM			(0x3 << 0)
#define BM_CLPCR_BYPASS_PMIC_READY	(0x1 << 2)
#define BM_CLPCR_ARM_CLK_DIS_ON_LPM	(0x1 << 5)
#define BM_CLPCR_SBYOS			(0x1 << 6)
#define BM_CLPCR_DIS_REF_OSC		(0x1 << 7)
#define BM_CLPCR_VSTBY			(0x1 << 8)
#define BP_CLPCR_STBY_COUNT		9
#define BM_CLPCR_STBY_COUNT		(0x3 << 9)
#define BM_CLPCR_COSC_PWRDOWN		(0x1 << 11)
#define BM_CLPCR_WB_PER_AT_LPM		(0x1 << 16)
#define BM_CLPCR_WB_CORE_AT_LPM		(0x1 << 17)
#define BM_CLPCR_BYP_MMDC_CH0_LPM_HS	(0x1 << 19)
#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS	(0x1 << 21)
#define BM_CLPCR_MASK_CORE0_WFI		(0x1 << 22)
#define BM_CLPCR_MASK_CORE1_WFI		(0x1 << 23)
#define BM_CLPCR_MASK_CORE2_WFI		(0x1 << 24)
#define BM_CLPCR_MASK_CORE3_WFI		(0x1 << 25)
#define BM_CLPCR_MASK_SCU_IDLE		(0x1 << 26)
#define BM_CLPCR_MASK_L2CC_IDLE		(0x1 << 27)

#define CGPR				0x64
#define BM_CGPR_CHICKEN_BIT		(0x1 << 17)

static void __iomem *ccm_base;

void imx6q_set_chicken_bit(void)
{
	u32 val = readl_relaxed(ccm_base + CGPR);

	val |= BM_CGPR_CHICKEN_BIT;
	writel_relaxed(val, ccm_base + CGPR);
}

static void imx6q_enable_rbc(bool enable)
{
	u32 val;

	/*
	 * need to mask all interrupts in GPC before
	 * operating RBC configurations
	 */
	imx_gpc_mask_all();

	/* configure RBC enable bit */
	val = readl_relaxed(ccm_base + CCR);
	val &= ~BM_CCR_RBC_EN;
	val |= enable ? BM_CCR_RBC_EN : 0;
	writel_relaxed(val, ccm_base + CCR);

	/* configure RBC count */
	val = readl_relaxed(ccm_base + CCR);
	val &= ~BM_CCR_RBC_BYPASS_COUNT;
	val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0;
	writel(val, ccm_base + CCR);

	/*
	 * need to delay at least 2 cycles of CKIL(32K)
	 * due to hardware design requirement, which is
	 * ~61us, here we use 65us for safe
	 */
	udelay(65);

	/* restore GPC interrupt mask settings */
	imx_gpc_restore_all();
}

static void imx6q_enable_wb(bool enable)
{
	u32 val;

	/* configure well bias enable bit */
	val = readl_relaxed(ccm_base + CLPCR);
	val &= ~BM_CLPCR_WB_PER_AT_LPM;
	val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0;
	writel_relaxed(val, ccm_base + CLPCR);

	/* configure well bias count */
	val = readl_relaxed(ccm_base + CCR);
	val &= ~BM_CCR_WB_COUNT;
	val |= enable ? BM_CCR_WB_COUNT : 0;
	writel_relaxed(val, ccm_base + CCR);
}

int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
{
	struct irq_data *iomuxc_irq_data = irq_get_irq_data(32);
	u32 val = readl_relaxed(ccm_base + CLPCR);

	val &= ~BM_CLPCR_LPM;
	switch (mode) {
	case WAIT_CLOCKED:
		break;
	case WAIT_UNCLOCKED:
		val |= 0x1 << BP_CLPCR_LPM;
		val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM;
		break;
	case STOP_POWER_ON:
		val |= 0x2 << BP_CLPCR_LPM;
		break;
	case WAIT_UNCLOCKED_POWER_OFF:
		val |= 0x1 << BP_CLPCR_LPM;
		val &= ~BM_CLPCR_VSTBY;
		val &= ~BM_CLPCR_SBYOS;
		break;
	case STOP_POWER_OFF:
		val |= 0x2 << BP_CLPCR_LPM;
		val |= 0x3 << BP_CLPCR_STBY_COUNT;
		val |= BM_CLPCR_VSTBY;
		val |= BM_CLPCR_SBYOS;
		if (cpu_is_imx6sl()) {
			val |= BM_CLPCR_BYPASS_PMIC_READY;
			val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
		} else {
			val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
		}
		break;
	default:
		return -EINVAL;
	}

	/*
	 * ERR007265: CCM: When improper low-power sequence is used,
	 * the SoC enters low power mode before the ARM core executes WFI.
	 *
	 * Software workaround:
	 * 1) Software should trigger IRQ #32 (IOMUX) to be always pending
	 *    by setting IOMUX_GPR1_GINT.
	 * 2) Software should then unmask IRQ #32 in GPC before setting CCM
	 *    Low-Power mode.
	 * 3) Software should mask IRQ #32 right after CCM Low-Power mode
	 *    is set (set bits 0-1 of CCM_CLPCR).
	 */
	imx_gpc_irq_unmask(iomuxc_irq_data);
	writel_relaxed(val, ccm_base + CLPCR);
	imx_gpc_irq_mask(iomuxc_irq_data);

	return 0;
}

static int imx6q_suspend_finish(unsigned long val)
{
	cpu_do_idle();
	return 0;
}

static int imx6q_pm_enter(suspend_state_t state)
{
	switch (state) {
	case PM_SUSPEND_MEM:
		imx6q_set_lpm(STOP_POWER_OFF);
		imx6q_enable_wb(true);
		imx6q_enable_rbc(true);
		imx_gpc_pre_suspend();
		imx_anatop_pre_suspend();
		imx_set_cpu_jump(0, v7_cpu_resume);
		/* Zzz ... */
		cpu_suspend(0, imx6q_suspend_finish);
		if (cpu_is_imx6q() || cpu_is_imx6dl())
			imx_smp_prepare();
		imx_anatop_post_resume();
		imx_gpc_post_resume();
		imx6q_enable_rbc(false);
		imx6q_enable_wb(false);
		imx6q_set_lpm(WAIT_CLOCKED);
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

static const struct platform_suspend_ops imx6q_pm_ops = {
	.enter = imx6q_pm_enter,
	.valid = suspend_valid_only_mem,
};

void __init imx6q_pm_set_ccm_base(void __iomem *base)
{
	ccm_base = base;
}

void __init imx6q_pm_init(void)
{
	struct regmap *gpr;

	WARN_ON(!ccm_base);

	/*
	 * This is for SW workaround step #1 of ERR007265, see comments
	 * in imx6q_set_lpm for details of this errata.
	 * Force IOMUXC irq pending, so that the interrupt to GPC can be
	 * used to deassert dsm_request signal when the signal gets
	 * asserted unexpectedly.
	 */
	gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
	if (!IS_ERR(gpr))
		regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_GINT,
				   IMX6Q_GPR1_GINT);


	suspend_set_ops(&imx6q_pm_ops);
}
Commit	Line	Data
a1f1c7ef	1	/*
e95dddb3	2	* Copyright 2011-2013 Freescale Semiconductor, Inc.
a1f1c7ef SG	3	* Copyright 2011 Linaro Ltd.
	4	*
	5	* The code contained herein is licensed under the GNU General Public
	6	* License. You may obtain a copy of the GNU General Public License
	7	* Version 2 or later at the following locations:
	8	*
	9	* http://www.opensource.org/licenses/gpl-license.html
	10	* http://www.gnu.org/copyleft/gpl.html
	11	*/
	12
9e8147bb	13	#include <linux/delay.h>
a1f1c7ef SG	14	#include <linux/init.h>
a1f1c7ef SG	15	#include <linux/io.h>
d48866fe SG	16	#include <linux/irq.h>
	17	#include <linux/mfd/syscon.h>
	18	#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
a1f1c7ef	19	#include <linux/of.h>
9e8147bb	20	#include <linux/of_address.h>
d48866fe	21	#include <linux/regmap.h>
a1f1c7ef SG	22	#include <linux/suspend.h>
	23	#include <asm/cacheflush.h>
	24	#include <asm/proc-fns.h>
	25	#include <asm/suspend.h>
	26	#include <asm/hardware/cache-l2x0.h>
a1f1c7ef	27
e3372474	28	#include "common.h"
50f2de61	29	#include "hardware.h"
e3372474	30
9e8147bb SG	31	#define CCR 0x0
	32	#define BM_CCR_WB_COUNT (0x7 << 16)
	33	#define BM_CCR_RBC_BYPASS_COUNT (0x3f << 21)
	34	#define BM_CCR_RBC_EN (0x1 << 27)
	35
	36	#define CLPCR 0x54
	37	#define BP_CLPCR_LPM 0
	38	#define BM_CLPCR_LPM (0x3 << 0)
	39	#define BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2)
	40	#define BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
	41	#define BM_CLPCR_SBYOS (0x1 << 6)
	42	#define BM_CLPCR_DIS_REF_OSC (0x1 << 7)
	43	#define BM_CLPCR_VSTBY (0x1 << 8)
	44	#define BP_CLPCR_STBY_COUNT 9
	45	#define BM_CLPCR_STBY_COUNT (0x3 << 9)
	46	#define BM_CLPCR_COSC_PWRDOWN (0x1 << 11)
	47	#define BM_CLPCR_WB_PER_AT_LPM (0x1 << 16)
	48	#define BM_CLPCR_WB_CORE_AT_LPM (0x1 << 17)
	49	#define BM_CLPCR_BYP_MMDC_CH0_LPM_HS (0x1 << 19)
	50	#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS (0x1 << 21)
	51	#define BM_CLPCR_MASK_CORE0_WFI (0x1 << 22)
	52	#define BM_CLPCR_MASK_CORE1_WFI (0x1 << 23)
	53	#define BM_CLPCR_MASK_CORE2_WFI (0x1 << 24)
	54	#define BM_CLPCR_MASK_CORE3_WFI (0x1 << 25)
	55	#define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26)
	56	#define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27)
	57
	58	#define CGPR 0x64
	59	#define BM_CGPR_CHICKEN_BIT (0x1 << 17)
	60
	61	static void __iomem *ccm_base;
	62
	63	void imx6q_set_chicken_bit(void)
	64	{
	65	u32 val = readl_relaxed(ccm_base + CGPR);
	66
	67	val \|= BM_CGPR_CHICKEN_BIT;
	68	writel_relaxed(val, ccm_base + CGPR);
	69	}
	70
	71	static void imx6q_enable_rbc(bool enable)
	72	{
	73	u32 val;
9e8147bb	74
9e8147bb SG	75	/*
	76	* need to mask all interrupts in GPC before
	77	* operating RBC configurations
	78	*/
	79	imx_gpc_mask_all();
	80
	81	/* configure RBC enable bit */
	82	val = readl_relaxed(ccm_base + CCR);
	83	val &= ~BM_CCR_RBC_EN;
	84	val \|= enable ? BM_CCR_RBC_EN : 0;
	85	writel_relaxed(val, ccm_base + CCR);
	86
	87	/* configure RBC count */
	88	val = readl_relaxed(ccm_base + CCR);
	89	val &= ~BM_CCR_RBC_BYPASS_COUNT;
	90	val \|= enable ? BM_CCR_RBC_BYPASS_COUNT : 0;
	91	writel(val, ccm_base + CCR);
	92
	93	/*
	94	* need to delay at least 2 cycles of CKIL(32K)
	95	* due to hardware design requirement, which is
	96	* ~61us, here we use 65us for safe
	97	*/
	98	udelay(65);
	99
	100	/* restore GPC interrupt mask settings */
	101	imx_gpc_restore_all();
9e8147bb SG	102	}
	103
	104	static void imx6q_enable_wb(bool enable)
	105	{
	106	u32 val;
9e8147bb SG	107
	108	/* configure well bias enable bit */
	109	val = readl_relaxed(ccm_base + CLPCR);
	110	val &= ~BM_CLPCR_WB_PER_AT_LPM;
	111	val \|= enable ? BM_CLPCR_WB_PER_AT_LPM : 0;
	112	writel_relaxed(val, ccm_base + CLPCR);
	113
	114	/* configure well bias count */
	115	val = readl_relaxed(ccm_base + CCR);
	116	val &= ~BM_CCR_WB_COUNT;
	117	val \|= enable ? BM_CCR_WB_COUNT : 0;
	118	writel_relaxed(val, ccm_base + CCR);
9e8147bb SG	119	}
	120
	121	int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
	122	{
8435cf75	123	struct irq_data *iomuxc_irq_data = irq_get_irq_data(32);
9e8147bb SG	124	u32 val = readl_relaxed(ccm_base + CLPCR);
	125
	126	val &= ~BM_CLPCR_LPM;
	127	switch (mode) {
	128	case WAIT_CLOCKED:
9e8147bb SG	129	break;
	130	case WAIT_UNCLOCKED:
	131	val \|= 0x1 << BP_CLPCR_LPM;
	132	val \|= BM_CLPCR_ARM_CLK_DIS_ON_LPM;
	133	break;
	134	case STOP_POWER_ON:
	135	val \|= 0x2 << BP_CLPCR_LPM;
	136	break;
	137	case WAIT_UNCLOCKED_POWER_OFF:
	138	val \|= 0x1 << BP_CLPCR_LPM;
	139	val &= ~BM_CLPCR_VSTBY;
	140	val &= ~BM_CLPCR_SBYOS;
	141	break;
	142	case STOP_POWER_OFF:
	143	val \|= 0x2 << BP_CLPCR_LPM;
	144	val \|= 0x3 << BP_CLPCR_STBY_COUNT;
	145	val \|= BM_CLPCR_VSTBY;
	146	val \|= BM_CLPCR_SBYOS;
9ba64fe3 SG	147	if (cpu_is_imx6sl()) {
	148	val \|= BM_CLPCR_BYPASS_PMIC_READY;
	149	val \|= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
	150	} else {
	151	val \|= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
	152	}
9e8147bb SG	153	break;
	154	default:
	155	return -EINVAL;
	156	}
	157
d48866fe	158	/*
48c95841 AH	159	* ERR007265: CCM: When improper low-power sequence is used,
	160	* the SoC enters low power mode before the ARM core executes WFI.
	161	*
	162	* Software workaround:
	163	* 1) Software should trigger IRQ #32 (IOMUX) to be always pending
	164	* by setting IOMUX_GPR1_GINT.
	165	* 2) Software should then unmask IRQ #32 in GPC before setting CCM
	166	* Low-Power mode.
	167	* 3) Software should mask IRQ #32 right after CCM Low-Power mode
	168	* is set (set bits 0-1 of CCM_CLPCR).
d48866fe	169	*/
8435cf75	170	imx_gpc_irq_unmask(iomuxc_irq_data);
9e8147bb	171	writel_relaxed(val, ccm_base + CLPCR);
8435cf75	172	imx_gpc_irq_mask(iomuxc_irq_data);
9e8147bb SG	173
	174	return 0;
	175	}
	176
a1f1c7ef SG	177	static int imx6q_suspend_finish(unsigned long val)
	178	{
	179	cpu_do_idle();
	180	return 0;
	181	}
	182
	183	static int imx6q_pm_enter(suspend_state_t state)
	184	{
	185	switch (state) {
	186	case PM_SUSPEND_MEM:
	187	imx6q_set_lpm(STOP_POWER_OFF);
1d674a73 SG	188	imx6q_enable_wb(true);
1d674a73 SG	189	imx6q_enable_rbc(true);
a1f1c7ef	190	imx_gpc_pre_suspend();
e95dddb3	191	imx_anatop_pre_suspend();
a1f1c7ef SG	192	imx_set_cpu_jump(0, v7_cpu_resume);
	193	/* Zzz ... */
	194	cpu_suspend(0, imx6q_suspend_finish);
9ba64fe3 SG	195	if (cpu_is_imx6q() \|\| cpu_is_imx6dl())
9ba64fe3 SG	196	imx_smp_prepare();
e95dddb3	197	imx_anatop_post_resume();
a1f1c7ef	198	imx_gpc_post_resume();
1d674a73 SG	199	imx6q_enable_rbc(false);
1d674a73 SG	200	imx6q_enable_wb(false);
83ae2098	201	imx6q_set_lpm(WAIT_CLOCKED);
a1f1c7ef SG	202	break;
	203	default:
	204	return -EINVAL;
	205	}
	206
	207	return 0;
	208	}
	209
	210	static const struct platform_suspend_ops imx6q_pm_ops = {
	211	.enter = imx6q_pm_enter,
	212	.valid = suspend_valid_only_mem,
	213	};
	214
9e8147bb SG	215	void __init imx6q_pm_set_ccm_base(void __iomem *base)
	216	{
	217	ccm_base = base;
	218	}
	219
a1f1c7ef SG	220	void __init imx6q_pm_init(void)
a1f1c7ef SG	221	{
d48866fe SG	222	struct regmap *gpr;
d48866fe SG	223
9e8147bb SG	224	WARN_ON(!ccm_base);
9e8147bb SG	225
d48866fe	226	/*
48c95841 AH	227	* This is for SW workaround step #1 of ERR007265, see comments
48c95841 AH	228	* in imx6q_set_lpm for details of this errata.
d48866fe SG	229	* Force IOMUXC irq pending, so that the interrupt to GPC can be
	230	* used to deassert dsm_request signal when the signal gets
	231	* asserted unexpectedly.
	232	*/
	233	gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
	234	if (!IS_ERR(gpr))
	235	regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_GINT,
	236	IMX6Q_GPR1_GINT);
	237
9e8147bb	238
a1f1c7ef SG	239	suspend_set_ops(&imx6q_pm_ops);
a1f1c7ef SG	240	}