[deliverable/linux.git] / arch / arm / mach-imx / pm-imx6q.c

/*
 * Copyright 2011-2013 Freescale Semiconductor, Inc.
 * Copyright 2011 Linaro Ltd.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <linux/delay.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/suspend.h>
#include <asm/cacheflush.h>
#include <asm/proc-fns.h>
#include <asm/suspend.h>
#include <asm/hardware/cache-l2x0.h>

#include "common.h"
#include "hardware.h"

#define CCR				0x0
#define BM_CCR_WB_COUNT			(0x7 << 16)
#define BM_CCR_RBC_BYPASS_COUNT		(0x3f << 21)
#define BM_CCR_RBC_EN			(0x1 << 27)

#define CLPCR				0x54
#define BP_CLPCR_LPM			0
#define BM_CLPCR_LPM			(0x3 << 0)
#define BM_CLPCR_BYPASS_PMIC_READY	(0x1 << 2)
#define BM_CLPCR_ARM_CLK_DIS_ON_LPM	(0x1 << 5)
#define BM_CLPCR_SBYOS			(0x1 << 6)
#define BM_CLPCR_DIS_REF_OSC		(0x1 << 7)
#define BM_CLPCR_VSTBY			(0x1 << 8)
#define BP_CLPCR_STBY_COUNT		9
#define BM_CLPCR_STBY_COUNT		(0x3 << 9)
#define BM_CLPCR_COSC_PWRDOWN		(0x1 << 11)
#define BM_CLPCR_WB_PER_AT_LPM		(0x1 << 16)
#define BM_CLPCR_WB_CORE_AT_LPM		(0x1 << 17)
#define BM_CLPCR_BYP_MMDC_CH0_LPM_HS	(0x1 << 19)
#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS	(0x1 << 21)
#define BM_CLPCR_MASK_CORE0_WFI		(0x1 << 22)
#define BM_CLPCR_MASK_CORE1_WFI		(0x1 << 23)
#define BM_CLPCR_MASK_CORE2_WFI		(0x1 << 24)
#define BM_CLPCR_MASK_CORE3_WFI		(0x1 << 25)
#define BM_CLPCR_MASK_SCU_IDLE		(0x1 << 26)
#define BM_CLPCR_MASK_L2CC_IDLE		(0x1 << 27)

#define CGPR				0x64
#define BM_CGPR_CHICKEN_BIT		(0x1 << 17)

static void __iomem *ccm_base;

void imx6q_set_chicken_bit(void)
{
	u32 val = readl_relaxed(ccm_base + CGPR);

	val |= BM_CGPR_CHICKEN_BIT;
	writel_relaxed(val, ccm_base + CGPR);
}

static void imx6q_enable_rbc(bool enable)
{
	u32 val;
	static bool last_rbc_mode;

	if (last_rbc_mode == enable)
		return;
	/*
	 * need to mask all interrupts in GPC before
	 * operating RBC configurations
	 */
	imx_gpc_mask_all();

	/* configure RBC enable bit */
	val = readl_relaxed(ccm_base + CCR);
	val &= ~BM_CCR_RBC_EN;
	val |= enable ? BM_CCR_RBC_EN : 0;
	writel_relaxed(val, ccm_base + CCR);

	/* configure RBC count */
	val = readl_relaxed(ccm_base + CCR);
	val &= ~BM_CCR_RBC_BYPASS_COUNT;
	val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0;
	writel(val, ccm_base + CCR);

	/*
	 * need to delay at least 2 cycles of CKIL(32K)
	 * due to hardware design requirement, which is
	 * ~61us, here we use 65us for safe
	 */
	udelay(65);

	/* restore GPC interrupt mask settings */
	imx_gpc_restore_all();

	last_rbc_mode = enable;
}

static void imx6q_enable_wb(bool enable)
{
	u32 val;
	static bool last_wb_mode;

	if (last_wb_mode == enable)
		return;

	/* configure well bias enable bit */
	val = readl_relaxed(ccm_base + CLPCR);
	val &= ~BM_CLPCR_WB_PER_AT_LPM;
	val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0;
	writel_relaxed(val, ccm_base + CLPCR);

	/* configure well bias count */
	val = readl_relaxed(ccm_base + CCR);
	val &= ~BM_CCR_WB_COUNT;
	val |= enable ? BM_CCR_WB_COUNT : 0;
	writel_relaxed(val, ccm_base + CCR);

	last_wb_mode = enable;
}

int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
{
	u32 val = readl_relaxed(ccm_base + CLPCR);

	val &= ~BM_CLPCR_LPM;
	switch (mode) {
	case WAIT_CLOCKED:
		imx6q_enable_wb(false);
		imx6q_enable_rbc(false);
		break;
	case WAIT_UNCLOCKED:
		val |= 0x1 << BP_CLPCR_LPM;
		val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM;
		break;
	case STOP_POWER_ON:
		val |= 0x2 << BP_CLPCR_LPM;
		break;
	case WAIT_UNCLOCKED_POWER_OFF:
		val |= 0x1 << BP_CLPCR_LPM;
		val &= ~BM_CLPCR_VSTBY;
		val &= ~BM_CLPCR_SBYOS;
		break;
	case STOP_POWER_OFF:
		val |= 0x2 << BP_CLPCR_LPM;
		val |= 0x3 << BP_CLPCR_STBY_COUNT;
		val |= BM_CLPCR_VSTBY;
		val |= BM_CLPCR_SBYOS;
		imx6q_enable_wb(true);
		imx6q_enable_rbc(true);
		break;
	default:
		return -EINVAL;
	}

	writel_relaxed(val, ccm_base + CLPCR);

	return 0;
}

static int imx6q_suspend_finish(unsigned long val)
{
	cpu_do_idle();
	return 0;
}

static int imx6q_pm_enter(suspend_state_t state)
{
	switch (state) {
	case PM_SUSPEND_MEM:
		imx6q_set_lpm(STOP_POWER_OFF);
		imx_gpc_pre_suspend();
		imx_anatop_pre_suspend();
		imx_set_cpu_jump(0, v7_cpu_resume);
		/* Zzz ... */
		cpu_suspend(0, imx6q_suspend_finish);
		imx_smp_prepare();
		imx_anatop_post_resume();
		imx_gpc_post_resume();
		imx6q_set_lpm(WAIT_CLOCKED);
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

static const struct platform_suspend_ops imx6q_pm_ops = {
	.enter = imx6q_pm_enter,
	.valid = suspend_valid_only_mem,
};

void __init imx6q_pm_set_ccm_base(void __iomem *base)
{
	ccm_base = base;
}

void __init imx6q_pm_init(void)
{
	WARN_ON(!ccm_base);

	/* Set initial power mode */
	imx6q_set_lpm(WAIT_CLOCKED);

	suspend_set_ops(&imx6q_pm_ops);
}
Commit	Line	Data
a1f1c7ef	1	/*
e95dddb3	2	* Copyright 2011-2013 Freescale Semiconductor, Inc.
a1f1c7ef SG	3	* Copyright 2011 Linaro Ltd.
	4	*
	5	* The code contained herein is licensed under the GNU General Public
	6	* License. You may obtain a copy of the GNU General Public License
	7	* Version 2 or later at the following locations:
	8	*
	9	* http://www.opensource.org/licenses/gpl-license.html
	10	* http://www.gnu.org/copyleft/gpl.html
	11	*/
	12
9e8147bb	13	#include <linux/delay.h>
a1f1c7ef SG	14	#include <linux/init.h>
	15	#include <linux/io.h>
	16	#include <linux/of.h>
9e8147bb	17	#include <linux/of_address.h>
a1f1c7ef SG	18	#include <linux/suspend.h>
	19	#include <asm/cacheflush.h>
	20	#include <asm/proc-fns.h>
	21	#include <asm/suspend.h>
	22	#include <asm/hardware/cache-l2x0.h>
a1f1c7ef	23
e3372474	24	#include "common.h"
50f2de61	25	#include "hardware.h"
e3372474	26
9e8147bb SG	27	#define CCR 0x0
	28	#define BM_CCR_WB_COUNT (0x7 << 16)
	29	#define BM_CCR_RBC_BYPASS_COUNT (0x3f << 21)
	30	#define BM_CCR_RBC_EN (0x1 << 27)
	31
	32	#define CLPCR 0x54
	33	#define BP_CLPCR_LPM 0
	34	#define BM_CLPCR_LPM (0x3 << 0)
	35	#define BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2)
	36	#define BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
	37	#define BM_CLPCR_SBYOS (0x1 << 6)
	38	#define BM_CLPCR_DIS_REF_OSC (0x1 << 7)
	39	#define BM_CLPCR_VSTBY (0x1 << 8)
	40	#define BP_CLPCR_STBY_COUNT 9
	41	#define BM_CLPCR_STBY_COUNT (0x3 << 9)
	42	#define BM_CLPCR_COSC_PWRDOWN (0x1 << 11)
	43	#define BM_CLPCR_WB_PER_AT_LPM (0x1 << 16)
	44	#define BM_CLPCR_WB_CORE_AT_LPM (0x1 << 17)
	45	#define BM_CLPCR_BYP_MMDC_CH0_LPM_HS (0x1 << 19)
	46	#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS (0x1 << 21)
	47	#define BM_CLPCR_MASK_CORE0_WFI (0x1 << 22)
	48	#define BM_CLPCR_MASK_CORE1_WFI (0x1 << 23)
	49	#define BM_CLPCR_MASK_CORE2_WFI (0x1 << 24)
	50	#define BM_CLPCR_MASK_CORE3_WFI (0x1 << 25)
	51	#define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26)
	52	#define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27)
	53
	54	#define CGPR 0x64
	55	#define BM_CGPR_CHICKEN_BIT (0x1 << 17)
	56
	57	static void __iomem *ccm_base;
	58
	59	void imx6q_set_chicken_bit(void)
	60	{
	61	u32 val = readl_relaxed(ccm_base + CGPR);
	62
	63	val \|= BM_CGPR_CHICKEN_BIT;
	64	writel_relaxed(val, ccm_base + CGPR);
	65	}
	66
	67	static void imx6q_enable_rbc(bool enable)
	68	{
	69	u32 val;
	70	static bool last_rbc_mode;
	71
	72	if (last_rbc_mode == enable)
	73	return;
	74	/*
	75	* need to mask all interrupts in GPC before
	76	* operating RBC configurations
	77	*/
	78	imx_gpc_mask_all();
	79
	80	/* configure RBC enable bit */
	81	val = readl_relaxed(ccm_base + CCR);
	82	val &= ~BM_CCR_RBC_EN;
	83	val \|= enable ? BM_CCR_RBC_EN : 0;
	84	writel_relaxed(val, ccm_base + CCR);
	85
	86	/* configure RBC count */
	87	val = readl_relaxed(ccm_base + CCR);
	88	val &= ~BM_CCR_RBC_BYPASS_COUNT;
	89	val \|= enable ? BM_CCR_RBC_BYPASS_COUNT : 0;
	90	writel(val, ccm_base + CCR);
91
92	/*
93	* need to delay at least 2 cycles of CKIL(32K)
94	* due to hardware design requirement, which is
95	* ~61us, here we use 65us for safe
96	*/
97	udelay(65);
98
99	/* restore GPC interrupt mask settings */
100	imx_gpc_restore_all();
101
102	last_rbc_mode = enable;
103	}
104
105	static void imx6q_enable_wb(bool enable)
106	{
107	u32 val;
108	static bool last_wb_mode;
109
110	if (last_wb_mode == enable)
111	return;
112
113	/* configure well bias enable bit */
114	val = readl_relaxed(ccm_base + CLPCR);
115	val &= ~BM_CLPCR_WB_PER_AT_LPM;
116	val \|= enable ? BM_CLPCR_WB_PER_AT_LPM : 0;
117	writel_relaxed(val, ccm_base + CLPCR);
118
119	/* configure well bias count */
120	val = readl_relaxed(ccm_base + CCR);
121	val &= ~BM_CCR_WB_COUNT;
122	val \|= enable ? BM_CCR_WB_COUNT : 0;
123	writel_relaxed(val, ccm_base + CCR);
124
125	last_wb_mode = enable;
126	}
127
128	int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
129	{
130	u32 val = readl_relaxed(ccm_base + CLPCR);
131
132	val &= ~BM_CLPCR_LPM;
133	switch (mode) {
134	case WAIT_CLOCKED:
135	imx6q_enable_wb(false);
136	imx6q_enable_rbc(false);
137	break;
138	case WAIT_UNCLOCKED:
139	val \|= 0x1 << BP_CLPCR_LPM;
140	val \|= BM_CLPCR_ARM_CLK_DIS_ON_LPM;
141	break;
142	case STOP_POWER_ON:
143	val \|= 0x2 << BP_CLPCR_LPM;
144	break;
145	case WAIT_UNCLOCKED_POWER_OFF:
146	val \|= 0x1 << BP_CLPCR_LPM;
147	val &= ~BM_CLPCR_VSTBY;
148	val &= ~BM_CLPCR_SBYOS;
149	break;
150	case STOP_POWER_OFF:
151	val \|= 0x2 << BP_CLPCR_LPM;
152	val \|= 0x3 << BP_CLPCR_STBY_COUNT;
153	val \|= BM_CLPCR_VSTBY;
154	val \|= BM_CLPCR_SBYOS;
155	imx6q_enable_wb(true);
156	imx6q_enable_rbc(true);
157	break;
158	default:
159	return -EINVAL;
160	}
161
162	writel_relaxed(val, ccm_base + CLPCR);
163
164	return 0;
165	}
166
a1f1c7ef SG	167	static int imx6q_suspend_finish(unsigned long val)
	168	{
	169	cpu_do_idle();
	170	return 0;
	171	}
	172
	173	static int imx6q_pm_enter(suspend_state_t state)
	174	{
	175	switch (state) {
	176	case PM_SUSPEND_MEM:
	177	imx6q_set_lpm(STOP_POWER_OFF);
	178	imx_gpc_pre_suspend();
e95dddb3	179	imx_anatop_pre_suspend();
a1f1c7ef SG	180	imx_set_cpu_jump(0, v7_cpu_resume);
	181	/* Zzz ... */
	182	cpu_suspend(0, imx6q_suspend_finish);
	183	imx_smp_prepare();
e95dddb3	184	imx_anatop_post_resume();
a1f1c7ef	185	imx_gpc_post_resume();
83ae2098	186	imx6q_set_lpm(WAIT_CLOCKED);
a1f1c7ef SG	187	break;
	188	default:
	189	return -EINVAL;
	190	}
	191
	192	return 0;
	193	}
	194
	195	static const struct platform_suspend_ops imx6q_pm_ops = {
	196	.enter = imx6q_pm_enter,
	197	.valid = suspend_valid_only_mem,
	198	};
	199
9e8147bb SG	200	void __init imx6q_pm_set_ccm_base(void __iomem *base)
	201	{
	202	ccm_base = base;
	203	}
	204
a1f1c7ef SG	205	void __init imx6q_pm_init(void)
a1f1c7ef SG	206	{
9e8147bb SG	207	WARN_ON(!ccm_base);
	208
	209	/* Set initial power mode */
	210	imx6q_set_lpm(WAIT_CLOCKED);
	211
a1f1c7ef SG	212	suspend_set_ops(&imx6q_pm_ops);
a1f1c7ef SG	213	}