projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 9fbbe689 SG |
1 | /* |
| 2 | * Copyright 2011 Freescale Semiconductor, Inc. | |
| 3 | * Copyright 2011 Linaro Ltd. | |
| 4 | * | |
| 5 | * The code contained herein is licensed under the GNU General Public | |
| 6 | * License. You may obtain a copy of the GNU General Public License | |
| 7 | * Version 2 or later at the following locations: | |
| 8 | * | |
| 9 | * http://www.opensource.org/licenses/gpl-license.html | |
| 10 | * http://www.gnu.org/copyleft/gpl.html | |
| 11 | */ | |
| 12 | ||
| 13 | #include <linux/init.h> | |
| 14 | #include <linux/io.h> | |
| 15 | #include <linux/of.h> | |
| 16 | #include <linux/of_address.h> | |
| eaa142ca | 17 | #include <linux/smp.h> |
| eb50439b | 18 | #include <asm/smp_plat.h> |
| 9fbbe689 SG |
19 | |
| 20 | #define SRC_SCR 0x000 | |
| 21 | #define SRC_GPR1 0x020 | |
| 0575fb75 | 22 | #define BP_SRC_SCR_WARM_RESET_ENABLE 0 |
| 9fbbe689 SG |
23 | #define BP_SRC_SCR_CORE1_RST 14 |
| 24 | #define BP_SRC_SCR_CORE1_ENABLE 22 | |
| 25 | ||
| 26 | static void __iomem *src_base; | |
| 27 | ||
| 28 | void imx_enable_cpu(int cpu, bool enable) | |
| 29 | { | |
| 30 | u32 mask, val; | |
| 31 | ||
| eaa142ca | 32 | cpu = cpu_logical_map(cpu); |
| 9fbbe689 SG |
33 | mask = 1 << (BP_SRC_SCR_CORE1_ENABLE + cpu - 1); |
| 34 | val = readl_relaxed(src_base + SRC_SCR); | |
| 35 | val = enable ? val | mask : val & ~mask; | |
| 36 | writel_relaxed(val, src_base + SRC_SCR); | |
| 37 | } | |
| 38 | ||
| 39 | void imx_set_cpu_jump(int cpu, void *jump_addr) | |
| 40 | { | |
| eaa142ca | 41 | cpu = cpu_logical_map(cpu); |
| 0a60cb14 | 42 | writel_relaxed(virt_to_phys(jump_addr), |
| 9fbbe689 SG |
43 | src_base + SRC_GPR1 + cpu * 8); |
| 44 | } | |
| 45 | ||
| 2f3edfd7 SG |
46 | u32 imx_get_cpu_arg(int cpu) |
| 47 | { | |
| 48 | cpu = cpu_logical_map(cpu); | |
| 49 | return readl_relaxed(src_base + SRC_GPR1 + cpu * 8 + 4); | |
| 50 | } | |
| 51 | ||
| 52 | void imx_set_cpu_arg(int cpu, u32 arg) | |
| 53 | { | |
| 54 | cpu = cpu_logical_map(cpu); | |
| 55 | writel_relaxed(arg, src_base + SRC_GPR1 + cpu * 8 + 4); | |
| 56 | } | |
| 57 | ||
| 0575fb75 SG |
58 | void imx_src_prepare_restart(void) |
| 59 | { | |
| 60 | u32 val; | |
| 61 | ||
| 62 | /* clear enable bits of secondary cores */ | |
| 63 | val = readl_relaxed(src_base + SRC_SCR); | |
| 64 | val &= ~(0x7 << BP_SRC_SCR_CORE1_ENABLE); | |
| 65 | writel_relaxed(val, src_base + SRC_SCR); | |
| 66 | ||
| 67 | /* clear persistent entry register of primary core */ | |
| 68 | writel_relaxed(0, src_base + SRC_GPR1); | |
| 69 | } | |
| 70 | ||
| 9fbbe689 SG |
71 | void __init imx_src_init(void) |
| 72 | { | |
| 73 | struct device_node *np; | |
| 0575fb75 | 74 | u32 val; |
| 9fbbe689 SG |
75 | |
| 76 | np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-src"); | |
| 77 | src_base = of_iomap(np, 0); | |
| 78 | WARN_ON(!src_base); | |
| 0575fb75 SG |
79 | |
| 80 | /* | |
| 81 | * force warm reset sources to generate cold reset | |
| 82 | * for a more reliable restart | |
| 83 | */ | |
| 84 | val = readl_relaxed(src_base + SRC_SCR); | |
| 85 | val &= ~(1 << BP_SRC_SCR_WARM_RESET_ENABLE); | |
| 86 | writel_relaxed(val, src_base + SRC_SCR); | |
| 9fbbe689 | 87 | } |