[deliverable/linux.git] / arch / arm / mach-imx / system.c

/*
 * Copyright (C) 1999 ARM Limited
 * Copyright (C) 2000 Deep Blue Solutions Ltd
 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
 * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/of.h>
#include <linux/of_address.h>

#include <asm/system_misc.h>
#include <asm/proc-fns.h>
#include <asm/mach-types.h>

#include "common.h"
#include "hardware.h"

static void __iomem *wdog_base;
static struct clk *wdog_clk;

/*
 * Reset the system. It is called by machine_restart().
 */
void mxc_restart(enum reboot_mode mode, const char *cmd)
{
	unsigned int wcr_enable;

	if (wdog_clk)
		clk_enable(wdog_clk);

	if (cpu_is_mx1())
		wcr_enable = (1 << 0);
	else
		wcr_enable = (1 << 2);

	/* Assert SRS signal */
	__raw_writew(wcr_enable, wdog_base);

	/* wait for reset to assert... */
	mdelay(500);

	pr_err("%s: Watchdog reset failed to assert reset\n", __func__);

	/* delay to allow the serial port to show the message */
	mdelay(50);

	/* we'll take a jump through zero as a poor second */
	soft_restart(0);
}

void __init mxc_arch_reset_init(void __iomem *base)
{
	wdog_base = base;

	wdog_clk = clk_get_sys("imx2-wdt.0", NULL);
	if (IS_ERR(wdog_clk)) {
		pr_warn("%s: failed to get wdog clock\n", __func__);
		wdog_clk = NULL;
		return;
	}

	clk_prepare(wdog_clk);
}

void __init mxc_arch_reset_init_dt(void)
{
	struct device_node *np;

	np = of_find_compatible_node(NULL, NULL, "fsl,imx21-wdt");
	wdog_base = of_iomap(np, 0);
	WARN_ON(!wdog_base);

	wdog_clk = of_clk_get(np, 0);
	if (IS_ERR(wdog_clk)) {
		pr_warn("%s: failed to get wdog clock\n", __func__);
		wdog_clk = NULL;
		return;
	}

	clk_prepare(wdog_clk);
}
Commit	Line	Data
eea643f7 JB	1	/*
	2	* Copyright (C) 1999 ARM Limited
	3	* Copyright (C) 2000 Deep Blue Solutions Ltd
	4	* Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
	5	* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
74bef9a4	6	* Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com
eea643f7 JB	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
eea643f7 JB	17	*/
	18
	19	#include <linux/kernel.h>
	20	#include <linux/clk.h>
	21	#include <linux/io.h>
74bef9a4 IY	22	#include <linux/err.h>
74bef9a4 IY	23	#include <linux/delay.h>
c1e31d12 SG	24	#include <linux/of.h>
c1e31d12 SG	25	#include <linux/of_address.h>
eea643f7	26
9f97da78	27	#include <asm/system_misc.h>
eea643f7	28	#include <asm/proc-fns.h>
c2932bf4	29	#include <asm/mach-types.h>
eea643f7	30
e3372474	31	#include "common.h"
50f2de61	32	#include "hardware.h"
e3372474	33
be124c94	34	static void __iomem *wdog_base;
18cb680f	35	static struct clk *wdog_clk;
eea643f7 JB	36
	37	/*
	38	* Reset the system. It is called by machine_restart().
	39	*/
7b6d864b	40	void mxc_restart(enum reboot_mode mode, const char *cmd)
eea643f7	41	{
be124c94 SH	42	unsigned int wcr_enable;
be124c94 SH	43
18cb680f SG	44	if (wdog_clk)
18cb680f SG	45	clk_enable(wdog_clk);
eea643f7	46
18cb680f SG	47	if (cpu_is_mx1())
	48	wcr_enable = (1 << 0);
	49	else
be124c94	50	wcr_enable = (1 << 2);
eea643f7	51
eea643f7	52	/* Assert SRS signal */
be124c94	53	__raw_writew(wcr_enable, wdog_base);
74bef9a4 IY	54
	55	/* wait for reset to assert... */
	56	mdelay(500);
	57
18cb680f	58	pr_err("%s: Watchdog reset failed to assert reset\n", __func__);
74bef9a4 IY	59
	60	/* delay to allow the serial port to show the message */
	61	mdelay(50);
	62
	63	/* we'll take a jump through zero as a poor second */
e879c862	64	soft_restart(0);
eea643f7	65	}
be124c94	66
18cb680f	67	void __init mxc_arch_reset_init(void __iomem *base)
be124c94 SH	68	{
be124c94 SH	69	wdog_base = base;
18cb680f SG	70
	71	wdog_clk = clk_get_sys("imx2-wdt.0", NULL);
	72	if (IS_ERR(wdog_clk)) {
	73	pr_warn("%s: failed to get wdog clock\n", __func__);
	74	wdog_clk = NULL;
	75	return;
	76	}
	77
	78	clk_prepare(wdog_clk);
be124c94	79	}
c1e31d12 SG	80
	81	void __init mxc_arch_reset_init_dt(void)
	82	{
	83	struct device_node *np;
	84
	85	np = of_find_compatible_node(NULL, NULL, "fsl,imx21-wdt");
	86	wdog_base = of_iomap(np, 0);
	87	WARN_ON(!wdog_base);
	88
	89	wdog_clk = of_clk_get(np, 0);
	90	if (IS_ERR(wdog_clk)) {
	91	pr_warn("%s: failed to get wdog clock\n", __func__);
	92	wdog_clk = NULL;
	93	return;
	94	}
	95
	96	clk_prepare(wdog_clk);
	97	}