Commit | Line | Data |
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eea643f7 JB |
1 | /* |
2 | * Copyright (C) 1999 ARM Limited | |
3 | * Copyright (C) 2000 Deep Blue Solutions Ltd | |
4 | * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
5 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | |
74bef9a4 | 6 | * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com |
eea643f7 JB |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
eea643f7 JB |
17 | */ |
18 | ||
19 | #include <linux/kernel.h> | |
20 | #include <linux/clk.h> | |
21 | #include <linux/io.h> | |
74bef9a4 IY |
22 | #include <linux/err.h> |
23 | #include <linux/delay.h> | |
c1e31d12 SG |
24 | #include <linux/of.h> |
25 | #include <linux/of_address.h> | |
eea643f7 | 26 | |
9f97da78 | 27 | #include <asm/system_misc.h> |
eea643f7 | 28 | #include <asm/proc-fns.h> |
c2932bf4 | 29 | #include <asm/mach-types.h> |
e6a07569 | 30 | #include <asm/hardware/cache-l2x0.h> |
eea643f7 | 31 | |
e3372474 | 32 | #include "common.h" |
50f2de61 | 33 | #include "hardware.h" |
e3372474 | 34 | |
be124c94 | 35 | static void __iomem *wdog_base; |
18cb680f | 36 | static struct clk *wdog_clk; |
6f98cb22 | 37 | static int wcr_enable = (1 << 2); |
eea643f7 JB |
38 | |
39 | /* | |
40 | * Reset the system. It is called by machine_restart(). | |
41 | */ | |
7b6d864b | 42 | void mxc_restart(enum reboot_mode mode, const char *cmd) |
eea643f7 | 43 | { |
5a6e1502 AS |
44 | if (!wdog_base) |
45 | goto reset_fallback; | |
46 | ||
ce8ad883 | 47 | if (!IS_ERR(wdog_clk)) |
18cb680f | 48 | clk_enable(wdog_clk); |
eea643f7 | 49 | |
eea643f7 | 50 | /* Assert SRS signal */ |
c553138f | 51 | imx_writew(wcr_enable, wdog_base); |
2c11b57a SG |
52 | /* |
53 | * Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be | |
54 | * written twice), we add another two writes to ensure there must be at | |
55 | * least two writes happen in the same one 32kHz clock period. We save | |
56 | * the target check here, since the writes shouldn't be a huge burden | |
57 | * for other platforms. | |
58 | */ | |
c553138f JB |
59 | imx_writew(wcr_enable, wdog_base); |
60 | imx_writew(wcr_enable, wdog_base); | |
74bef9a4 IY |
61 | |
62 | /* wait for reset to assert... */ | |
63 | mdelay(500); | |
64 | ||
18cb680f | 65 | pr_err("%s: Watchdog reset failed to assert reset\n", __func__); |
74bef9a4 IY |
66 | |
67 | /* delay to allow the serial port to show the message */ | |
68 | mdelay(50); | |
69 | ||
5a6e1502 | 70 | reset_fallback: |
74bef9a4 | 71 | /* we'll take a jump through zero as a poor second */ |
e879c862 | 72 | soft_restart(0); |
eea643f7 | 73 | } |
be124c94 | 74 | |
18cb680f | 75 | void __init mxc_arch_reset_init(void __iomem *base) |
be124c94 SH |
76 | { |
77 | wdog_base = base; | |
18cb680f SG |
78 | |
79 | wdog_clk = clk_get_sys("imx2-wdt.0", NULL); | |
ce8ad883 | 80 | if (IS_ERR(wdog_clk)) |
18cb680f | 81 | pr_warn("%s: failed to get wdog clock\n", __func__); |
ce8ad883 AS |
82 | else |
83 | clk_prepare(wdog_clk); | |
be124c94 | 84 | } |
c1e31d12 | 85 | |
6f98cb22 AB |
86 | #ifdef CONFIG_SOC_IMX1 |
87 | void __init imx1_reset_init(void __iomem *base) | |
88 | { | |
89 | wcr_enable = (1 << 0); | |
90 | mxc_arch_reset_init(base); | |
91 | } | |
92 | #endif | |
93 | ||
e6a07569 | 94 | #ifdef CONFIG_CACHE_L2X0 |
10eff770 | 95 | void __init imx_init_l2cache(void) |
e6a07569 SG |
96 | { |
97 | void __iomem *l2x0_base; | |
98 | struct device_node *np; | |
99 | unsigned int val; | |
100 | ||
101 | np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache"); | |
102 | if (!np) | |
510aca64 | 103 | return; |
e6a07569 SG |
104 | |
105 | l2x0_base = of_iomap(np, 0); | |
510aca64 AS |
106 | if (!l2x0_base) |
107 | goto put_node; | |
e6a07569 | 108 | |
c00e4c54 AS |
109 | if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) { |
110 | /* Configure the L2 PREFETCH and POWER registers */ | |
111 | val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL); | |
b8290371 AS |
112 | val |= L310_PREFETCH_CTRL_DBL_LINEFILL | |
113 | L310_PREFETCH_CTRL_INSTR_PREFETCH | | |
1d9e9477 AS |
114 | L310_PREFETCH_CTRL_DATA_PREFETCH; |
115 | ||
116 | /* Set perfetch offset to improve performance */ | |
117 | val &= ~L310_PREFETCH_CTRL_OFFSET_MASK; | |
118 | val |= 15; | |
119 | ||
c00e4c54 AS |
120 | writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL); |
121 | } | |
e6a07569 SG |
122 | |
123 | iounmap(l2x0_base); | |
510aca64 | 124 | put_node: |
e6a07569 | 125 | of_node_put(np); |
e6a07569 SG |
126 | } |
127 | #endif |