[deliverable/linux.git] / arch / arm / mach-imx / tzic.c

/*
 * Copyright (C)2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/io.h>
#include <linux/irqdomain.h>
#include <linux/of.h>

#include <asm/mach/irq.h>
#include <asm/exception.h>

#include "common.h"
#include "hardware.h"
#include "irq-common.h"

/*
 *****************************************
 * TZIC Registers                        *
 *****************************************
 */

#define TZIC_INTCNTL	0x0000	/* Control register */
#define TZIC_INTTYPE	0x0004	/* Controller Type register */
#define TZIC_IMPID	0x0008	/* Distributor Implementer Identification */
#define TZIC_PRIOMASK	0x000C	/* Priority Mask Reg */
#define TZIC_SYNCCTRL	0x0010	/* Synchronizer Control register */
#define TZIC_DSMINT	0x0014	/* DSM interrupt Holdoffregister */
#define TZIC_INTSEC0(i)	(0x0080 + ((i) << 2)) /* Interrupt Security Reg 0 */
#define TZIC_ENSET0(i)	(0x0100 + ((i) << 2)) /* Enable Set Reg 0 */
#define TZIC_ENCLEAR0(i) (0x0180 + ((i) << 2)) /* Enable Clear Reg 0 */
#define TZIC_SRCSET0	0x0200	/* Source Set Register 0 */
#define TZIC_SRCCLAR0	0x0280	/* Source Clear Register 0 */
#define TZIC_PRIORITY0	0x0400	/* Priority Register 0 */
#define TZIC_PND0	0x0D00	/* Pending Register 0 */
#define TZIC_HIPND(i)	(0x0D80+ ((i) << 2))	/* High Priority Pending Register */
#define TZIC_WAKEUP0(i)	(0x0E00 + ((i) << 2))	/* Wakeup Config Register */
#define TZIC_SWINT	0x0F00	/* Software Interrupt Rigger Register */
#define TZIC_ID0	0x0FD0	/* Indentification Register 0 */

static void __iomem *tzic_base;
static struct irq_domain *domain;

#define TZIC_NUM_IRQS 128

#ifdef CONFIG_FIQ
static int tzic_set_irq_fiq(unsigned int irq, unsigned int type)
{
	unsigned int index, mask, value;

	index = irq >> 5;
	if (unlikely(index >= 4))
		return -EINVAL;
	mask = 1U << (irq & 0x1F);

	value = __raw_readl(tzic_base + TZIC_INTSEC0(index)) | mask;
	if (type)
		value &= ~mask;
	__raw_writel(value, tzic_base + TZIC_INTSEC0(index));

	return 0;
}
#else
#define tzic_set_irq_fiq NULL
#endif

#ifdef CONFIG_PM
static void tzic_irq_suspend(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	int idx = d->hwirq >> 5;

	__raw_writel(gc->wake_active, tzic_base + TZIC_WAKEUP0(idx));
}

static void tzic_irq_resume(struct irq_data *d)
{
	int idx = d->hwirq >> 5;

	__raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(idx)),
		     tzic_base + TZIC_WAKEUP0(idx));
}

#else
#define tzic_irq_suspend NULL
#define tzic_irq_resume NULL
#endif

static struct mxc_extra_irq tzic_extra_irq = {
#ifdef CONFIG_FIQ
	.set_irq_fiq = tzic_set_irq_fiq,
#endif
};

static __init void tzic_init_gc(int idx, unsigned int irq_start)
{
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;

	gc = irq_alloc_generic_chip("tzic", 1, irq_start, tzic_base,
				    handle_level_irq);
	gc->private = &tzic_extra_irq;
	gc->wake_enabled = IRQ_MSK(32);

	ct = gc->chip_types;
	ct->chip.irq_mask = irq_gc_mask_disable_reg;
	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
	ct->chip.irq_set_wake = irq_gc_set_wake;
	ct->chip.irq_suspend = tzic_irq_suspend;
	ct->chip.irq_resume = tzic_irq_resume;
	ct->regs.disable = TZIC_ENCLEAR0(idx);
	ct->regs.enable = TZIC_ENSET0(idx);

	irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
}

static void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs)
{
	u32 stat;
	int i, irqofs, handled;

	do {
		handled = 0;

		for (i = 0; i < 4; i++) {
			stat = __raw_readl(tzic_base + TZIC_HIPND(i)) &
				__raw_readl(tzic_base + TZIC_INTSEC0(i));

			while (stat) {
				handled = 1;
				irqofs = fls(stat) - 1;
				handle_IRQ(irq_find_mapping(domain,
						irqofs + i * 32), regs);
				stat &= ~(1 << irqofs);
			}
		}
	} while (handled);
}

/*
 * This function initializes the TZIC hardware and disables all the
 * interrupts. It registers the interrupt enable and disable functions
 * to the kernel for each interrupt source.
 */
void __init tzic_init_irq(void __iomem *irqbase)
{
	struct device_node *np;
	int irq_base;
	int i;

	tzic_base = irqbase;
	/* put the TZIC into the reset value with
	 * all interrupts disabled
	 */
	i = __raw_readl(tzic_base + TZIC_INTCNTL);

	__raw_writel(0x80010001, tzic_base + TZIC_INTCNTL);
	__raw_writel(0x1f, tzic_base + TZIC_PRIOMASK);
	__raw_writel(0x02, tzic_base + TZIC_SYNCCTRL);

	for (i = 0; i < 4; i++)
		__raw_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0(i));

	/* disable all interrupts */
	for (i = 0; i < 4; i++)
		__raw_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0(i));

	/* all IRQ no FIQ Warning :: No selection */

	irq_base = irq_alloc_descs(-1, 0, TZIC_NUM_IRQS, numa_node_id());
	WARN_ON(irq_base < 0);

	np = of_find_compatible_node(NULL, NULL, "fsl,tzic");
	domain = irq_domain_add_legacy(np, TZIC_NUM_IRQS, irq_base, 0,
				       &irq_domain_simple_ops, NULL);
	WARN_ON(!domain);

	for (i = 0; i < 4; i++, irq_base += 32)
		tzic_init_gc(i, irq_base);

	set_handle_irq(tzic_handle_irq);

#ifdef CONFIG_FIQ
	/* Initialize FIQ */
	init_FIQ(FIQ_START);
#endif

	pr_info("TrustZone Interrupt Controller (TZIC) initialized\n");
}

/**
 * tzic_enable_wake() - enable wakeup interrupt
 *
 * @return			0 if successful; non-zero otherwise
 *
 * This function provides an interrupt synchronization point that is required
 * by tzic enabled platforms before entering imx specific low power modes (ie,
 * those low power modes beyond the WAIT_CLOCKED basic ARM WFI only mode).
 */
int tzic_enable_wake(void)
{
	unsigned int i;

	__raw_writel(1, tzic_base + TZIC_DSMINT);
	if (unlikely(__raw_readl(tzic_base + TZIC_DSMINT) == 0))
		return -EAGAIN;

	for (i = 0; i < 4; i++)
		__raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(i)),
			     tzic_base + TZIC_WAKEUP0(i));

	return 0;
}
Commit	Line	Data
a003708a	1	/*
e24798e6	2	* Copyright (C)2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
a003708a AK	3	*
	4	* The code contained herein is licensed under the GNU General Public
	5	* License. You may obtain a copy of the GNU General Public License
	6	* Version 2 or later at the following locations:
	7	*
	8	* http://www.opensource.org/licenses/gpl-license.html
	9	* http://www.gnu.org/copyleft/gpl.html
	10	*/
	11
	12	#include <linux/module.h>
	13	#include <linux/moduleparam.h>
	14	#include <linux/init.h>
	15	#include <linux/device.h>
	16	#include <linux/errno.h>
	17	#include <linux/io.h>
f3eac29d SG	18	#include <linux/irqdomain.h>
f3eac29d SG	19	#include <linux/of.h>
a003708a AK	20
a003708a AK	21	#include <asm/mach/irq.h>
98de0cbb	22	#include <asm/exception.h>
a003708a	23
e3372474	24	#include "common.h"
50f2de61	25	#include "hardware.h"
cdc3f106 PH	26	#include "irq-common.h"
cdc3f106 PH	27
a003708a AK	28	/*
	29	*****************************************
	30	* TZIC Registers *
	31	*****************************************
	32	*/
	33
	34	#define TZIC_INTCNTL 0x0000 /* Control register */
	35	#define TZIC_INTTYPE 0x0004 /* Controller Type register */
	36	#define TZIC_IMPID 0x0008 /* Distributor Implementer Identification */
	37	#define TZIC_PRIOMASK 0x000C /* Priority Mask Reg */
	38	#define TZIC_SYNCCTRL 0x0010 /* Synchronizer Control register */
	39	#define TZIC_DSMINT 0x0014 /* DSM interrupt Holdoffregister */
	40	#define TZIC_INTSEC0(i) (0x0080 + ((i) << 2)) /* Interrupt Security Reg 0 */
	41	#define TZIC_ENSET0(i) (0x0100 + ((i) << 2)) /* Enable Set Reg 0 */
	42	#define TZIC_ENCLEAR0(i) (0x0180 + ((i) << 2)) /* Enable Clear Reg 0 */
	43	#define TZIC_SRCSET0 0x0200 /* Source Set Register 0 */
	44	#define TZIC_SRCCLAR0 0x0280 /* Source Clear Register 0 */
	45	#define TZIC_PRIORITY0 0x0400 /* Priority Register 0 */
	46	#define TZIC_PND0 0x0D00 /* Pending Register 0 */
58a92600	47	#define TZIC_HIPND(i) (0x0D80+ ((i) << 2)) /* High Priority Pending Register */
a003708a AK	48	#define TZIC_WAKEUP0(i) (0x0E00 + ((i) << 2)) /* Wakeup Config Register */
	49	#define TZIC_SWINT 0x0F00 /* Software Interrupt Rigger Register */
	50	#define TZIC_ID0 0x0FD0 /* Indentification Register 0 */
	51
516e89d7	52	static void __iomem *tzic_base;
f3eac29d	53	static struct irq_domain *domain;
a003708a	54
fe31ad41 SH	55	#define TZIC_NUM_IRQS 128
fe31ad41 SH	56
cdc3f106 PH	57	#ifdef CONFIG_FIQ
	58	static int tzic_set_irq_fiq(unsigned int irq, unsigned int type)
	59	{
	60	unsigned int index, mask, value;
	61
	62	index = irq >> 5;
	63	if (unlikely(index >= 4))
	64	return -EINVAL;
	65	mask = 1U << (irq & 0x1F);
	66
	67	value = __raw_readl(tzic_base + TZIC_INTSEC0(index)) \| mask;
	68	if (type)
	69	value &= ~mask;
	70	__raw_writel(value, tzic_base + TZIC_INTSEC0(index));
	71
	72	return 0;
	73	}
8b6c44f1 SG	74	#else
8b6c44f1 SG	75	#define tzic_set_irq_fiq NULL
cdc3f106 PH	76	#endif
cdc3f106 PH	77
010dc8af HW	78	#ifdef CONFIG_PM
	79	static void tzic_irq_suspend(struct irq_data *d)
	80	{
	81	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
f3eac29d	82	int idx = d->hwirq >> 5;
010dc8af HW	83
	84	__raw_writel(gc->wake_active, tzic_base + TZIC_WAKEUP0(idx));
	85	}
	86
	87	static void tzic_irq_resume(struct irq_data *d)
	88	{
f3eac29d	89	int idx = d->hwirq >> 5;
010dc8af HW	90
	91	__raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(idx)),
	92	tzic_base + TZIC_WAKEUP0(idx));
	93	}
	94
	95	#else
	96	#define tzic_irq_suspend NULL
	97	#define tzic_irq_resume NULL
	98	#endif
a003708a	99
3439a397 HW	100	static struct mxc_extra_irq tzic_extra_irq = {
	101	#ifdef CONFIG_FIQ
	102	.set_irq_fiq = tzic_set_irq_fiq,
	103	#endif
	104	};
	105
f3eac29d	106	static __init void tzic_init_gc(int idx, unsigned int irq_start)
a003708a	107	{
8b6c44f1 SG	108	struct irq_chip_generic *gc;
8b6c44f1 SG	109	struct irq_chip_type *ct;
8b6c44f1 SG	110
	111	gc = irq_alloc_generic_chip("tzic", 1, irq_start, tzic_base,
	112	handle_level_irq);
3439a397	113	gc->private = &tzic_extra_irq;
8b6c44f1	114	gc->wake_enabled = IRQ_MSK(32);
8b6c44f1 SG	115
	116	ct = gc->chip_types;
	117	ct->chip.irq_mask = irq_gc_mask_disable_reg;
	118	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
	119	ct->chip.irq_set_wake = irq_gc_set_wake;
010dc8af HW	120	ct->chip.irq_suspend = tzic_irq_suspend;
010dc8af HW	121	ct->chip.irq_resume = tzic_irq_resume;
8b6c44f1 SG	122	ct->regs.disable = TZIC_ENCLEAR0(idx);
	123	ct->regs.enable = TZIC_ENSET0(idx);
	124
	125	irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
a003708a AK	126	}
a003708a AK	127
000bf9ee	128	static void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs)
58a92600 SH	129	{
	130	u32 stat;
	131	int i, irqofs, handled;
	132
	133	do {
	134	handled = 0;
	135
	136	for (i = 0; i < 4; i++) {
	137	stat = __raw_readl(tzic_base + TZIC_HIPND(i)) &
	138	__raw_readl(tzic_base + TZIC_INTSEC0(i));
	139
	140	while (stat) {
	141	handled = 1;
	142	irqofs = fls(stat) - 1;
f3eac29d SG	143	handle_IRQ(irq_find_mapping(domain,
f3eac29d SG	144	irqofs + i * 32), regs);
58a92600 SH	145	stat &= ~(1 << irqofs);
	146	}
	147	}
	148	} while (handled);
	149	}
	150
a003708a AK	151	/*
	152	* This function initializes the TZIC hardware and disables all the
	153	* interrupts. It registers the interrupt enable and disable functions
	154	* to the kernel for each interrupt source.
	155	*/
	156	void __init tzic_init_irq(void __iomem *irqbase)
	157	{
f3eac29d SG	158	struct device_node *np;
f3eac29d SG	159	int irq_base;
a003708a AK	160	int i;
	161
	162	tzic_base = irqbase;
	163	/* put the TZIC into the reset value with
	164	* all interrupts disabled
	165	*/
	166	i = __raw_readl(tzic_base + TZIC_INTCNTL);
	167
	168	__raw_writel(0x80010001, tzic_base + TZIC_INTCNTL);
	169	__raw_writel(0x1f, tzic_base + TZIC_PRIOMASK);
	170	__raw_writel(0x02, tzic_base + TZIC_SYNCCTRL);
	171
	172	for (i = 0; i < 4; i++)
	173	__raw_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0(i));
	174
	175	/* disable all interrupts */
	176	for (i = 0; i < 4; i++)
	177	__raw_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0(i));
	178
	179	/* all IRQ no FIQ Warning :: No selection */
	180
f3eac29d SG	181	irq_base = irq_alloc_descs(-1, 0, TZIC_NUM_IRQS, numa_node_id());
	182	WARN_ON(irq_base < 0);
	183
	184	np = of_find_compatible_node(NULL, NULL, "fsl,tzic");
	185	domain = irq_domain_add_legacy(np, TZIC_NUM_IRQS, irq_base, 0,
	186	&irq_domain_simple_ops, NULL);
	187	WARN_ON(!domain);
	188
	189	for (i = 0; i < 4; i++, irq_base += 32)
	190	tzic_init_gc(i, irq_base);
cdc3f106	191
000bf9ee AS	192	set_handle_irq(tzic_handle_irq);
000bf9ee AS	193
cdc3f106 PH	194	#ifdef CONFIG_FIQ
cdc3f106 PH	195	/* Initialize FIQ */
bc89663a	196	init_FIQ(FIQ_START);
cdc3f106 PH	197	#endif
cdc3f106 PH	198
a003708a AK	199	pr_info("TrustZone Interrupt Controller (TZIC) initialized\n");
	200	}
	201
	202	/**
	203	* tzic_enable_wake() - enable wakeup interrupt
	204	*
a003708a	205	* @return 0 if successful; non-zero otherwise
eee4f400 RL	206	*
	207	* This function provides an interrupt synchronization point that is required
	208	* by tzic enabled platforms before entering imx specific low power modes (ie,
	209	* those low power modes beyond the WAIT_CLOCKED basic ARM WFI only mode).
a003708a	210	*/
010dc8af	211	int tzic_enable_wake(void)
a003708a	212	{
010dc8af	213	unsigned int i;
a003708a AK	214
	215	__raw_writel(1, tzic_base + TZIC_DSMINT);
	216	if (unlikely(__raw_readl(tzic_base + TZIC_DSMINT) == 0))
	217	return -EAGAIN;
	218
010dc8af HW	219	for (i = 0; i < 4; i++)
	220	__raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(i)),
	221	tzic_base + TZIC_WAKEUP0(i));
a003708a AK	222
	223	return 0;
	224	}