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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mach-integrator/integrator_ap.c | |
3 | * | |
4 | * Copyright (C) 2000-2003 Deep Blue Solutions Ltd | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
20 | #include <linux/types.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/list.h> | |
d052d1be | 24 | #include <linux/platform_device.h> |
1da177e4 LT |
25 | #include <linux/slab.h> |
26 | #include <linux/string.h> | |
b7808056 | 27 | #include <linux/syscore_ops.h> |
a62c80e5 RK |
28 | #include <linux/amba/bus.h> |
29 | #include <linux/amba/kmi.h> | |
fced80c7 | 30 | #include <linux/io.h> |
44fa72d1 | 31 | #include <linux/irqchip.h> |
a613163d | 32 | #include <linux/platform_data/clk-integrator.h> |
4980f9bc LW |
33 | #include <linux/of_irq.h> |
34 | #include <linux/of_address.h> | |
4672cddf | 35 | #include <linux/of_platform.h> |
e67ae6be | 36 | #include <linux/stat.h> |
379df279 | 37 | #include <linux/termios.h> |
1da177e4 | 38 | |
1da177e4 | 39 | #include <asm/setup.h> |
4e57b681 | 40 | #include <asm/param.h> /* HZ */ |
1da177e4 | 41 | #include <asm/mach-types.h> |
1da177e4 | 42 | |
1da177e4 | 43 | #include <asm/mach/arch.h> |
1da177e4 LT |
44 | #include <asm/mach/irq.h> |
45 | #include <asm/mach/map.h> | |
46 | #include <asm/mach/time.h> | |
47 | ||
1b1ef755 | 48 | #include "hardware.h" |
bb4dbefe | 49 | #include "cm.h" |
98c672cf | 50 | #include "common.h" |
ae9daf2d | 51 | #include "pci_v3.h" |
c36928ad | 52 | #include "lm.h" |
98c672cf | 53 | |
83feba51 | 54 | /* Base address to the AP system controller */ |
379df279 | 55 | void __iomem *ap_syscon_base; |
307b9667 LW |
56 | /* Base address to the external bus interface */ |
57 | static void __iomem *ebi_base; | |
83feba51 | 58 | |
83feba51 LW |
59 | |
60 | /* | |
1da177e4 LT |
61 | * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx |
62 | * is the (PA >> 12). | |
63 | * | |
64 | * Setup a VA for the Integrator interrupt controller (for header #0, | |
65 | * just for now). | |
66 | */ | |
c41b16f8 | 67 | #define VA_IC_BASE __io_address(INTEGRATOR_IC_BASE) |
1da177e4 LT |
68 | |
69 | /* | |
70 | * Logical Physical | |
1da177e4 | 71 | * ef000000 Cache flush |
1da177e4 | 72 | * f1100000 11000000 System controller registers |
1da177e4 LT |
73 | * f1300000 13000000 Counter/Timer |
74 | * f1400000 14000000 Interrupt controller | |
75 | * f1600000 16000000 UART 0 | |
76 | * f1700000 17000000 UART 1 | |
77 | * f1a00000 1a000000 Debug LEDs | |
78 | * f1b00000 1b000000 GPIO | |
79 | */ | |
80 | ||
060fd1be | 81 | static struct map_desc ap_io_desc[] __initdata __maybe_unused = { |
c8d27298 | 82 | { |
c8d27298 DS |
83 | .virtual = IO_ADDRESS(INTEGRATOR_IC_BASE), |
84 | .pfn = __phys_to_pfn(INTEGRATOR_IC_BASE), | |
85 | .length = SZ_4K, | |
86 | .type = MT_DEVICE | |
87 | }, { | |
88 | .virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE), | |
89 | .pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE), | |
90 | .length = SZ_4K, | |
91 | .type = MT_DEVICE | |
c8d27298 DS |
92 | }, { |
93 | .virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE), | |
94 | .pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE), | |
95 | .length = SZ_4K, | |
96 | .type = MT_DEVICE | |
97 | }, { | |
da7ba956 RK |
98 | .virtual = IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE), |
99 | .pfn = __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE), | |
c8d27298 DS |
100 | .length = SZ_4K, |
101 | .type = MT_DEVICE | |
c8d27298 | 102 | } |
1da177e4 LT |
103 | }; |
104 | ||
105 | static void __init ap_map_io(void) | |
106 | { | |
107 | iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc)); | |
ae9daf2d | 108 | pci_v3_early_init(); |
1da177e4 LT |
109 | } |
110 | ||
1da177e4 LT |
111 | #ifdef CONFIG_PM |
112 | static unsigned long ic_irq_enable; | |
113 | ||
b7808056 | 114 | static int irq_suspend(void) |
1da177e4 LT |
115 | { |
116 | ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE); | |
117 | return 0; | |
118 | } | |
119 | ||
b7808056 | 120 | static void irq_resume(void) |
1da177e4 LT |
121 | { |
122 | /* disable all irq sources */ | |
bb4dbefe | 123 | cm_clear_irqs(); |
1da177e4 LT |
124 | writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR); |
125 | writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR); | |
126 | ||
127 | writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET); | |
1da177e4 LT |
128 | } |
129 | #else | |
130 | #define irq_suspend NULL | |
131 | #define irq_resume NULL | |
132 | #endif | |
133 | ||
b7808056 | 134 | static struct syscore_ops irq_syscore_ops = { |
1da177e4 LT |
135 | .suspend = irq_suspend, |
136 | .resume = irq_resume, | |
137 | }; | |
138 | ||
b7808056 | 139 | static int __init irq_syscore_init(void) |
1da177e4 | 140 | { |
b7808056 RW |
141 | register_syscore_ops(&irq_syscore_ops); |
142 | ||
143 | return 0; | |
1da177e4 LT |
144 | } |
145 | ||
b7808056 | 146 | device_initcall(irq_syscore_init); |
1da177e4 | 147 | |
379df279 LW |
148 | /* |
149 | * For the PL010 found in the Integrator/AP some of the UART control is | |
150 | * implemented in the system controller and accessed using a callback | |
151 | * from the driver. | |
152 | */ | |
153 | static void integrator_uart_set_mctrl(struct amba_device *dev, | |
154 | void __iomem *base, unsigned int mctrl) | |
155 | { | |
156 | unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask; | |
157 | u32 phybase = dev->res.start; | |
158 | ||
159 | if (phybase == INTEGRATOR_UART0_BASE) { | |
160 | /* UART0 */ | |
161 | rts_mask = 1 << 4; | |
162 | dtr_mask = 1 << 5; | |
163 | } else { | |
164 | /* UART1 */ | |
165 | rts_mask = 1 << 6; | |
166 | dtr_mask = 1 << 7; | |
167 | } | |
168 | ||
169 | if (mctrl & TIOCM_RTS) | |
170 | ctrlc |= rts_mask; | |
171 | else | |
172 | ctrls |= rts_mask; | |
173 | ||
174 | if (mctrl & TIOCM_DTR) | |
175 | ctrlc |= dtr_mask; | |
176 | else | |
177 | ctrls |= dtr_mask; | |
178 | ||
179 | __raw_writel(ctrls, ap_syscon_base + INTEGRATOR_SC_CTRLS_OFFSET); | |
180 | __raw_writel(ctrlc, ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET); | |
181 | } | |
182 | ||
183 | struct amba_pl010_data ap_uart_data = { | |
184 | .set_mctrl = integrator_uart_set_mctrl, | |
185 | }; | |
186 | ||
a613163d LW |
187 | void __init ap_init_early(void) |
188 | { | |
189 | } | |
190 | ||
4980f9bc LW |
191 | static void __init ap_init_irq_of(void) |
192 | { | |
bb4dbefe | 193 | cm_init(); |
44fa72d1 | 194 | irqchip_init(); |
4980f9bc LW |
195 | } |
196 | ||
4672cddf LW |
197 | /* For the Device Tree, add in the UART callbacks as AUXDATA */ |
198 | static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = { | |
199 | OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE, | |
200 | "rtc", NULL), | |
201 | OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE, | |
379df279 | 202 | "uart0", &ap_uart_data), |
4672cddf | 203 | OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE, |
379df279 | 204 | "uart1", &ap_uart_data), |
4672cddf LW |
205 | OF_DEV_AUXDATA("arm,primecell", KMI0_BASE, |
206 | "kmi0", NULL), | |
207 | OF_DEV_AUXDATA("arm,primecell", KMI1_BASE, | |
208 | "kmi1", NULL), | |
209 | { /* sentinel */ }, | |
210 | }; | |
211 | ||
df36680f LW |
212 | static const struct of_device_id ap_syscon_match[] = { |
213 | { .compatible = "arm,integrator-ap-syscon"}, | |
214 | { }, | |
215 | }; | |
216 | ||
307b9667 LW |
217 | static const struct of_device_id ebi_match[] = { |
218 | { .compatible = "arm,external-bus-interface"}, | |
219 | { }, | |
220 | }; | |
221 | ||
4672cddf LW |
222 | static void __init ap_init_of(void) |
223 | { | |
224 | unsigned long sc_dec; | |
e67ae6be | 225 | struct device_node *syscon; |
307b9667 | 226 | struct device_node *ebi; |
4672cddf LW |
227 | int i; |
228 | ||
11f9323a | 229 | syscon = of_find_matching_node(NULL, ap_syscon_match); |
e67ae6be LW |
230 | if (!syscon) |
231 | return; | |
11f9323a | 232 | ebi = of_find_matching_node(NULL, ebi_match); |
307b9667 LW |
233 | if (!ebi) |
234 | return; | |
e67ae6be LW |
235 | |
236 | ap_syscon_base = of_iomap(syscon, 0); | |
237 | if (!ap_syscon_base) | |
238 | return; | |
307b9667 LW |
239 | ebi_base = of_iomap(ebi, 0); |
240 | if (!ebi_base) | |
241 | return; | |
e67ae6be | 242 | |
11f9323a LW |
243 | of_platform_populate(NULL, of_default_bus_match_table, |
244 | ap_auxdata_lookup, NULL); | |
245 | ||
83feba51 | 246 | sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET); |
4672cddf LW |
247 | for (i = 0; i < 4; i++) { |
248 | struct lm_device *lmdev; | |
249 | ||
250 | if ((sc_dec & (16 << i)) == 0) | |
251 | continue; | |
252 | ||
253 | lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL); | |
254 | if (!lmdev) | |
255 | continue; | |
256 | ||
257 | lmdev->resource.start = 0xc0000000 + 0x10000000 * i; | |
258 | lmdev->resource.end = lmdev->resource.start + 0x0fffffff; | |
259 | lmdev->resource.flags = IORESOURCE_MEM; | |
a6720258 | 260 | lmdev->irq = irq_of_parse_and_map(syscon, i); |
4672cddf LW |
261 | lmdev->id = i; |
262 | ||
263 | lm_device_register(lmdev); | |
264 | } | |
265 | } | |
266 | ||
4980f9bc LW |
267 | static const char * ap_dt_board_compat[] = { |
268 | "arm,integrator-ap", | |
269 | NULL, | |
270 | }; | |
271 | ||
272 | DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)") | |
273 | .reserve = integrator_reserve, | |
274 | .map_io = ap_map_io, | |
4980f9bc LW |
275 | .init_early = ap_init_early, |
276 | .init_irq = ap_init_irq_of, | |
4672cddf | 277 | .init_machine = ap_init_of, |
4980f9bc LW |
278 | .dt_compat = ap_dt_board_compat, |
279 | MACHINE_END |