[deliverable/linux.git] / arch / arm / mach-integrator / integrator_ap.c

/*
 *  linux/arch/arm/mach-integrator/integrator_ap.c
 *
 *  Copyright (C) 2000-2003 Deep Blue Solutions Ltd
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/syscore_ops.h>
#include <linux/amba/bus.h>
#include <linux/amba/kmi.h>
#include <linux/io.h>
#include <linux/irqchip.h>
#include <linux/mtd/physmap.h>
#include <linux/platform_data/clk-integrator.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/stat.h>
#include <linux/termios.h>

#include <asm/setup.h>
#include <asm/param.h>		/* HZ */
#include <asm/mach-types.h>

#include <asm/mach/arch.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>

#include "hardware.h"
#include "cm.h"
#include "common.h"
#include "pci_v3.h"
#include "lm.h"

/* Base address to the AP system controller */
void __iomem *ap_syscon_base;
/* Base address to the external bus interface */
static void __iomem *ebi_base;


/*
 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
 * is the (PA >> 12).
 *
 * Setup a VA for the Integrator interrupt controller (for header #0,
 * just for now).
 */
#define VA_IC_BASE	__io_address(INTEGRATOR_IC_BASE)

/*
 * Logical      Physical
 * ef000000			Cache flush
 * f1100000	11000000	System controller registers
 * f1300000	13000000	Counter/Timer
 * f1400000	14000000	Interrupt controller
 * f1600000	16000000	UART 0
 * f1700000	17000000	UART 1
 * f1a00000	1a000000	Debug LEDs
 * f1b00000	1b000000	GPIO
 */

static struct map_desc ap_io_desc[] __initdata __maybe_unused = {
	{
		.virtual	= IO_ADDRESS(INTEGRATOR_IC_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_IC_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_UART0_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_UART0_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_DBG_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_DBG_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}
};

static void __init ap_map_io(void)
{
	iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
	pci_v3_early_init();
}

#ifdef CONFIG_PM
static unsigned long ic_irq_enable;

static int irq_suspend(void)
{
	ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
	return 0;
}

static void irq_resume(void)
{
	/* disable all irq sources */
	cm_clear_irqs();
	writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
	writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);

	writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
}
#else
#define irq_suspend NULL
#define irq_resume NULL
#endif

static struct syscore_ops irq_syscore_ops = {
	.suspend	= irq_suspend,
	.resume		= irq_resume,
};

static int __init irq_syscore_init(void)
{
	register_syscore_ops(&irq_syscore_ops);

	return 0;
}

device_initcall(irq_syscore_init);

/*
 * Flash handling.
 */
static int ap_flash_init(struct platform_device *dev)
{
	u32 tmp;

	writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP,
	       ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);

	tmp = readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) |
		INTEGRATOR_EBI_WRITE_ENABLE;
	writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);

	if (!(readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET)
	      & INTEGRATOR_EBI_WRITE_ENABLE)) {
		writel(0xa05f, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
		writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
		writel(0, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
	}
	return 0;
}

static void ap_flash_exit(struct platform_device *dev)
{
	u32 tmp;

	writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP,
	       ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);

	tmp = readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) &
		~INTEGRATOR_EBI_WRITE_ENABLE;
	writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);

	if (readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) &
	    INTEGRATOR_EBI_WRITE_ENABLE) {
		writel(0xa05f, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
		writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
		writel(0, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
	}
}

static void ap_flash_set_vpp(struct platform_device *pdev, int on)
{
	if (on)
		writel(INTEGRATOR_SC_CTRL_nFLVPPEN,
		       ap_syscon_base + INTEGRATOR_SC_CTRLS_OFFSET);
	else
		writel(INTEGRATOR_SC_CTRL_nFLVPPEN,
		       ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
}

static struct physmap_flash_data ap_flash_data = {
	.width		= 4,
	.init		= ap_flash_init,
	.exit		= ap_flash_exit,
	.set_vpp	= ap_flash_set_vpp,
};

/*
 * For the PL010 found in the Integrator/AP some of the UART control is
 * implemented in the system controller and accessed using a callback
 * from the driver.
 */
static void integrator_uart_set_mctrl(struct amba_device *dev,
				void __iomem *base, unsigned int mctrl)
{
	unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask;
	u32 phybase = dev->res.start;

	if (phybase == INTEGRATOR_UART0_BASE) {
		/* UART0 */
		rts_mask = 1 << 4;
		dtr_mask = 1 << 5;
	} else {
		/* UART1 */
		rts_mask = 1 << 6;
		dtr_mask = 1 << 7;
	}

	if (mctrl & TIOCM_RTS)
		ctrlc |= rts_mask;
	else
		ctrls |= rts_mask;

	if (mctrl & TIOCM_DTR)
		ctrlc |= dtr_mask;
	else
		ctrls |= dtr_mask;

	__raw_writel(ctrls, ap_syscon_base + INTEGRATOR_SC_CTRLS_OFFSET);
	__raw_writel(ctrlc, ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
}

struct amba_pl010_data ap_uart_data = {
	.set_mctrl = integrator_uart_set_mctrl,
};

void __init ap_init_early(void)
{
}

static void __init ap_init_irq_of(void)
{
	cm_init();
	irqchip_init();
}

/* For the Device Tree, add in the UART callbacks as AUXDATA */
static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = {
	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
		"rtc", NULL),
	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
		"uart0", &ap_uart_data),
	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
		"uart1", &ap_uart_data),
	OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
		"kmi0", NULL),
	OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
		"kmi1", NULL),
	OF_DEV_AUXDATA("cfi-flash", INTEGRATOR_FLASH_BASE,
		"physmap-flash", &ap_flash_data),
	{ /* sentinel */ },
};

static const struct of_device_id ap_syscon_match[] = {
	{ .compatible = "arm,integrator-ap-syscon"},
	{ },
};

static const struct of_device_id ebi_match[] = {
	{ .compatible = "arm,external-bus-interface"},
	{ },
};

static void __init ap_init_of(void)
{
	unsigned long sc_dec;
	struct device_node *syscon;
	struct device_node *ebi;
	int i;

	syscon = of_find_matching_node(NULL, ap_syscon_match);
	if (!syscon)
		return;
	ebi = of_find_matching_node(NULL, ebi_match);
	if (!ebi)
		return;

	ap_syscon_base = of_iomap(syscon, 0);
	if (!ap_syscon_base)
		return;
	ebi_base = of_iomap(ebi, 0);
	if (!ebi_base)
		return;

	of_platform_populate(NULL, of_default_bus_match_table,
			ap_auxdata_lookup, NULL);

	sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET);
	for (i = 0; i < 4; i++) {
		struct lm_device *lmdev;

		if ((sc_dec & (16 << i)) == 0)
			continue;

		lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
		if (!lmdev)
			continue;

		lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
		lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
		lmdev->resource.flags = IORESOURCE_MEM;
		lmdev->irq = irq_of_parse_and_map(syscon, i);
		lmdev->id = i;

		lm_device_register(lmdev);
	}
}

static const char * ap_dt_board_compat[] = {
	"arm,integrator-ap",
	NULL,
};

DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
	.reserve	= integrator_reserve,
	.map_io		= ap_map_io,
	.init_early	= ap_init_early,
	.init_irq	= ap_init_irq_of,
	.init_machine	= ap_init_of,
	.dt_compat      = ap_dt_board_compat,
MACHINE_END
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-integrator/integrator_ap.c
	3	*
	4	* Copyright (C) 2000-2003 Deep Blue Solutions Ltd
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20	#include <linux/types.h>
	21	#include <linux/kernel.h>
	22	#include <linux/init.h>
	23	#include <linux/list.h>
d052d1be	24	#include <linux/platform_device.h>
1da177e4 LT	25	#include <linux/slab.h>
1da177e4 LT	26	#include <linux/string.h>
b7808056	27	#include <linux/syscore_ops.h>
a62c80e5 RK	28	#include <linux/amba/bus.h>
a62c80e5 RK	29	#include <linux/amba/kmi.h>
fced80c7	30	#include <linux/io.h>
44fa72d1	31	#include <linux/irqchip.h>
f07e762e	32	#include <linux/mtd/physmap.h>
a613163d	33	#include <linux/platform_data/clk-integrator.h>
4980f9bc LW	34	#include <linux/of_irq.h>
4980f9bc LW	35	#include <linux/of_address.h>
4672cddf	36	#include <linux/of_platform.h>
e67ae6be	37	#include <linux/stat.h>
379df279	38	#include <linux/termios.h>
1da177e4	39
1da177e4	40	#include <asm/setup.h>
4e57b681	41	#include <asm/param.h> /* HZ */
1da177e4	42	#include <asm/mach-types.h>
1da177e4	43
1da177e4	44	#include <asm/mach/arch.h>
1da177e4 LT	45	#include <asm/mach/irq.h>
	46	#include <asm/mach/map.h>
	47	#include <asm/mach/time.h>
	48
1b1ef755	49	#include "hardware.h"
bb4dbefe	50	#include "cm.h"
98c672cf	51	#include "common.h"
ae9daf2d	52	#include "pci_v3.h"
c36928ad	53	#include "lm.h"
98c672cf	54
83feba51	55	/* Base address to the AP system controller */
379df279	56	void __iomem *ap_syscon_base;
307b9667 LW	57	/* Base address to the external bus interface */
307b9667 LW	58	static void __iomem *ebi_base;
83feba51	59
83feba51 LW	60
83feba51 LW	61	/*
1da177e4 LT	62	* All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
	63	* is the (PA >> 12).
	64	*
	65	* Setup a VA for the Integrator interrupt controller (for header #0,
	66	* just for now).
	67	*/
c41b16f8	68	#define VA_IC_BASE __io_address(INTEGRATOR_IC_BASE)
1da177e4 LT	69
	70	/*
	71	* Logical Physical
1da177e4	72	* ef000000 Cache flush
1da177e4	73	* f1100000 11000000 System controller registers
1da177e4 LT	74	* f1300000 13000000 Counter/Timer
	75	* f1400000 14000000 Interrupt controller
	76	* f1600000 16000000 UART 0
	77	* f1700000 17000000 UART 1
	78	* f1a00000 1a000000 Debug LEDs
	79	* f1b00000 1b000000 GPIO
	80	*/
	81
060fd1be	82	static struct map_desc ap_io_desc[] __initdata __maybe_unused = {
c8d27298	83	{
c8d27298 DS	84	.virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
	85	.pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
	86	.length = SZ_4K,
	87	.type = MT_DEVICE
	88	}, {
	89	.virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
	90	.pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
	91	.length = SZ_4K,
	92	.type = MT_DEVICE
c8d27298 DS	93	}, {
	94	.virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
	95	.pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
	96	.length = SZ_4K,
	97	.type = MT_DEVICE
	98	}, {
da7ba956 RK	99	.virtual = IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE),
da7ba956 RK	100	.pfn = __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE),
c8d27298 DS	101	.length = SZ_4K,
c8d27298 DS	102	.type = MT_DEVICE
c8d27298	103	}
1da177e4 LT	104	};
	105
	106	static void __init ap_map_io(void)
	107	{
	108	iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
ae9daf2d	109	pci_v3_early_init();
1da177e4 LT	110	}
1da177e4 LT	111
1da177e4 LT	112	#ifdef CONFIG_PM
	113	static unsigned long ic_irq_enable;
	114
b7808056	115	static int irq_suspend(void)
1da177e4 LT	116	{
	117	ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
	118	return 0;
	119	}
	120
b7808056	121	static void irq_resume(void)
1da177e4 LT	122	{
1da177e4 LT	123	/* disable all irq sources */
bb4dbefe	124	cm_clear_irqs();
1da177e4 LT	125	writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
	126	writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
	127
	128	writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
1da177e4 LT	129	}
	130	#else
	131	#define irq_suspend NULL
	132	#define irq_resume NULL
	133	#endif
	134
b7808056	135	static struct syscore_ops irq_syscore_ops = {
1da177e4 LT	136	.suspend = irq_suspend,
	137	.resume = irq_resume,
	138	};
	139
b7808056	140	static int __init irq_syscore_init(void)
1da177e4	141	{
b7808056 RW	142	register_syscore_ops(&irq_syscore_ops);
	143
	144	return 0;
1da177e4 LT	145	}
1da177e4 LT	146
b7808056	147	device_initcall(irq_syscore_init);
1da177e4 LT	148
	149	/*
	150	* Flash handling.
	151	*/
f07e762e	152	static int ap_flash_init(struct platform_device *dev)
1da177e4 LT	153	{
	154	u32 tmp;
	155
83feba51 LW	156	writel(INTEGRATOR_SC_CTRL_nFLVPPEN \| INTEGRATOR_SC_CTRL_nFLWP,
83feba51 LW	157	ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
1da177e4	158
307b9667 LW	159	tmp = readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) \|
	160	INTEGRATOR_EBI_WRITE_ENABLE;
	161	writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
1da177e4	162
307b9667 LW	163	if (!(readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET)
	164	& INTEGRATOR_EBI_WRITE_ENABLE)) {
	165	writel(0xa05f, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
	166	writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
	167	writel(0, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
1da177e4 LT	168	}
	169	return 0;
	170	}
	171
f07e762e	172	static void ap_flash_exit(struct platform_device *dev)
1da177e4 LT	173	{
	174	u32 tmp;
	175
83feba51 LW	176	writel(INTEGRATOR_SC_CTRL_nFLVPPEN \| INTEGRATOR_SC_CTRL_nFLWP,
83feba51 LW	177	ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
1da177e4	178
307b9667 LW	179	tmp = readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) &
	180	~INTEGRATOR_EBI_WRITE_ENABLE;
	181	writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
1da177e4	182
307b9667 LW	183	if (readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) &
	184	INTEGRATOR_EBI_WRITE_ENABLE) {
	185	writel(0xa05f, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
	186	writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
	187	writel(0, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
1da177e4 LT	188	}
	189	}
	190
667f390b	191	static void ap_flash_set_vpp(struct platform_device *pdev, int on)
1da177e4	192	{
83feba51 LW	193	if (on)
	194	writel(INTEGRATOR_SC_CTRL_nFLVPPEN,
	195	ap_syscon_base + INTEGRATOR_SC_CTRLS_OFFSET);
	196	else
	197	writel(INTEGRATOR_SC_CTRL_nFLVPPEN,
	198	ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
1da177e4 LT	199	}
1da177e4 LT	200
f07e762e	201	static struct physmap_flash_data ap_flash_data = {
1da177e4 LT	202	.width = 4,
	203	.init = ap_flash_init,
	204	.exit = ap_flash_exit,
	205	.set_vpp = ap_flash_set_vpp,
	206	};
	207
379df279 LW	208	/*
	209	* For the PL010 found in the Integrator/AP some of the UART control is
	210	* implemented in the system controller and accessed using a callback
	211	* from the driver.
	212	*/
	213	static void integrator_uart_set_mctrl(struct amba_device *dev,
	214	void __iomem *base, unsigned int mctrl)
	215	{
	216	unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask;
	217	u32 phybase = dev->res.start;
	218
	219	if (phybase == INTEGRATOR_UART0_BASE) {
	220	/* UART0 */
	221	rts_mask = 1 << 4;
	222	dtr_mask = 1 << 5;
	223	} else {
	224	/* UART1 */
	225	rts_mask = 1 << 6;
	226	dtr_mask = 1 << 7;
	227	}
	228
	229	if (mctrl & TIOCM_RTS)
	230	ctrlc \|= rts_mask;
	231	else
	232	ctrls \|= rts_mask;
	233
	234	if (mctrl & TIOCM_DTR)
	235	ctrlc \|= dtr_mask;
	236	else
	237	ctrls \|= dtr_mask;
	238
	239	__raw_writel(ctrls, ap_syscon_base + INTEGRATOR_SC_CTRLS_OFFSET);
	240	__raw_writel(ctrlc, ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
	241	}
	242
	243	struct amba_pl010_data ap_uart_data = {
	244	.set_mctrl = integrator_uart_set_mctrl,
	245	};
	246
a613163d LW	247	void __init ap_init_early(void)
	248	{
	249	}
	250
4980f9bc LW	251	static void __init ap_init_irq_of(void)
4980f9bc LW	252	{
bb4dbefe	253	cm_init();
44fa72d1	254	irqchip_init();
4980f9bc LW	255	}
4980f9bc LW	256
4672cddf LW	257	/* For the Device Tree, add in the UART callbacks as AUXDATA */
	258	static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = {
	259	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
	260	"rtc", NULL),
	261	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
379df279	262	"uart0", &ap_uart_data),
4672cddf	263	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
379df279	264	"uart1", &ap_uart_data),
4672cddf LW	265	OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
	266	"kmi0", NULL),
	267	OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
	268	"kmi1", NULL),
73efd530 LW	269	OF_DEV_AUXDATA("cfi-flash", INTEGRATOR_FLASH_BASE,
73efd530 LW	270	"physmap-flash", &ap_flash_data),
4672cddf LW	271	{ /* sentinel */ },
	272	};
	273
df36680f LW	274	static const struct of_device_id ap_syscon_match[] = {
	275	{ .compatible = "arm,integrator-ap-syscon"},
	276	{ },
	277	};
	278
307b9667 LW	279	static const struct of_device_id ebi_match[] = {
	280	{ .compatible = "arm,external-bus-interface"},
	281	{ },
	282	};
	283
4672cddf LW	284	static void __init ap_init_of(void)
	285	{
	286	unsigned long sc_dec;
e67ae6be	287	struct device_node *syscon;
307b9667	288	struct device_node *ebi;
4672cddf LW	289	int i;
4672cddf LW	290
11f9323a	291	syscon = of_find_matching_node(NULL, ap_syscon_match);
e67ae6be LW	292	if (!syscon)
e67ae6be LW	293	return;
11f9323a	294	ebi = of_find_matching_node(NULL, ebi_match);
307b9667 LW	295	if (!ebi)
307b9667 LW	296	return;
e67ae6be LW	297
	298	ap_syscon_base = of_iomap(syscon, 0);
	299	if (!ap_syscon_base)
	300	return;
307b9667 LW	301	ebi_base = of_iomap(ebi, 0);
	302	if (!ebi_base)
	303	return;
e67ae6be	304
11f9323a LW	305	of_platform_populate(NULL, of_default_bus_match_table,
	306	ap_auxdata_lookup, NULL);
	307
83feba51	308	sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET);
4672cddf LW	309	for (i = 0; i < 4; i++) {
	310	struct lm_device *lmdev;
	311
	312	if ((sc_dec & (16 << i)) == 0)
	313	continue;
	314
	315	lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
	316	if (!lmdev)
	317	continue;
	318
	319	lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
	320	lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
	321	lmdev->resource.flags = IORESOURCE_MEM;
a6720258	322	lmdev->irq = irq_of_parse_and_map(syscon, i);
4672cddf LW	323	lmdev->id = i;
	324
	325	lm_device_register(lmdev);
	326	}
	327	}
	328
4980f9bc LW	329	static const char * ap_dt_board_compat[] = {
	330	"arm,integrator-ap",
	331	NULL,
	332	};
	333
	334	DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
	335	.reserve = integrator_reserve,
	336	.map_io = ap_map_io,
4980f9bc LW	337	.init_early = ap_init_early,
4980f9bc LW	338	.init_irq = ap_init_irq_of,
4672cddf	339	.init_machine = ap_init_of,
4980f9bc LW	340	.dt_compat = ap_dt_board_compat,
4980f9bc LW	341	MACHINE_END