[deliverable/linux.git] / arch / arm / mach-integrator / integrator_ap.c

/*
 *  linux/arch/arm/mach-integrator/integrator_ap.c
 *
 *  Copyright (C) 2000-2003 Deep Blue Solutions Ltd
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/syscore_ops.h>
#include <linux/amba/bus.h>
#include <linux/amba/kmi.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irqchip/versatile-fpga.h>
#include <linux/mtd/physmap.h>
#include <linux/clk.h>
#include <linux/platform_data/clk-integrator.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/stat.h>
#include <linux/sys_soc.h>
#include <linux/termios.h>
#include <linux/sched_clock.h>

#include <mach/hardware.h>
#include <mach/platform.h>
#include <asm/hardware/arm_timer.h>
#include <asm/setup.h>
#include <asm/param.h>		/* HZ */
#include <asm/mach-types.h>

#include <mach/lm.h>

#include <asm/mach/arch.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>

#include "cm.h"
#include "common.h"
#include "pci_v3.h"

/* Base address to the AP system controller */
void __iomem *ap_syscon_base;

/*
 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
 * is the (PA >> 12).
 *
 * Setup a VA for the Integrator interrupt controller (for header #0,
 * just for now).
 */
#define VA_IC_BASE	__io_address(INTEGRATOR_IC_BASE)
#define VA_EBI_BASE	__io_address(INTEGRATOR_EBI_BASE)
#define VA_CMIC_BASE	__io_address(INTEGRATOR_HDR_IC)

/*
 * Logical      Physical
 * ef000000			Cache flush
 * f1000000	10000000	Core module registers
 * f1100000	11000000	System controller registers
 * f1200000	12000000	EBI registers
 * f1300000	13000000	Counter/Timer
 * f1400000	14000000	Interrupt controller
 * f1600000	16000000	UART 0
 * f1700000	17000000	UART 1
 * f1a00000	1a000000	Debug LEDs
 * f1b00000	1b000000	GPIO
 */

static struct map_desc ap_io_desc[] __initdata __maybe_unused = {
	{
		.virtual	= IO_ADDRESS(INTEGRATOR_HDR_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_HDR_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_EBI_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_EBI_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_CT_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_CT_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_IC_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_IC_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_UART0_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_UART0_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_DBG_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_DBG_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}
};

static void __init ap_map_io(void)
{
	iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
	pci_v3_early_init();
}

#ifdef CONFIG_PM
static unsigned long ic_irq_enable;

static int irq_suspend(void)
{
	ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
	return 0;
}

static void irq_resume(void)
{
	/* disable all irq sources */
	cm_clear_irqs();
	writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
	writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);

	writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
}
#else
#define irq_suspend NULL
#define irq_resume NULL
#endif

static struct syscore_ops irq_syscore_ops = {
	.suspend	= irq_suspend,
	.resume		= irq_resume,
};

static int __init irq_syscore_init(void)
{
	register_syscore_ops(&irq_syscore_ops);

	return 0;
}

device_initcall(irq_syscore_init);

/*
 * Flash handling.
 */
#define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
#define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)

static int ap_flash_init(struct platform_device *dev)
{
	u32 tmp;

	writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP,
	       ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);

	tmp = readl(EBI_CSR1) | INTEGRATOR_EBI_WRITE_ENABLE;
	writel(tmp, EBI_CSR1);

	if (!(readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) {
		writel(0xa05f, EBI_LOCK);
		writel(tmp, EBI_CSR1);
		writel(0, EBI_LOCK);
	}
	return 0;
}

static void ap_flash_exit(struct platform_device *dev)
{
	u32 tmp;

	writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP,
	       ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);

	tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE;
	writel(tmp, EBI_CSR1);

	if (readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) {
		writel(0xa05f, EBI_LOCK);
		writel(tmp, EBI_CSR1);
		writel(0, EBI_LOCK);
	}
}

static void ap_flash_set_vpp(struct platform_device *pdev, int on)
{
	if (on)
		writel(INTEGRATOR_SC_CTRL_nFLVPPEN,
		       ap_syscon_base + INTEGRATOR_SC_CTRLS_OFFSET);
	else
		writel(INTEGRATOR_SC_CTRL_nFLVPPEN,
		       ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
}

static struct physmap_flash_data ap_flash_data = {
	.width		= 4,
	.init		= ap_flash_init,
	.exit		= ap_flash_exit,
	.set_vpp	= ap_flash_set_vpp,
};

/*
 * For the PL010 found in the Integrator/AP some of the UART control is
 * implemented in the system controller and accessed using a callback
 * from the driver.
 */
static void integrator_uart_set_mctrl(struct amba_device *dev,
				void __iomem *base, unsigned int mctrl)
{
	unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask;
	u32 phybase = dev->res.start;

	if (phybase == INTEGRATOR_UART0_BASE) {
		/* UART0 */
		rts_mask = 1 << 4;
		dtr_mask = 1 << 5;
	} else {
		/* UART1 */
		rts_mask = 1 << 6;
		dtr_mask = 1 << 7;
	}

	if (mctrl & TIOCM_RTS)
		ctrlc |= rts_mask;
	else
		ctrls |= rts_mask;

	if (mctrl & TIOCM_DTR)
		ctrlc |= dtr_mask;
	else
		ctrls |= dtr_mask;

	__raw_writel(ctrls, ap_syscon_base + INTEGRATOR_SC_CTRLS_OFFSET);
	__raw_writel(ctrlc, ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
}

struct amba_pl010_data ap_uart_data = {
	.set_mctrl = integrator_uart_set_mctrl,
};

/*
 * Where is the timer (VA)?
 */
#define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
#define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
#define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)

static unsigned long timer_reload;

static u32 notrace integrator_read_sched_clock(void)
{
	return -readl((void __iomem *) TIMER2_VA_BASE + TIMER_VALUE);
}

static void integrator_clocksource_init(unsigned long inrate,
					void __iomem *base)
{
	u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC;
	unsigned long rate = inrate;

	if (rate >= 1500000) {
		rate /= 16;
		ctrl |= TIMER_CTRL_DIV16;
	}

	writel(0xffff, base + TIMER_LOAD);
	writel(ctrl, base + TIMER_CTRL);

	clocksource_mmio_init(base + TIMER_VALUE, "timer2",
			rate, 200, 16, clocksource_mmio_readl_down);
	setup_sched_clock(integrator_read_sched_clock, 16, rate);
}

static void __iomem * clkevt_base;

/*
 * IRQ handler for the timer
 */
static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	/* clear the interrupt */
	writel(1, clkevt_base + TIMER_INTCLR);

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
{
	u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;

	/* Disable timer */
	writel(ctrl, clkevt_base + TIMER_CTRL);

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		/* Enable the timer and start the periodic tick */
		writel(timer_reload, clkevt_base + TIMER_LOAD);
		ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
		writel(ctrl, clkevt_base + TIMER_CTRL);
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		/* Leave the timer disabled, .set_next_event will enable it */
		ctrl &= ~TIMER_CTRL_PERIODIC;
		writel(ctrl, clkevt_base + TIMER_CTRL);
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_RESUME:
	default:
		/* Just leave in disabled state */
		break;
	}

}

static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt)
{
	unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);

	writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
	writel(next, clkevt_base + TIMER_LOAD);
	writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);

	return 0;
}

static struct clock_event_device integrator_clockevent = {
	.name		= "timer1",
	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.set_mode	= clkevt_set_mode,
	.set_next_event	= clkevt_set_next_event,
	.rating		= 300,
};

static struct irqaction integrator_timer_irq = {
	.name		= "timer",
	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= integrator_timer_interrupt,
	.dev_id		= &integrator_clockevent,
};

static void integrator_clockevent_init(unsigned long inrate,
				void __iomem *base, int irq)
{
	unsigned long rate = inrate;
	unsigned int ctrl = 0;

	clkevt_base = base;
	/* Calculate and program a divisor */
	if (rate > 0x100000 * HZ) {
		rate /= 256;
		ctrl |= TIMER_CTRL_DIV256;
	} else if (rate > 0x10000 * HZ) {
		rate /= 16;
		ctrl |= TIMER_CTRL_DIV16;
	}
	timer_reload = rate / HZ;
	writel(ctrl, clkevt_base + TIMER_CTRL);

	setup_irq(irq, &integrator_timer_irq);
	clockevents_config_and_register(&integrator_clockevent,
					rate,
					1,
					0xffffU);
}

void __init ap_init_early(void)
{
}

static void __init ap_of_timer_init(void)
{
	struct device_node *node;
	const char *path;
	void __iomem *base;
	int err;
	int irq;
	struct clk *clk;
	unsigned long rate;

	clk = clk_get_sys("ap_timer", NULL);
	BUG_ON(IS_ERR(clk));
	clk_prepare_enable(clk);
	rate = clk_get_rate(clk);

	err = of_property_read_string(of_aliases,
				"arm,timer-primary", &path);
	if (WARN_ON(err))
		return;
	node = of_find_node_by_path(path);
	base = of_iomap(node, 0);
	if (WARN_ON(!base))
		return;
	writel(0, base + TIMER_CTRL);
	integrator_clocksource_init(rate, base);

	err = of_property_read_string(of_aliases,
				"arm,timer-secondary", &path);
	if (WARN_ON(err))
		return;
	node = of_find_node_by_path(path);
	base = of_iomap(node, 0);
	if (WARN_ON(!base))
		return;
	irq = irq_of_parse_and_map(node, 0);
	writel(0, base + TIMER_CTRL);
	integrator_clockevent_init(rate, base, irq);
}

static const struct of_device_id fpga_irq_of_match[] __initconst = {
	{ .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
	{ /* Sentinel */ }
};

static void __init ap_init_irq_of(void)
{
	cm_init();
	of_irq_init(fpga_irq_of_match);
	integrator_clk_init(false);
}

/* For the Device Tree, add in the UART callbacks as AUXDATA */
static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = {
	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
		"rtc", NULL),
	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
		"uart0", &ap_uart_data),
	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
		"uart1", &ap_uart_data),
	OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
		"kmi0", NULL),
	OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
		"kmi1", NULL),
	OF_DEV_AUXDATA("cfi-flash", INTEGRATOR_FLASH_BASE,
		"physmap-flash", &ap_flash_data),
	{ /* sentinel */ },
};

static const struct of_device_id ap_syscon_match[] = {
	{ .compatible = "arm,integrator-ap-syscon"},
	{ },
};

static void __init ap_init_of(void)
{
	unsigned long sc_dec;
	struct device_node *root;
	struct device_node *syscon;
	struct device *parent;
	struct soc_device *soc_dev;
	struct soc_device_attribute *soc_dev_attr;
	u32 ap_sc_id;
	int err;
	int i;

	/* Here we create an SoC device for the root node */
	root = of_find_node_by_path("/");
	if (!root)
		return;

	syscon = of_find_matching_node(root, ap_syscon_match);
	if (!syscon)
		return;

	ap_syscon_base = of_iomap(syscon, 0);
	if (!ap_syscon_base)
		return;

	ap_sc_id = readl(ap_syscon_base);

	soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
	if (!soc_dev_attr)
		return;

	err = of_property_read_string(root, "compatible",
				      &soc_dev_attr->soc_id);
	if (err)
		return;
	err = of_property_read_string(root, "model", &soc_dev_attr->machine);
	if (err)
		return;
	soc_dev_attr->family = "Integrator";
	soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c",
					   'A' + (ap_sc_id & 0x0f));

	soc_dev = soc_device_register(soc_dev_attr);
	if (IS_ERR(soc_dev)) {
		kfree(soc_dev_attr->revision);
		kfree(soc_dev_attr);
		return;
	}

	parent = soc_device_to_device(soc_dev);
	integrator_init_sysfs(parent, ap_sc_id);

	of_platform_populate(root, of_default_bus_match_table,
			ap_auxdata_lookup, parent);

	sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET);
	for (i = 0; i < 4; i++) {
		struct lm_device *lmdev;

		if ((sc_dec & (16 << i)) == 0)
			continue;

		lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
		if (!lmdev)
			continue;

		lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
		lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
		lmdev->resource.flags = IORESOURCE_MEM;
		lmdev->irq = irq_of_parse_and_map(syscon, i);
		lmdev->id = i;

		lm_device_register(lmdev);
	}
}

static const char * ap_dt_board_compat[] = {
	"arm,integrator-ap",
	NULL,
};

DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
	.reserve	= integrator_reserve,
	.map_io		= ap_map_io,
	.init_early	= ap_init_early,
	.init_irq	= ap_init_irq_of,
	.handle_irq	= fpga_handle_irq,
	.init_time	= ap_of_timer_init,
	.init_machine	= ap_init_of,
	.restart	= integrator_restart,
	.dt_compat      = ap_dt_board_compat,
MACHINE_END
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-integrator/integrator_ap.c
	3	*
	4	* Copyright (C) 2000-2003 Deep Blue Solutions Ltd
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20	#include <linux/types.h>
	21	#include <linux/kernel.h>
	22	#include <linux/init.h>
	23	#include <linux/list.h>
d052d1be	24	#include <linux/platform_device.h>
1da177e4 LT	25	#include <linux/slab.h>
1da177e4 LT	26	#include <linux/string.h>
b7808056	27	#include <linux/syscore_ops.h>
a62c80e5 RK	28	#include <linux/amba/bus.h>
a62c80e5 RK	29	#include <linux/amba/kmi.h>
6be4826e RK	30	#include <linux/clocksource.h>
	31	#include <linux/clockchips.h>
	32	#include <linux/interrupt.h>
fced80c7	33	#include <linux/io.h>
2389d501	34	#include <linux/irqchip/versatile-fpga.h>
f07e762e	35	#include <linux/mtd/physmap.h>
bb76079a	36	#include <linux/clk.h>
a613163d	37	#include <linux/platform_data/clk-integrator.h>
4980f9bc LW	38	#include <linux/of_irq.h>
4980f9bc LW	39	#include <linux/of_address.h>
4672cddf	40	#include <linux/of_platform.h>
e67ae6be LW	41	#include <linux/stat.h>
e67ae6be LW	42	#include <linux/sys_soc.h>
379df279	43	#include <linux/termios.h>
38ff87f7	44	#include <linux/sched_clock.h>
1da177e4	45
a09e64fb	46	#include <mach/hardware.h>
a285edcf	47	#include <mach/platform.h>
6be4826e	48	#include <asm/hardware/arm_timer.h>
1da177e4	49	#include <asm/setup.h>
4e57b681	50	#include <asm/param.h> /* HZ */
1da177e4	51	#include <asm/mach-types.h>
1da177e4	52
a09e64fb	53	#include <mach/lm.h>
1da177e4 LT	54
1da177e4 LT	55	#include <asm/mach/arch.h>
1da177e4 LT	56	#include <asm/mach/irq.h>
	57	#include <asm/mach/map.h>
	58	#include <asm/mach/time.h>
	59
bb4dbefe	60	#include "cm.h"
98c672cf	61	#include "common.h"
ae9daf2d	62	#include "pci_v3.h"
98c672cf	63
83feba51	64	/* Base address to the AP system controller */
379df279	65	void __iomem *ap_syscon_base;
83feba51 LW	66
83feba51 LW	67	/*
1da177e4 LT	68	* All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
	69	* is the (PA >> 12).
	70	*
	71	* Setup a VA for the Integrator interrupt controller (for header #0,
	72	* just for now).
	73	*/
c41b16f8	74	#define VA_IC_BASE __io_address(INTEGRATOR_IC_BASE)
c41b16f8 RK	75	#define VA_EBI_BASE __io_address(INTEGRATOR_EBI_BASE)
c41b16f8 RK	76	#define VA_CMIC_BASE __io_address(INTEGRATOR_HDR_IC)
1da177e4 LT	77
	78	/*
	79	* Logical Physical
1da177e4 LT	80	* ef000000 Cache flush
	81	* f1000000 10000000 Core module registers
	82	* f1100000 11000000 System controller registers
	83	* f1200000 12000000 EBI registers
	84	* f1300000 13000000 Counter/Timer
	85	* f1400000 14000000 Interrupt controller
	86	* f1600000 16000000 UART 0
	87	* f1700000 17000000 UART 1
	88	* f1a00000 1a000000 Debug LEDs
	89	* f1b00000 1b000000 GPIO
	90	*/
	91
060fd1be	92	static struct map_desc ap_io_desc[] __initdata __maybe_unused = {
c8d27298 DS	93	{
	94	.virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
	95	.pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE),
	96	.length = SZ_4K,
	97	.type = MT_DEVICE
c8d27298 DS	98	}, {
	99	.virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE),
	100	.pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE),
	101	.length = SZ_4K,
	102	.type = MT_DEVICE
	103	}, {
	104	.virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
	105	.pfn = __phys_to_pfn(INTEGRATOR_CT_BASE),
	106	.length = SZ_4K,
	107	.type = MT_DEVICE
	108	}, {
	109	.virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
	110	.pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
	111	.length = SZ_4K,
	112	.type = MT_DEVICE
	113	}, {
	114	.virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
	115	.pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
	116	.length = SZ_4K,
	117	.type = MT_DEVICE
c8d27298 DS	118	}, {
	119	.virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
	120	.pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
	121	.length = SZ_4K,
	122	.type = MT_DEVICE
	123	}, {
da7ba956 RK	124	.virtual = IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE),
da7ba956 RK	125	.pfn = __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE),
c8d27298 DS	126	.length = SZ_4K,
c8d27298 DS	127	.type = MT_DEVICE
c8d27298	128	}
1da177e4 LT	129	};
	130
	131	static void __init ap_map_io(void)
	132	{
	133	iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
ae9daf2d	134	pci_v3_early_init();
1da177e4 LT	135	}
1da177e4 LT	136
1da177e4 LT	137	#ifdef CONFIG_PM
	138	static unsigned long ic_irq_enable;
	139
b7808056	140	static int irq_suspend(void)
1da177e4 LT	141	{
	142	ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
	143	return 0;
	144	}
	145
b7808056	146	static void irq_resume(void)
1da177e4 LT	147	{
1da177e4 LT	148	/* disable all irq sources */
bb4dbefe	149	cm_clear_irqs();
1da177e4 LT	150	writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
	151	writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
	152
	153	writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
1da177e4 LT	154	}
	155	#else
	156	#define irq_suspend NULL
	157	#define irq_resume NULL
	158	#endif
	159
b7808056	160	static struct syscore_ops irq_syscore_ops = {
1da177e4 LT	161	.suspend = irq_suspend,
	162	.resume = irq_resume,
	163	};
	164
b7808056	165	static int __init irq_syscore_init(void)
1da177e4	166	{
b7808056 RW	167	register_syscore_ops(&irq_syscore_ops);
	168
	169	return 0;
1da177e4 LT	170	}
1da177e4 LT	171
b7808056	172	device_initcall(irq_syscore_init);
1da177e4 LT	173
	174	/*
	175	* Flash handling.
	176	*/
1da177e4 LT	177	#define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
	178	#define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
	179
f07e762e	180	static int ap_flash_init(struct platform_device *dev)
1da177e4 LT	181	{
	182	u32 tmp;
	183
83feba51 LW	184	writel(INTEGRATOR_SC_CTRL_nFLVPPEN \| INTEGRATOR_SC_CTRL_nFLWP,
83feba51 LW	185	ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
1da177e4 LT	186
	187	tmp = readl(EBI_CSR1) \| INTEGRATOR_EBI_WRITE_ENABLE;
	188	writel(tmp, EBI_CSR1);
	189
	190	if (!(readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) {
	191	writel(0xa05f, EBI_LOCK);
	192	writel(tmp, EBI_CSR1);
	193	writel(0, EBI_LOCK);
	194	}
	195	return 0;
	196	}
	197
f07e762e	198	static void ap_flash_exit(struct platform_device *dev)
1da177e4 LT	199	{
	200	u32 tmp;
	201
83feba51 LW	202	writel(INTEGRATOR_SC_CTRL_nFLVPPEN \| INTEGRATOR_SC_CTRL_nFLWP,
83feba51 LW	203	ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
1da177e4 LT	204
	205	tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE;
	206	writel(tmp, EBI_CSR1);
	207
	208	if (readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) {
	209	writel(0xa05f, EBI_LOCK);
	210	writel(tmp, EBI_CSR1);
	211	writel(0, EBI_LOCK);
	212	}
	213	}
	214
667f390b	215	static void ap_flash_set_vpp(struct platform_device *pdev, int on)
1da177e4	216	{
83feba51 LW	217	if (on)
	218	writel(INTEGRATOR_SC_CTRL_nFLVPPEN,
	219	ap_syscon_base + INTEGRATOR_SC_CTRLS_OFFSET);
	220	else
	221	writel(INTEGRATOR_SC_CTRL_nFLVPPEN,
	222	ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
1da177e4 LT	223	}
1da177e4 LT	224
f07e762e	225	static struct physmap_flash_data ap_flash_data = {
1da177e4 LT	226	.width = 4,
	227	.init = ap_flash_init,
	228	.exit = ap_flash_exit,
	229	.set_vpp = ap_flash_set_vpp,
	230	};
	231
379df279 LW	232	/*
	233	* For the PL010 found in the Integrator/AP some of the UART control is
	234	* implemented in the system controller and accessed using a callback
	235	* from the driver.
	236	*/
	237	static void integrator_uart_set_mctrl(struct amba_device *dev,
	238	void __iomem *base, unsigned int mctrl)
	239	{
	240	unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask;
	241	u32 phybase = dev->res.start;
	242
	243	if (phybase == INTEGRATOR_UART0_BASE) {
	244	/* UART0 */
	245	rts_mask = 1 << 4;
	246	dtr_mask = 1 << 5;
	247	} else {
	248	/* UART1 */
	249	rts_mask = 1 << 6;
	250	dtr_mask = 1 << 7;
	251	}
	252
	253	if (mctrl & TIOCM_RTS)
	254	ctrlc \|= rts_mask;
	255	else
	256	ctrls \|= rts_mask;
	257
	258	if (mctrl & TIOCM_DTR)
	259	ctrlc \|= dtr_mask;
	260	else
	261	ctrls \|= dtr_mask;
	262
	263	__raw_writel(ctrls, ap_syscon_base + INTEGRATOR_SC_CTRLS_OFFSET);
	264	__raw_writel(ctrlc, ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
	265	}
	266
	267	struct amba_pl010_data ap_uart_data = {
	268	.set_mctrl = integrator_uart_set_mctrl,
	269	};
	270
6be4826e RK	271	/*
	272	* Where is the timer (VA)?
	273	*/
b7a3f8db AB	274	#define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
	275	#define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
	276	#define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)
6be4826e	277
6be4826e RK	278	static unsigned long timer_reload;
6be4826e RK	279
a9d6d151 LW	280	static u32 notrace integrator_read_sched_clock(void)
	281	{
	282	return -readl((void __iomem *) TIMER2_VA_BASE + TIMER_VALUE);
	283	}
	284
4980f9bc LW	285	static void integrator_clocksource_init(unsigned long inrate,
4980f9bc LW	286	void __iomem *base)
6be4826e	287	{
bb9ea778	288	u32 ctrl = TIMER_CTRL_ENABLE \| TIMER_CTRL_PERIODIC;
bb76079a	289	unsigned long rate = inrate;
6be4826e	290
bb76079a LW	291	if (rate >= 1500000) {
bb76079a LW	292	rate /= 16;
bb9ea778	293	ctrl \|= TIMER_CTRL_DIV16;
6be4826e RK	294	}
6be4826e RK	295
6be4826e	296	writel(0xffff, base + TIMER_LOAD);
bb9ea778	297	writel(ctrl, base + TIMER_CTRL);
6be4826e	298
c5039f52	299	clocksource_mmio_init(base + TIMER_VALUE, "timer2",
bb76079a	300	rate, 200, 16, clocksource_mmio_readl_down);
a9d6d151	301	setup_sched_clock(integrator_read_sched_clock, 16, rate);
6be4826e RK	302	}
6be4826e RK	303
4980f9bc	304	static void __iomem * clkevt_base;
6be4826e RK	305
	306	/*
	307	* IRQ handler for the timer
	308	*/
	309	static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id)
	310	{
	311	struct clock_event_device *evt = dev_id;
	312
	313	/* clear the interrupt */
	314	writel(1, clkevt_base + TIMER_INTCLR);
	315
	316	evt->event_handler(evt);
	317
	318	return IRQ_HANDLED;
	319	}
	320
	321	static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
	322	{
	323	u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
	324
02f56321 LW	325	/* Disable timer */
02f56321 LW	326	writel(ctrl, clkevt_base + TIMER_CTRL);
6be4826e	327
02f56321 LW	328	switch (mode) {
	329	case CLOCK_EVT_MODE_PERIODIC:
	330	/* Enable the timer and start the periodic tick */
6be4826e RK	331	writel(timer_reload, clkevt_base + TIMER_LOAD);
6be4826e RK	332	ctrl \|= TIMER_CTRL_PERIODIC \| TIMER_CTRL_ENABLE;
02f56321 LW	333	writel(ctrl, clkevt_base + TIMER_CTRL);
	334	break;
	335	case CLOCK_EVT_MODE_ONESHOT:
	336	/* Leave the timer disabled, .set_next_event will enable it */
	337	ctrl &= ~TIMER_CTRL_PERIODIC;
	338	writel(ctrl, clkevt_base + TIMER_CTRL);
	339	break;
	340	case CLOCK_EVT_MODE_UNUSED:
	341	case CLOCK_EVT_MODE_SHUTDOWN:
	342	case CLOCK_EVT_MODE_RESUME:
	343	default:
	344	/* Just leave in disabled state */
	345	break;
6be4826e RK	346	}
6be4826e RK	347
6be4826e RK	348	}
	349
	350	static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt)
	351	{
	352	unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
	353
	354	writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
	355	writel(next, clkevt_base + TIMER_LOAD);
	356	writel(ctrl \| TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
	357
	358	return 0;
	359	}
	360
	361	static struct clock_event_device integrator_clockevent = {
	362	.name = "timer1",
02f56321	363	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
6be4826e RK	364	.set_mode = clkevt_set_mode,
	365	.set_next_event = clkevt_set_next_event,
	366	.rating = 300,
6be4826e RK	367	};
	368
	369	static struct irqaction integrator_timer_irq = {
	370	.name = "timer",
	371	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL,
	372	.handler = integrator_timer_interrupt,
	373	.dev_id = &integrator_clockevent,
	374	};
	375
4980f9bc LW	376	static void integrator_clockevent_init(unsigned long inrate,
4980f9bc LW	377	void __iomem *base, int irq)
6be4826e	378	{
bb76079a	379	unsigned long rate = inrate;
6be4826e RK	380	unsigned int ctrl = 0;
6be4826e RK	381
4980f9bc	382	clkevt_base = base;
6d8ce712	383	/* Calculate and program a divisor */
bb76079a LW	384	if (rate > 0x100000 * HZ) {
bb76079a LW	385	rate /= 256;
6be4826e	386	ctrl \|= TIMER_CTRL_DIV256;
bb76079a LW	387	} else if (rate > 0x10000 * HZ) {
bb76079a LW	388	rate /= 16;
6be4826e RK	389	ctrl \|= TIMER_CTRL_DIV16;
6be4826e RK	390	}
bb76079a	391	timer_reload = rate / HZ;
6be4826e RK	392	writel(ctrl, clkevt_base + TIMER_CTRL);
6be4826e RK	393
4980f9bc	394	setup_irq(irq, &integrator_timer_irq);
6d8ce712	395	clockevents_config_and_register(&integrator_clockevent,
bb76079a	396	rate,
6d8ce712 LW	397	1,
6d8ce712 LW	398	0xffffU);
6be4826e RK	399	}
6be4826e RK	400
a613163d LW	401	void __init ap_init_early(void)
	402	{
	403	}
	404
6bb27d73	405	static void __init ap_of_timer_init(void)
4980f9bc LW	406	{
	407	struct device_node *node;
	408	const char *path;
	409	void __iomem *base;
	410	int err;
	411	int irq;
	412	struct clk *clk;
	413	unsigned long rate;
	414
	415	clk = clk_get_sys("ap_timer", NULL);
	416	BUG_ON(IS_ERR(clk));
	417	clk_prepare_enable(clk);
	418	rate = clk_get_rate(clk);
	419
	420	err = of_property_read_string(of_aliases,
	421	"arm,timer-primary", &path);
	422	if (WARN_ON(err))
	423	return;
	424	node = of_find_node_by_path(path);
	425	base = of_iomap(node, 0);
	426	if (WARN_ON(!base))
	427	return;
	428	writel(0, base + TIMER_CTRL);
	429	integrator_clocksource_init(rate, base);
	430
	431	err = of_property_read_string(of_aliases,
	432	"arm,timer-secondary", &path);
	433	if (WARN_ON(err))
	434	return;
	435	node = of_find_node_by_path(path);
	436	base = of_iomap(node, 0);
	437	if (WARN_ON(!base))
	438	return;
	439	irq = irq_of_parse_and_map(node, 0);
	440	writel(0, base + TIMER_CTRL);
	441	integrator_clockevent_init(rate, base, irq);
	442	}
	443
4980f9bc LW	444	static const struct of_device_id fpga_irq_of_match[] __initconst = {
	445	{ .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
	446	{ /* Sentinel */ }
	447	};
	448
	449	static void __init ap_init_irq_of(void)
	450	{
bb4dbefe	451	cm_init();
4980f9bc LW	452	of_irq_init(fpga_irq_of_match);
	453	integrator_clk_init(false);
	454	}
	455
4672cddf LW	456	/* For the Device Tree, add in the UART callbacks as AUXDATA */
	457	static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = {
	458	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
	459	"rtc", NULL),
	460	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
379df279	461	"uart0", &ap_uart_data),
4672cddf	462	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
379df279	463	"uart1", &ap_uart_data),
4672cddf LW	464	OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
	465	"kmi0", NULL),
	466	OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
	467	"kmi1", NULL),
73efd530 LW	468	OF_DEV_AUXDATA("cfi-flash", INTEGRATOR_FLASH_BASE,
73efd530 LW	469	"physmap-flash", &ap_flash_data),
4672cddf LW	470	{ /* sentinel */ },
	471	};
	472
df36680f LW	473	static const struct of_device_id ap_syscon_match[] = {
	474	{ .compatible = "arm,integrator-ap-syscon"},
	475	{ },
	476	};
	477
4672cddf LW	478	static void __init ap_init_of(void)
	479	{
	480	unsigned long sc_dec;
e67ae6be LW	481	struct device_node *root;
	482	struct device_node *syscon;
	483	struct device *parent;
	484	struct soc_device *soc_dev;
	485	struct soc_device_attribute *soc_dev_attr;
	486	u32 ap_sc_id;
	487	int err;
4672cddf LW	488	int i;
4672cddf LW	489
e67ae6be LW	490	/* Here we create an SoC device for the root node */
	491	root = of_find_node_by_path("/");
	492	if (!root)
	493	return;
df36680f LW	494
df36680f LW	495	syscon = of_find_matching_node(root, ap_syscon_match);
e67ae6be LW	496	if (!syscon)
	497	return;
	498
	499	ap_syscon_base = of_iomap(syscon, 0);
	500	if (!ap_syscon_base)
	501	return;
	502
	503	ap_sc_id = readl(ap_syscon_base);
	504
	505	soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
	506	if (!soc_dev_attr)
	507	return;
	508
	509	err = of_property_read_string(root, "compatible",
	510	&soc_dev_attr->soc_id);
	511	if (err)
	512	return;
	513	err = of_property_read_string(root, "model", &soc_dev_attr->machine);
	514	if (err)
	515	return;
	516	soc_dev_attr->family = "Integrator";
	517	soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c",
	518	'A' + (ap_sc_id & 0x0f));
	519
	520	soc_dev = soc_device_register(soc_dev_attr);
b269b170	521	if (IS_ERR(soc_dev)) {
e67ae6be LW	522	kfree(soc_dev_attr->revision);
	523	kfree(soc_dev_attr);
	524	return;
	525	}
	526
	527	parent = soc_device_to_device(soc_dev);
b269b170	528	integrator_init_sysfs(parent, ap_sc_id);
e67ae6be LW	529
	530	of_platform_populate(root, of_default_bus_match_table,
	531	ap_auxdata_lookup, parent);
4672cddf	532
83feba51	533	sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET);
4672cddf LW	534	for (i = 0; i < 4; i++) {
	535	struct lm_device *lmdev;
	536
	537	if ((sc_dec & (16 << i)) == 0)
	538	continue;
	539
	540	lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
	541	if (!lmdev)
	542	continue;
	543
	544	lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
	545	lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
	546	lmdev->resource.flags = IORESOURCE_MEM;
a6720258	547	lmdev->irq = irq_of_parse_and_map(syscon, i);
4672cddf LW	548	lmdev->id = i;
	549
	550	lm_device_register(lmdev);
	551	}
	552	}
	553
4980f9bc LW	554	static const char * ap_dt_board_compat[] = {
	555	"arm,integrator-ap",
	556	NULL,
	557	};
	558
	559	DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
	560	.reserve = integrator_reserve,
	561	.map_io = ap_map_io,
4980f9bc LW	562	.init_early = ap_init_early,
	563	.init_irq = ap_init_irq_of,
	564	.handle_irq = fpga_handle_irq,
6bb27d73	565	.init_time = ap_of_timer_init,
4672cddf	566	.init_machine = ap_init_of,
4980f9bc LW	567	.restart = integrator_restart,
	568	.dt_compat = ap_dt_board_compat,
	569	MACHINE_END