[deliverable/linux.git] / arch / arm / mach-integrator / integrator_ap.c

/*
 *  linux/arch/arm/mach-integrator/integrator_ap.c
 *
 *  Copyright (C) 2000-2003 Deep Blue Solutions Ltd
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/syscore_ops.h>
#include <linux/amba/bus.h>
#include <linux/amba/kmi.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/mtd/physmap.h>

#include <mach/hardware.h>
#include <mach/platform.h>
#include <asm/hardware/arm_timer.h>
#include <asm/irq.h>
#include <asm/setup.h>
#include <asm/param.h>		/* HZ */
#include <asm/mach-types.h>

#include <mach/lm.h>

#include <asm/mach/arch.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>

#include <plat/fpga-irq.h>

#include "common.h"

/* 
 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
 * is the (PA >> 12).
 *
 * Setup a VA for the Integrator interrupt controller (for header #0,
 * just for now).
 */
#define VA_IC_BASE	__io_address(INTEGRATOR_IC_BASE)
#define VA_SC_BASE	__io_address(INTEGRATOR_SC_BASE)
#define VA_EBI_BASE	__io_address(INTEGRATOR_EBI_BASE)
#define VA_CMIC_BASE	__io_address(INTEGRATOR_HDR_IC)

/*
 * Logical      Physical
 * e8000000	40000000	PCI memory		PHYS_PCI_MEM_BASE	(max 512M)
 * ec000000	61000000	PCI config space	PHYS_PCI_CONFIG_BASE	(max 16M)
 * ed000000	62000000	PCI V3 regs		PHYS_PCI_V3_BASE	(max 64k)
 * ee000000	60000000	PCI IO			PHYS_PCI_IO_BASE	(max 16M)
 * ef000000			Cache flush
 * f1000000	10000000	Core module registers
 * f1100000	11000000	System controller registers
 * f1200000	12000000	EBI registers
 * f1300000	13000000	Counter/Timer
 * f1400000	14000000	Interrupt controller
 * f1600000	16000000	UART 0
 * f1700000	17000000	UART 1
 * f1a00000	1a000000	Debug LEDs
 * f1b00000	1b000000	GPIO
 */

static struct map_desc ap_io_desc[] __initdata = {
	{
		.virtual	= IO_ADDRESS(INTEGRATOR_HDR_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_HDR_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_SC_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_SC_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_EBI_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_EBI_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_CT_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_CT_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_IC_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_IC_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_UART0_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_UART0_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_UART1_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_UART1_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_DBG_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_DBG_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= PCI_MEMORY_VADDR,
		.pfn		= __phys_to_pfn(PHYS_PCI_MEM_BASE),
		.length		= SZ_16M,
		.type		= MT_DEVICE
	}, {
		.virtual	= PCI_CONFIG_VADDR,
		.pfn		= __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
		.length		= SZ_16M,
		.type		= MT_DEVICE
	}, {
		.virtual	= PCI_V3_VADDR,
		.pfn		= __phys_to_pfn(PHYS_PCI_V3_BASE),
		.length		= SZ_64K,
		.type		= MT_DEVICE
	}, {
		.virtual	= PCI_IO_VADDR,
		.pfn		= __phys_to_pfn(PHYS_PCI_IO_BASE),
		.length		= SZ_64K,
		.type		= MT_DEVICE
	}
};

static void __init ap_map_io(void)
{
	iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
}

#define INTEGRATOR_SC_VALID_INT	0x003fffff

static struct fpga_irq_data sc_irq_data = {
	.base		= VA_IC_BASE,
	.irq_start	= 0,
	.chip.name	= "SC",
};

static void __init ap_init_irq(void)
{
	/* Disable all interrupts initially. */
	/* Do the core module ones */
	writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);

	/* do the header card stuff next */
	writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
	writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);

	fpga_irq_init(-1, INTEGRATOR_SC_VALID_INT, &sc_irq_data);
}

#ifdef CONFIG_PM
static unsigned long ic_irq_enable;

static int irq_suspend(void)
{
	ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
	return 0;
}

static void irq_resume(void)
{
	/* disable all irq sources */
	writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
	writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
	writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);

	writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
}
#else
#define irq_suspend NULL
#define irq_resume NULL
#endif

static struct syscore_ops irq_syscore_ops = {
	.suspend	= irq_suspend,
	.resume		= irq_resume,
};

static int __init irq_syscore_init(void)
{
	register_syscore_ops(&irq_syscore_ops);

	return 0;
}

device_initcall(irq_syscore_init);

/*
 * Flash handling.
 */
#define SC_CTRLC (VA_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
#define SC_CTRLS (VA_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
#define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
#define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)

static int ap_flash_init(struct platform_device *dev)
{
	u32 tmp;

	writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);

	tmp = readl(EBI_CSR1) | INTEGRATOR_EBI_WRITE_ENABLE;
	writel(tmp, EBI_CSR1);

	if (!(readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) {
		writel(0xa05f, EBI_LOCK);
		writel(tmp, EBI_CSR1);
		writel(0, EBI_LOCK);
	}
	return 0;
}

static void ap_flash_exit(struct platform_device *dev)
{
	u32 tmp;

	writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);

	tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE;
	writel(tmp, EBI_CSR1);

	if (readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) {
		writel(0xa05f, EBI_LOCK);
		writel(tmp, EBI_CSR1);
		writel(0, EBI_LOCK);
	}
}

static void ap_flash_set_vpp(struct platform_device *pdev, int on)
{
	void __iomem *reg = on ? SC_CTRLS : SC_CTRLC;

	writel(INTEGRATOR_SC_CTRL_nFLVPPEN, reg);
}

static struct physmap_flash_data ap_flash_data = {
	.width		= 4,
	.init		= ap_flash_init,
	.exit		= ap_flash_exit,
	.set_vpp	= ap_flash_set_vpp,
};

static struct resource cfi_flash_resource = {
	.start		= INTEGRATOR_FLASH_BASE,
	.end		= INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
	.flags		= IORESOURCE_MEM,
};

static struct platform_device cfi_flash_device = {
	.name		= "physmap-flash",
	.id		= 0,
	.dev		= {
		.platform_data	= &ap_flash_data,
	},
	.num_resources	= 1,
	.resource	= &cfi_flash_resource,
};

static void __init ap_init(void)
{
	unsigned long sc_dec;
	int i;

	platform_device_register(&cfi_flash_device);

	sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
	for (i = 0; i < 4; i++) {
		struct lm_device *lmdev;

		if ((sc_dec & (16 << i)) == 0)
			continue;

		lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
		if (!lmdev)
			continue;

		lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
		lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
		lmdev->resource.flags = IORESOURCE_MEM;
		lmdev->irq = IRQ_AP_EXPINT0 + i;
		lmdev->id = i;

		lm_device_register(lmdev);
	}
}

/*
 * Where is the timer (VA)?
 */
#define TIMER0_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER0_BASE)
#define TIMER1_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER1_BASE)
#define TIMER2_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER2_BASE)

static unsigned long timer_reload;

static void integrator_clocksource_init(u32 khz)
{
	void __iomem *base = (void __iomem *)TIMER2_VA_BASE;
	u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC;

	if (khz >= 1500) {
		khz /= 16;
		ctrl |= TIMER_CTRL_DIV16;
	}

	writel(0xffff, base + TIMER_LOAD);
	writel(ctrl, base + TIMER_CTRL);

	clocksource_mmio_init(base + TIMER_VALUE, "timer2",
		khz * 1000, 200, 16, clocksource_mmio_readl_down);
}

static void __iomem * const clkevt_base = (void __iomem *)TIMER1_VA_BASE;

/*
 * IRQ handler for the timer
 */
static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	/* clear the interrupt */
	writel(1, clkevt_base + TIMER_INTCLR);

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
{
	u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;

	/* Disable timer */
	writel(ctrl, clkevt_base + TIMER_CTRL);

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		/* Enable the timer and start the periodic tick */
		writel(timer_reload, clkevt_base + TIMER_LOAD);
		ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
		writel(ctrl, clkevt_base + TIMER_CTRL);
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		/* Leave the timer disabled, .set_next_event will enable it */
		ctrl &= ~TIMER_CTRL_PERIODIC;
		writel(ctrl, clkevt_base + TIMER_CTRL);
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_RESUME:
	default:
		/* Just leave in disabled state */
		break;
	}

}

static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt)
{
	unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);

	writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
	writel(next, clkevt_base + TIMER_LOAD);
	writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);

	return 0;
}

static struct clock_event_device integrator_clockevent = {
	.name		= "timer1",
	.shift		= 34,
	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.set_mode	= clkevt_set_mode,
	.set_next_event	= clkevt_set_next_event,
	.rating		= 300,
	.cpumask	= cpu_all_mask,
};

static struct irqaction integrator_timer_irq = {
	.name		= "timer",
	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= integrator_timer_interrupt,
	.dev_id		= &integrator_clockevent,
};

static void integrator_clockevent_init(u32 khz)
{
	struct clock_event_device *evt = &integrator_clockevent;
	unsigned int ctrl = 0;

	if (khz * 1000 > 0x100000 * HZ) {
		khz /= 256;
		ctrl |= TIMER_CTRL_DIV256;
	} else if (khz * 1000 > 0x10000 * HZ) {
		khz /= 16;
		ctrl |= TIMER_CTRL_DIV16;
	}

	timer_reload = khz * 1000 / HZ;
	writel(ctrl, clkevt_base + TIMER_CTRL);

	evt->irq = IRQ_TIMERINT1;
	evt->mult = div_sc(khz, NSEC_PER_MSEC, evt->shift);
	evt->max_delta_ns = clockevent_delta2ns(0xffff, evt);
	evt->min_delta_ns = clockevent_delta2ns(0xf, evt);

	setup_irq(IRQ_TIMERINT1, &integrator_timer_irq);
	clockevents_register_device(evt);
}

/*
 * Set up timer(s).
 */
static void __init ap_init_timer(void)
{
	u32 khz = TICKS_PER_uSEC * 1000;

	writel(0, TIMER0_VA_BASE + TIMER_CTRL);
	writel(0, TIMER1_VA_BASE + TIMER_CTRL);
	writel(0, TIMER2_VA_BASE + TIMER_CTRL);

	integrator_clocksource_init(khz);
	integrator_clockevent_init(khz);
}

static struct sys_timer ap_timer = {
	.init		= ap_init_timer,
};

MACHINE_START(INTEGRATOR, "ARM-Integrator")
	/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
	.boot_params	= 0x00000100,
	.reserve	= integrator_reserve,
	.map_io		= ap_map_io,
	.init_early	= integrator_init_early,
	.init_irq	= ap_init_irq,
	.timer		= &ap_timer,
	.init_machine	= ap_init,
MACHINE_END
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-integrator/integrator_ap.c
	3	*
	4	* Copyright (C) 2000-2003 Deep Blue Solutions Ltd
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20	#include <linux/types.h>
	21	#include <linux/kernel.h>
	22	#include <linux/init.h>
	23	#include <linux/list.h>
d052d1be	24	#include <linux/platform_device.h>
1da177e4 LT	25	#include <linux/slab.h>
1da177e4 LT	26	#include <linux/string.h>
b7808056	27	#include <linux/syscore_ops.h>
a62c80e5 RK	28	#include <linux/amba/bus.h>
a62c80e5 RK	29	#include <linux/amba/kmi.h>
6be4826e RK	30	#include <linux/clocksource.h>
	31	#include <linux/clockchips.h>
	32	#include <linux/interrupt.h>
fced80c7	33	#include <linux/io.h>
f07e762e	34	#include <linux/mtd/physmap.h>
1da177e4	35
a09e64fb	36	#include <mach/hardware.h>
a285edcf	37	#include <mach/platform.h>
6be4826e	38	#include <asm/hardware/arm_timer.h>
1da177e4 LT	39	#include <asm/irq.h>
1da177e4 LT	40	#include <asm/setup.h>
4e57b681	41	#include <asm/param.h> /* HZ */
1da177e4	42	#include <asm/mach-types.h>
1da177e4	43
a09e64fb	44	#include <mach/lm.h>
1da177e4 LT	45
1da177e4 LT	46	#include <asm/mach/arch.h>
1da177e4 LT	47	#include <asm/mach/irq.h>
	48	#include <asm/mach/map.h>
	49	#include <asm/mach/time.h>
	50
c41b16f8 RK	51	#include <plat/fpga-irq.h>
c41b16f8 RK	52
98c672cf RK	53	#include "common.h"
98c672cf RK	54
1da177e4 LT	55	/*
	56	* All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
	57	* is the (PA >> 12).
	58	*
	59	* Setup a VA for the Integrator interrupt controller (for header #0,
	60	* just for now).
	61	*/
c41b16f8 RK	62	#define VA_IC_BASE __io_address(INTEGRATOR_IC_BASE)
	63	#define VA_SC_BASE __io_address(INTEGRATOR_SC_BASE)
	64	#define VA_EBI_BASE __io_address(INTEGRATOR_EBI_BASE)
	65	#define VA_CMIC_BASE __io_address(INTEGRATOR_HDR_IC)
1da177e4 LT	66
	67	/*
	68	* Logical Physical
	69	* e8000000 40000000 PCI memory PHYS_PCI_MEM_BASE (max 512M)
	70	* ec000000 61000000 PCI config space PHYS_PCI_CONFIG_BASE (max 16M)
	71	* ed000000 62000000 PCI V3 regs PHYS_PCI_V3_BASE (max 64k)
	72	* ee000000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M)
	73	* ef000000 Cache flush
	74	* f1000000 10000000 Core module registers
	75	* f1100000 11000000 System controller registers
	76	* f1200000 12000000 EBI registers
	77	* f1300000 13000000 Counter/Timer
	78	* f1400000 14000000 Interrupt controller
	79	* f1600000 16000000 UART 0
	80	* f1700000 17000000 UART 1
	81	* f1a00000 1a000000 Debug LEDs
	82	* f1b00000 1b000000 GPIO
	83	*/
	84
	85	static struct map_desc ap_io_desc[] __initdata = {
c8d27298 DS	86	{
	87	.virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
	88	.pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE),
	89	.length = SZ_4K,
	90	.type = MT_DEVICE
	91	}, {
	92	.virtual = IO_ADDRESS(INTEGRATOR_SC_BASE),
	93	.pfn = __phys_to_pfn(INTEGRATOR_SC_BASE),
	94	.length = SZ_4K,
	95	.type = MT_DEVICE
	96	}, {
	97	.virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE),
	98	.pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE),
	99	.length = SZ_4K,
	100	.type = MT_DEVICE
	101	}, {
	102	.virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
	103	.pfn = __phys_to_pfn(INTEGRATOR_CT_BASE),
	104	.length = SZ_4K,
	105	.type = MT_DEVICE
	106	}, {
	107	.virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
	108	.pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
	109	.length = SZ_4K,
	110	.type = MT_DEVICE
	111	}, {
	112	.virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
	113	.pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
	114	.length = SZ_4K,
	115	.type = MT_DEVICE
	116	}, {
	117	.virtual = IO_ADDRESS(INTEGRATOR_UART1_BASE),
	118	.pfn = __phys_to_pfn(INTEGRATOR_UART1_BASE),
	119	.length = SZ_4K,
	120	.type = MT_DEVICE
	121	}, {
	122	.virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
	123	.pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
	124	.length = SZ_4K,
	125	.type = MT_DEVICE
	126	}, {
da7ba956 RK	127	.virtual = IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE),
da7ba956 RK	128	.pfn = __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE),
c8d27298 DS	129	.length = SZ_4K,
	130	.type = MT_DEVICE
	131	}, {
	132	.virtual = PCI_MEMORY_VADDR,
	133	.pfn = __phys_to_pfn(PHYS_PCI_MEM_BASE),
	134	.length = SZ_16M,
	135	.type = MT_DEVICE
	136	}, {
	137	.virtual = PCI_CONFIG_VADDR,
	138	.pfn = __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
	139	.length = SZ_16M,
	140	.type = MT_DEVICE
	141	}, {
	142	.virtual = PCI_V3_VADDR,
	143	.pfn = __phys_to_pfn(PHYS_PCI_V3_BASE),
	144	.length = SZ_64K,
	145	.type = MT_DEVICE
	146	}, {
	147	.virtual = PCI_IO_VADDR,
	148	.pfn = __phys_to_pfn(PHYS_PCI_IO_BASE),
	149	.length = SZ_64K,
	150	.type = MT_DEVICE
	151	}
1da177e4 LT	152	};
	153
	154	static void __init ap_map_io(void)
	155	{
	156	iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
	157	}
	158
	159	#define INTEGRATOR_SC_VALID_INT 0x003fffff
	160
c41b16f8 RK	161	static struct fpga_irq_data sc_irq_data = {
	162	.base = VA_IC_BASE,
	163	.irq_start = 0,
	164	.chip.name = "SC",
1da177e4 LT	165	};
	166
	167	static void __init ap_init_irq(void)
	168	{
1da177e4 LT	169	/* Disable all interrupts initially. */
	170	/* Do the core module ones */
	171	writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
	172
	173	/* do the header card stuff next */
	174	writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
	175	writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
	176
c41b16f8	177	fpga_irq_init(-1, INTEGRATOR_SC_VALID_INT, &sc_irq_data);
1da177e4 LT	178	}
	179
	180	#ifdef CONFIG_PM
	181	static unsigned long ic_irq_enable;
	182
b7808056	183	static int irq_suspend(void)
1da177e4 LT	184	{
	185	ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
	186	return 0;
	187	}
	188
b7808056	189	static void irq_resume(void)
1da177e4 LT	190	{
	191	/* disable all irq sources */
	192	writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
	193	writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
	194	writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
	195
	196	writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
1da177e4 LT	197	}
	198	#else
	199	#define irq_suspend NULL
	200	#define irq_resume NULL
	201	#endif
	202
b7808056	203	static struct syscore_ops irq_syscore_ops = {
1da177e4 LT	204	.suspend = irq_suspend,
	205	.resume = irq_resume,
	206	};
	207
b7808056	208	static int __init irq_syscore_init(void)
1da177e4	209	{
b7808056 RW	210	register_syscore_ops(&irq_syscore_ops);
	211
	212	return 0;
1da177e4 LT	213	}
1da177e4 LT	214
b7808056	215	device_initcall(irq_syscore_init);
1da177e4 LT	216
	217	/*
	218	* Flash handling.
	219	*/
	220	#define SC_CTRLC (VA_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
	221	#define SC_CTRLS (VA_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
	222	#define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
	223	#define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
	224
f07e762e	225	static int ap_flash_init(struct platform_device *dev)
1da177e4 LT	226	{
	227	u32 tmp;
	228
	229	writel(INTEGRATOR_SC_CTRL_nFLVPPEN \| INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
	230
	231	tmp = readl(EBI_CSR1) \| INTEGRATOR_EBI_WRITE_ENABLE;
	232	writel(tmp, EBI_CSR1);
	233
	234	if (!(readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) {
	235	writel(0xa05f, EBI_LOCK);
	236	writel(tmp, EBI_CSR1);
	237	writel(0, EBI_LOCK);
	238	}
	239	return 0;
	240	}
	241
f07e762e	242	static void ap_flash_exit(struct platform_device *dev)
1da177e4 LT	243	{
	244	u32 tmp;
	245
	246	writel(INTEGRATOR_SC_CTRL_nFLVPPEN \| INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
	247
	248	tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE;
	249	writel(tmp, EBI_CSR1);
	250
	251	if (readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) {
	252	writel(0xa05f, EBI_LOCK);
	253	writel(tmp, EBI_CSR1);
	254	writel(0, EBI_LOCK);
	255	}
	256	}
	257
667f390b	258	static void ap_flash_set_vpp(struct platform_device *pdev, int on)
1da177e4	259	{
c41b16f8	260	void __iomem *reg = on ? SC_CTRLS : SC_CTRLC;
1da177e4 LT	261
	262	writel(INTEGRATOR_SC_CTRL_nFLVPPEN, reg);
	263	}
	264
f07e762e	265	static struct physmap_flash_data ap_flash_data = {
1da177e4 LT	266	.width = 4,
	267	.init = ap_flash_init,
	268	.exit = ap_flash_exit,
	269	.set_vpp = ap_flash_set_vpp,
	270	};
	271
	272	static struct resource cfi_flash_resource = {
	273	.start = INTEGRATOR_FLASH_BASE,
	274	.end = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
	275	.flags = IORESOURCE_MEM,
	276	};
	277
	278	static struct platform_device cfi_flash_device = {
f07e762e	279	.name = "physmap-flash",
1da177e4 LT	280	.id = 0,
	281	.dev = {
	282	.platform_data = &ap_flash_data,
	283	},
	284	.num_resources = 1,
	285	.resource = &cfi_flash_resource,
	286	};
	287
	288	static void __init ap_init(void)
	289	{
	290	unsigned long sc_dec;
	291	int i;
	292
	293	platform_device_register(&cfi_flash_device);
	294
	295	sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
	296	for (i = 0; i < 4; i++) {
	297	struct lm_device *lmdev;
	298
	299	if ((sc_dec & (16 << i)) == 0)
	300	continue;
	301
d2a02b93	302	lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
1da177e4 LT	303	if (!lmdev)
	304	continue;
	305
1da177e4 LT	306	lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
	307	lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
	308	lmdev->resource.flags = IORESOURCE_MEM;
	309	lmdev->irq = IRQ_AP_EXPINT0 + i;
	310	lmdev->id = i;
	311
	312	lm_device_register(lmdev);
	313	}
	314	}
	315
6be4826e RK	316	/*
	317	* Where is the timer (VA)?
	318	*/
	319	#define TIMER0_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER0_BASE)
	320	#define TIMER1_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER1_BASE)
	321	#define TIMER2_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER2_BASE)
	322
6be4826e RK	323	static unsigned long timer_reload;
6be4826e RK	324
6be4826e RK	325	static void integrator_clocksource_init(u32 khz)
6be4826e RK	326	{
c5039f52	327	void __iomem base = (void __iomem )TIMER2_VA_BASE;
bb9ea778	328	u32 ctrl = TIMER_CTRL_ENABLE \| TIMER_CTRL_PERIODIC;
6be4826e RK	329
	330	if (khz >= 1500) {
	331	khz /= 16;
bb9ea778	332	ctrl \|= TIMER_CTRL_DIV16;
6be4826e RK	333	}
6be4826e RK	334
6be4826e	335	writel(0xffff, base + TIMER_LOAD);
bb9ea778	336	writel(ctrl, base + TIMER_CTRL);
6be4826e	337
c5039f52 RK	338	clocksource_mmio_init(base + TIMER_VALUE, "timer2",
c5039f52 RK	339	khz * 1000, 200, 16, clocksource_mmio_readl_down);
6be4826e RK	340	}
	341
	342	static void __iomem * const clkevt_base = (void __iomem *)TIMER1_VA_BASE;
	343
	344	/*
	345	* IRQ handler for the timer
	346	*/
	347	static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id)
	348	{
	349	struct clock_event_device *evt = dev_id;
	350
	351	/* clear the interrupt */
	352	writel(1, clkevt_base + TIMER_INTCLR);
	353
	354	evt->event_handler(evt);
	355
	356	return IRQ_HANDLED;
	357	}
	358
	359	static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
	360	{
	361	u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
	362
02f56321 LW	363	/* Disable timer */
02f56321 LW	364	writel(ctrl, clkevt_base + TIMER_CTRL);
6be4826e	365
02f56321 LW	366	switch (mode) {
	367	case CLOCK_EVT_MODE_PERIODIC:
	368	/* Enable the timer and start the periodic tick */
6be4826e RK	369	writel(timer_reload, clkevt_base + TIMER_LOAD);
6be4826e RK	370	ctrl \|= TIMER_CTRL_PERIODIC \| TIMER_CTRL_ENABLE;
02f56321 LW	371	writel(ctrl, clkevt_base + TIMER_CTRL);
	372	break;
	373	case CLOCK_EVT_MODE_ONESHOT:
	374	/* Leave the timer disabled, .set_next_event will enable it */
	375	ctrl &= ~TIMER_CTRL_PERIODIC;
	376	writel(ctrl, clkevt_base + TIMER_CTRL);
	377	break;
	378	case CLOCK_EVT_MODE_UNUSED:
	379	case CLOCK_EVT_MODE_SHUTDOWN:
	380	case CLOCK_EVT_MODE_RESUME:
	381	default:
	382	/* Just leave in disabled state */
	383	break;
6be4826e RK	384	}
6be4826e RK	385
6be4826e RK	386	}
	387
	388	static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt)
	389	{
	390	unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
	391
	392	writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
	393	writel(next, clkevt_base + TIMER_LOAD);
	394	writel(ctrl \| TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
	395
	396	return 0;
	397	}
	398
	399	static struct clock_event_device integrator_clockevent = {
	400	.name = "timer1",
	401	.shift = 34,
02f56321	402	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
6be4826e RK	403	.set_mode = clkevt_set_mode,
	404	.set_next_event = clkevt_set_next_event,
	405	.rating = 300,
	406	.cpumask = cpu_all_mask,
	407	};
	408
	409	static struct irqaction integrator_timer_irq = {
	410	.name = "timer",
	411	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL,
	412	.handler = integrator_timer_interrupt,
	413	.dev_id = &integrator_clockevent,
	414	};
	415
	416	static void integrator_clockevent_init(u32 khz)
	417	{
	418	struct clock_event_device *evt = &integrator_clockevent;
	419	unsigned int ctrl = 0;
	420
	421	if (khz * 1000 > 0x100000 * HZ) {
	422	khz /= 256;
	423	ctrl \|= TIMER_CTRL_DIV256;
	424	} else if (khz * 1000 > 0x10000 * HZ) {
	425	khz /= 16;
	426	ctrl \|= TIMER_CTRL_DIV16;
	427	}
	428
	429	timer_reload = khz * 1000 / HZ;
	430	writel(ctrl, clkevt_base + TIMER_CTRL);
	431
	432	evt->irq = IRQ_TIMERINT1;
	433	evt->mult = div_sc(khz, NSEC_PER_MSEC, evt->shift);
	434	evt->max_delta_ns = clockevent_delta2ns(0xffff, evt);
	435	evt->min_delta_ns = clockevent_delta2ns(0xf, evt);
	436
	437	setup_irq(IRQ_TIMERINT1, &integrator_timer_irq);
	438	clockevents_register_device(evt);
	439	}
	440
	441	/*
	442	* Set up timer(s).
	443	*/
1da177e4 LT	444	static void __init ap_init_timer(void)
1da177e4 LT	445	{
6be4826e RK	446	u32 khz = TICKS_PER_uSEC * 1000;
	447
	448	writel(0, TIMER0_VA_BASE + TIMER_CTRL);
	449	writel(0, TIMER1_VA_BASE + TIMER_CTRL);
	450	writel(0, TIMER2_VA_BASE + TIMER_CTRL);
	451
	452	integrator_clocksource_init(khz);
	453	integrator_clockevent_init(khz);
1da177e4 LT	454	}
	455
	456	static struct sys_timer ap_timer = {
	457	.init = ap_init_timer,
1da177e4 LT	458	};
	459
	460	MACHINE_START(INTEGRATOR, "ARM-Integrator")
e9dea0c6	461	/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
e9dea0c6	462	.boot_params = 0x00000100,
98c672cf	463	.reserve = integrator_reserve,
c735c987 RK	464	.map_io = ap_map_io,
c735c987 RK	465	.init_early = integrator_init_early,
e9dea0c6	466	.init_irq = ap_init_irq,
1da177e4	467	.timer = &ap_timer,
e9dea0c6	468	.init_machine = ap_init,
1da177e4	469	MACHINE_END