[deliverable/linux.git] / arch / arm / mach-integrator / integrator_ap.c

/*
 *  linux/arch/arm/mach-integrator/integrator_ap.c
 *
 *  Copyright (C) 2000-2003 Deep Blue Solutions Ltd
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/syscore_ops.h>
#include <linux/amba/bus.h>
#include <linux/amba/kmi.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/mtd/physmap.h>
#include <linux/clk.h>
#include <linux/platform_data/clk-integrator.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/stat.h>
#include <linux/sys_soc.h>
#include <video/vga.h>

#include <mach/hardware.h>
#include <mach/platform.h>
#include <asm/hardware/arm_timer.h>
#include <asm/setup.h>
#include <asm/param.h>		/* HZ */
#include <asm/mach-types.h>
#include <asm/sched_clock.h>

#include <mach/lm.h>
#include <mach/irqs.h>

#include <asm/mach/arch.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>
#include <asm/mach/pci.h>
#include <asm/mach/time.h>

#include <plat/fpga-irq.h>

#include "common.h"

/* Base address to the AP system controller */
static void __iomem *ap_syscon_base;

/*
 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
 * is the (PA >> 12).
 *
 * Setup a VA for the Integrator interrupt controller (for header #0,
 * just for now).
 */
#define VA_IC_BASE	__io_address(INTEGRATOR_IC_BASE)
#define VA_EBI_BASE	__io_address(INTEGRATOR_EBI_BASE)
#define VA_CMIC_BASE	__io_address(INTEGRATOR_HDR_IC)

/*
 * Logical      Physical
 * e8000000	40000000	PCI memory		PHYS_PCI_MEM_BASE	(max 512M)
 * ec000000	61000000	PCI config space	PHYS_PCI_CONFIG_BASE	(max 16M)
 * ed000000	62000000	PCI V3 regs		PHYS_PCI_V3_BASE	(max 64k)
 * fee00000	60000000	PCI IO			PHYS_PCI_IO_BASE	(max 16M)
 * ef000000			Cache flush
 * f1000000	10000000	Core module registers
 * f1100000	11000000	System controller registers
 * f1200000	12000000	EBI registers
 * f1300000	13000000	Counter/Timer
 * f1400000	14000000	Interrupt controller
 * f1600000	16000000	UART 0
 * f1700000	17000000	UART 1
 * f1a00000	1a000000	Debug LEDs
 * f1b00000	1b000000	GPIO
 */

static struct map_desc ap_io_desc[] __initdata = {
	{
		.virtual	= IO_ADDRESS(INTEGRATOR_HDR_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_HDR_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_EBI_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_EBI_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_CT_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_CT_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_IC_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_IC_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_UART0_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_UART0_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_DBG_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_DBG_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= (unsigned long)PCI_MEMORY_VADDR,
		.pfn		= __phys_to_pfn(PHYS_PCI_MEM_BASE),
		.length		= SZ_16M,
		.type		= MT_DEVICE
	}, {
		.virtual	= (unsigned long)PCI_CONFIG_VADDR,
		.pfn		= __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
		.length		= SZ_16M,
		.type		= MT_DEVICE
	}, {
		.virtual	= (unsigned long)PCI_V3_VADDR,
		.pfn		= __phys_to_pfn(PHYS_PCI_V3_BASE),
		.length		= SZ_64K,
		.type		= MT_DEVICE
	}
};

static void __init ap_map_io(void)
{
	iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
	vga_base = (unsigned long)PCI_MEMORY_VADDR;
	pci_map_io_early(__phys_to_pfn(PHYS_PCI_IO_BASE));
}

#ifdef CONFIG_PM
static unsigned long ic_irq_enable;

static int irq_suspend(void)
{
	ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
	return 0;
}

static void irq_resume(void)
{
	/* disable all irq sources */
	writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
	writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
	writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);

	writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
}
#else
#define irq_suspend NULL
#define irq_resume NULL
#endif

static struct syscore_ops irq_syscore_ops = {
	.suspend	= irq_suspend,
	.resume		= irq_resume,
};

static int __init irq_syscore_init(void)
{
	register_syscore_ops(&irq_syscore_ops);

	return 0;
}

device_initcall(irq_syscore_init);

/*
 * Flash handling.
 */
#define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
#define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)

static int ap_flash_init(struct platform_device *dev)
{
	u32 tmp;

	writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP,
	       ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);

	tmp = readl(EBI_CSR1) | INTEGRATOR_EBI_WRITE_ENABLE;
	writel(tmp, EBI_CSR1);

	if (!(readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) {
		writel(0xa05f, EBI_LOCK);
		writel(tmp, EBI_CSR1);
		writel(0, EBI_LOCK);
	}
	return 0;
}

static void ap_flash_exit(struct platform_device *dev)
{
	u32 tmp;

	writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP,
	       ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);

	tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE;
	writel(tmp, EBI_CSR1);

	if (readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) {
		writel(0xa05f, EBI_LOCK);
		writel(tmp, EBI_CSR1);
		writel(0, EBI_LOCK);
	}
}

static void ap_flash_set_vpp(struct platform_device *pdev, int on)
{
	if (on)
		writel(INTEGRATOR_SC_CTRL_nFLVPPEN,
		       ap_syscon_base + INTEGRATOR_SC_CTRLS_OFFSET);
	else
		writel(INTEGRATOR_SC_CTRL_nFLVPPEN,
		       ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
}

static struct physmap_flash_data ap_flash_data = {
	.width		= 4,
	.init		= ap_flash_init,
	.exit		= ap_flash_exit,
	.set_vpp	= ap_flash_set_vpp,
};

/*
 * Where is the timer (VA)?
 */
#define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
#define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
#define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)

static unsigned long timer_reload;

static u32 notrace integrator_read_sched_clock(void)
{
	return -readl((void __iomem *) TIMER2_VA_BASE + TIMER_VALUE);
}

static void integrator_clocksource_init(unsigned long inrate,
					void __iomem *base)
{
	u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC;
	unsigned long rate = inrate;

	if (rate >= 1500000) {
		rate /= 16;
		ctrl |= TIMER_CTRL_DIV16;
	}

	writel(0xffff, base + TIMER_LOAD);
	writel(ctrl, base + TIMER_CTRL);

	clocksource_mmio_init(base + TIMER_VALUE, "timer2",
			rate, 200, 16, clocksource_mmio_readl_down);
	setup_sched_clock(integrator_read_sched_clock, 16, rate);
}

static void __iomem * clkevt_base;

/*
 * IRQ handler for the timer
 */
static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	/* clear the interrupt */
	writel(1, clkevt_base + TIMER_INTCLR);

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
{
	u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;

	/* Disable timer */
	writel(ctrl, clkevt_base + TIMER_CTRL);

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		/* Enable the timer and start the periodic tick */
		writel(timer_reload, clkevt_base + TIMER_LOAD);
		ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
		writel(ctrl, clkevt_base + TIMER_CTRL);
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		/* Leave the timer disabled, .set_next_event will enable it */
		ctrl &= ~TIMER_CTRL_PERIODIC;
		writel(ctrl, clkevt_base + TIMER_CTRL);
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_RESUME:
	default:
		/* Just leave in disabled state */
		break;
	}

}

static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt)
{
	unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);

	writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
	writel(next, clkevt_base + TIMER_LOAD);
	writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);

	return 0;
}

static struct clock_event_device integrator_clockevent = {
	.name		= "timer1",
	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.set_mode	= clkevt_set_mode,
	.set_next_event	= clkevt_set_next_event,
	.rating		= 300,
};

static struct irqaction integrator_timer_irq = {
	.name		= "timer",
	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= integrator_timer_interrupt,
	.dev_id		= &integrator_clockevent,
};

static void integrator_clockevent_init(unsigned long inrate,
				void __iomem *base, int irq)
{
	unsigned long rate = inrate;
	unsigned int ctrl = 0;

	clkevt_base = base;
	/* Calculate and program a divisor */
	if (rate > 0x100000 * HZ) {
		rate /= 256;
		ctrl |= TIMER_CTRL_DIV256;
	} else if (rate > 0x10000 * HZ) {
		rate /= 16;
		ctrl |= TIMER_CTRL_DIV16;
	}
	timer_reload = rate / HZ;
	writel(ctrl, clkevt_base + TIMER_CTRL);

	setup_irq(irq, &integrator_timer_irq);
	clockevents_config_and_register(&integrator_clockevent,
					rate,
					1,
					0xffffU);
}

void __init ap_init_early(void)
{
}

#ifdef CONFIG_OF

static void __init ap_init_timer_of(void)
{
	struct device_node *node;
	const char *path;
	void __iomem *base;
	int err;
	int irq;
	struct clk *clk;
	unsigned long rate;

	clk = clk_get_sys("ap_timer", NULL);
	BUG_ON(IS_ERR(clk));
	clk_prepare_enable(clk);
	rate = clk_get_rate(clk);

	err = of_property_read_string(of_aliases,
				"arm,timer-primary", &path);
	if (WARN_ON(err))
		return;
	node = of_find_node_by_path(path);
	base = of_iomap(node, 0);
	if (WARN_ON(!base))
		return;
	writel(0, base + TIMER_CTRL);
	integrator_clocksource_init(rate, base);

	err = of_property_read_string(of_aliases,
				"arm,timer-secondary", &path);
	if (WARN_ON(err))
		return;
	node = of_find_node_by_path(path);
	base = of_iomap(node, 0);
	if (WARN_ON(!base))
		return;
	irq = irq_of_parse_and_map(node, 0);
	writel(0, base + TIMER_CTRL);
	integrator_clockevent_init(rate, base, irq);
}

static struct sys_timer ap_of_timer = {
	.init		= ap_init_timer_of,
};

static const struct of_device_id fpga_irq_of_match[] __initconst = {
	{ .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
	{ /* Sentinel */ }
};

static void __init ap_init_irq_of(void)
{
	/* disable core module IRQs */
	writel(0xffffffffU, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
	of_irq_init(fpga_irq_of_match);
	integrator_clk_init(false);
}

/* For the Device Tree, add in the UART callbacks as AUXDATA */
static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = {
	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
		"rtc", NULL),
	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
		"uart0", &integrator_uart_data),
	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
		"uart1", &integrator_uart_data),
	OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
		"kmi0", NULL),
	OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
		"kmi1", NULL),
	OF_DEV_AUXDATA("cfi-flash", INTEGRATOR_FLASH_BASE,
		"physmap-flash", &ap_flash_data),
	{ /* sentinel */ },
};

static void __init ap_init_of(void)
{
	unsigned long sc_dec;
	struct device_node *root;
	struct device_node *syscon;
	struct device *parent;
	struct soc_device *soc_dev;
	struct soc_device_attribute *soc_dev_attr;
	u32 ap_sc_id;
	int err;
	int i;

	/* Here we create an SoC device for the root node */
	root = of_find_node_by_path("/");
	if (!root)
		return;
	syscon = of_find_node_by_path("/syscon");
	if (!syscon)
		return;

	ap_syscon_base = of_iomap(syscon, 0);
	if (!ap_syscon_base)
		return;

	ap_sc_id = readl(ap_syscon_base);

	soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
	if (!soc_dev_attr)
		return;

	err = of_property_read_string(root, "compatible",
				      &soc_dev_attr->soc_id);
	if (err)
		return;
	err = of_property_read_string(root, "model", &soc_dev_attr->machine);
	if (err)
		return;
	soc_dev_attr->family = "Integrator";
	soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c",
					   'A' + (ap_sc_id & 0x0f));

	soc_dev = soc_device_register(soc_dev_attr);
	if (IS_ERR_OR_NULL(soc_dev)) {
		kfree(soc_dev_attr->revision);
		kfree(soc_dev_attr);
		return;
	}

	parent = soc_device_to_device(soc_dev);

	if (!IS_ERR_OR_NULL(parent))
		integrator_init_sysfs(parent, ap_sc_id);

	of_platform_populate(root, of_default_bus_match_table,
			ap_auxdata_lookup, parent);

	sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET);
	for (i = 0; i < 4; i++) {
		struct lm_device *lmdev;

		if ((sc_dec & (16 << i)) == 0)
			continue;

		lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
		if (!lmdev)
			continue;

		lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
		lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
		lmdev->resource.flags = IORESOURCE_MEM;
		lmdev->irq = IRQ_AP_EXPINT0 + i;
		lmdev->id = i;

		lm_device_register(lmdev);
	}
}

static const char * ap_dt_board_compat[] = {
	"arm,integrator-ap",
	NULL,
};

DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
	.reserve	= integrator_reserve,
	.map_io		= ap_map_io,
	.nr_irqs	= NR_IRQS_INTEGRATOR_AP,
	.init_early	= ap_init_early,
	.init_irq	= ap_init_irq_of,
	.handle_irq	= fpga_handle_irq,
	.timer		= &ap_of_timer,
	.init_machine	= ap_init_of,
	.restart	= integrator_restart,
	.dt_compat      = ap_dt_board_compat,
MACHINE_END

#endif

#ifdef CONFIG_ATAGS

/*
 * For the ATAG boot some static mappings are needed. This will
 * go away with the ATAG support down the road.
 */

static struct map_desc ap_io_desc_atag[] __initdata = {
	{
		.virtual	= IO_ADDRESS(INTEGRATOR_SC_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_SC_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	},
};

static void __init ap_map_io_atag(void)
{
	iotable_init(ap_io_desc_atag, ARRAY_SIZE(ap_io_desc_atag));
	ap_syscon_base = __io_address(INTEGRATOR_SC_BASE);
	ap_map_io();
}

/*
 * This is where non-devicetree initialization code is collected and stashed
 * for eventual deletion.
 */

static struct resource cfi_flash_resource = {
	.start		= INTEGRATOR_FLASH_BASE,
	.end		= INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
	.flags		= IORESOURCE_MEM,
};

static struct platform_device cfi_flash_device = {
	.name		= "physmap-flash",
	.id		= 0,
	.dev		= {
		.platform_data	= &ap_flash_data,
	},
	.num_resources	= 1,
	.resource	= &cfi_flash_resource,
};

static void __init ap_init_timer(void)
{
	struct clk *clk;
	unsigned long rate;

	clk = clk_get_sys("ap_timer", NULL);
	BUG_ON(IS_ERR(clk));
	clk_prepare_enable(clk);
	rate = clk_get_rate(clk);

	writel(0, TIMER0_VA_BASE + TIMER_CTRL);
	writel(0, TIMER1_VA_BASE + TIMER_CTRL);
	writel(0, TIMER2_VA_BASE + TIMER_CTRL);

	integrator_clocksource_init(rate, (void __iomem *)TIMER2_VA_BASE);
	integrator_clockevent_init(rate, (void __iomem *)TIMER1_VA_BASE,
				IRQ_TIMERINT1);
}

static struct sys_timer ap_timer = {
	.init		= ap_init_timer,
};

#define INTEGRATOR_SC_VALID_INT	0x003fffff

static void __init ap_init_irq(void)
{
	/* Disable all interrupts initially. */
	/* Do the core module ones */
	writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);

	/* do the header card stuff next */
	writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
	writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);

	fpga_irq_init(VA_IC_BASE, "SC", IRQ_PIC_START,
		-1, INTEGRATOR_SC_VALID_INT, NULL);
	integrator_clk_init(false);
}

static void __init ap_init(void)
{
	unsigned long sc_dec;
	int i;

	platform_device_register(&cfi_flash_device);

	sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET);
	for (i = 0; i < 4; i++) {
		struct lm_device *lmdev;

		if ((sc_dec & (16 << i)) == 0)
			continue;

		lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
		if (!lmdev)
			continue;

		lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
		lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
		lmdev->resource.flags = IORESOURCE_MEM;
		lmdev->irq = IRQ_AP_EXPINT0 + i;
		lmdev->id = i;

		lm_device_register(lmdev);
	}

	integrator_init(false);
}

MACHINE_START(INTEGRATOR, "ARM-Integrator")
	/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
	.atag_offset	= 0x100,
	.reserve	= integrator_reserve,
	.map_io		= ap_map_io_atag,
	.nr_irqs	= NR_IRQS_INTEGRATOR_AP,
	.init_early	= ap_init_early,
	.init_irq	= ap_init_irq,
	.handle_irq	= fpga_handle_irq,
	.timer		= &ap_timer,
	.init_machine	= ap_init,
	.restart	= integrator_restart,
MACHINE_END

#endif
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-integrator/integrator_ap.c
	3	*
	4	* Copyright (C) 2000-2003 Deep Blue Solutions Ltd
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20	#include <linux/types.h>
	21	#include <linux/kernel.h>
	22	#include <linux/init.h>
	23	#include <linux/list.h>
d052d1be	24	#include <linux/platform_device.h>
1da177e4 LT	25	#include <linux/slab.h>
1da177e4 LT	26	#include <linux/string.h>
b7808056	27	#include <linux/syscore_ops.h>
a62c80e5 RK	28	#include <linux/amba/bus.h>
a62c80e5 RK	29	#include <linux/amba/kmi.h>
6be4826e RK	30	#include <linux/clocksource.h>
	31	#include <linux/clockchips.h>
	32	#include <linux/interrupt.h>
fced80c7	33	#include <linux/io.h>
f07e762e	34	#include <linux/mtd/physmap.h>
bb76079a	35	#include <linux/clk.h>
a613163d	36	#include <linux/platform_data/clk-integrator.h>
4980f9bc LW	37	#include <linux/of_irq.h>
4980f9bc LW	38	#include <linux/of_address.h>
4672cddf	39	#include <linux/of_platform.h>
e67ae6be LW	40	#include <linux/stat.h>
e67ae6be LW	41	#include <linux/sys_soc.h>
b71d8429	42	#include <video/vga.h>
1da177e4	43
a09e64fb	44	#include <mach/hardware.h>
a285edcf	45	#include <mach/platform.h>
6be4826e	46	#include <asm/hardware/arm_timer.h>
1da177e4	47	#include <asm/setup.h>
4e57b681	48	#include <asm/param.h> /* HZ */
1da177e4	49	#include <asm/mach-types.h>
a9d6d151	50	#include <asm/sched_clock.h>
1da177e4	51
a09e64fb	52	#include <mach/lm.h>
695436e3	53	#include <mach/irqs.h>
1da177e4 LT	54
1da177e4 LT	55	#include <asm/mach/arch.h>
1da177e4 LT	56	#include <asm/mach/irq.h>
1da177e4 LT	57	#include <asm/mach/map.h>
68ef6322	58	#include <asm/mach/pci.h>
1da177e4 LT	59	#include <asm/mach/time.h>
1da177e4 LT	60
c41b16f8 RK	61	#include <plat/fpga-irq.h>
c41b16f8 RK	62
98c672cf RK	63	#include "common.h"
98c672cf RK	64
83feba51 LW	65	/* Base address to the AP system controller */
	66	static void __iomem *ap_syscon_base;
	67
	68	/*
1da177e4 LT	69	* All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
	70	* is the (PA >> 12).
	71	*
	72	* Setup a VA for the Integrator interrupt controller (for header #0,
	73	* just for now).
	74	*/
c41b16f8	75	#define VA_IC_BASE __io_address(INTEGRATOR_IC_BASE)
c41b16f8 RK	76	#define VA_EBI_BASE __io_address(INTEGRATOR_EBI_BASE)
c41b16f8 RK	77	#define VA_CMIC_BASE __io_address(INTEGRATOR_HDR_IC)
1da177e4 LT	78
	79	/*
	80	* Logical Physical
	81	* e8000000 40000000 PCI memory PHYS_PCI_MEM_BASE (max 512M)
	82	* ec000000 61000000 PCI config space PHYS_PCI_CONFIG_BASE (max 16M)
	83	* ed000000 62000000 PCI V3 regs PHYS_PCI_V3_BASE (max 64k)
68ef6322	84	* fee00000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M)
1da177e4 LT	85	* ef000000 Cache flush
	86	* f1000000 10000000 Core module registers
	87	* f1100000 11000000 System controller registers
	88	* f1200000 12000000 EBI registers
	89	* f1300000 13000000 Counter/Timer
	90	* f1400000 14000000 Interrupt controller
	91	* f1600000 16000000 UART 0
	92	* f1700000 17000000 UART 1
	93	* f1a00000 1a000000 Debug LEDs
	94	* f1b00000 1b000000 GPIO
	95	*/
	96
	97	static struct map_desc ap_io_desc[] __initdata = {
c8d27298 DS	98	{
	99	.virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
	100	.pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE),
	101	.length = SZ_4K,
	102	.type = MT_DEVICE
c8d27298 DS	103	}, {
	104	.virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE),
	105	.pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE),
	106	.length = SZ_4K,
	107	.type = MT_DEVICE
	108	}, {
	109	.virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
	110	.pfn = __phys_to_pfn(INTEGRATOR_CT_BASE),
	111	.length = SZ_4K,
	112	.type = MT_DEVICE
	113	}, {
	114	.virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
	115	.pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
	116	.length = SZ_4K,
	117	.type = MT_DEVICE
	118	}, {
	119	.virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
	120	.pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
	121	.length = SZ_4K,
	122	.type = MT_DEVICE
c8d27298 DS	123	}, {
	124	.virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
	125	.pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
	126	.length = SZ_4K,
	127	.type = MT_DEVICE
	128	}, {
da7ba956 RK	129	.virtual = IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE),
da7ba956 RK	130	.pfn = __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE),
c8d27298 DS	131	.length = SZ_4K,
	132	.type = MT_DEVICE
	133	}, {
b7a3f8db	134	.virtual = (unsigned long)PCI_MEMORY_VADDR,
c8d27298 DS	135	.pfn = __phys_to_pfn(PHYS_PCI_MEM_BASE),
	136	.length = SZ_16M,
	137	.type = MT_DEVICE
	138	}, {
b7a3f8db	139	.virtual = (unsigned long)PCI_CONFIG_VADDR,
c8d27298 DS	140	.pfn = __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
	141	.length = SZ_16M,
	142	.type = MT_DEVICE
	143	}, {
b7a3f8db	144	.virtual = (unsigned long)PCI_V3_VADDR,
c8d27298 DS	145	.pfn = __phys_to_pfn(PHYS_PCI_V3_BASE),
	146	.length = SZ_64K,
	147	.type = MT_DEVICE
c8d27298	148	}
1da177e4 LT	149	};
	150
	151	static void __init ap_map_io(void)
	152	{
	153	iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
21c8715f	154	vga_base = (unsigned long)PCI_MEMORY_VADDR;
68ef6322	155	pci_map_io_early(__phys_to_pfn(PHYS_PCI_IO_BASE));
1da177e4 LT	156	}
1da177e4 LT	157
1da177e4 LT	158	#ifdef CONFIG_PM
	159	static unsigned long ic_irq_enable;
	160
b7808056	161	static int irq_suspend(void)
1da177e4 LT	162	{
	163	ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
	164	return 0;
	165	}
	166
b7808056	167	static void irq_resume(void)
1da177e4 LT	168	{
	169	/* disable all irq sources */
	170	writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
	171	writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
	172	writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
	173
	174	writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
1da177e4 LT	175	}
	176	#else
	177	#define irq_suspend NULL
	178	#define irq_resume NULL
	179	#endif
	180
b7808056	181	static struct syscore_ops irq_syscore_ops = {
1da177e4 LT	182	.suspend = irq_suspend,
	183	.resume = irq_resume,
	184	};
	185
b7808056	186	static int __init irq_syscore_init(void)
1da177e4	187	{
b7808056 RW	188	register_syscore_ops(&irq_syscore_ops);
	189
	190	return 0;
1da177e4 LT	191	}
1da177e4 LT	192
b7808056	193	device_initcall(irq_syscore_init);
1da177e4 LT	194
	195	/*
	196	* Flash handling.
	197	*/
1da177e4 LT	198	#define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
	199	#define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
	200
f07e762e	201	static int ap_flash_init(struct platform_device *dev)
1da177e4 LT	202	{
	203	u32 tmp;
	204
83feba51 LW	205	writel(INTEGRATOR_SC_CTRL_nFLVPPEN \| INTEGRATOR_SC_CTRL_nFLWP,
83feba51 LW	206	ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
1da177e4 LT	207
	208	tmp = readl(EBI_CSR1) \| INTEGRATOR_EBI_WRITE_ENABLE;
	209	writel(tmp, EBI_CSR1);
	210
	211	if (!(readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) {
	212	writel(0xa05f, EBI_LOCK);
	213	writel(tmp, EBI_CSR1);
	214	writel(0, EBI_LOCK);
	215	}
	216	return 0;
	217	}
	218
f07e762e	219	static void ap_flash_exit(struct platform_device *dev)
1da177e4 LT	220	{
	221	u32 tmp;
	222
83feba51 LW	223	writel(INTEGRATOR_SC_CTRL_nFLVPPEN \| INTEGRATOR_SC_CTRL_nFLWP,
83feba51 LW	224	ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
1da177e4 LT	225
	226	tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE;
	227	writel(tmp, EBI_CSR1);
	228
	229	if (readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) {
	230	writel(0xa05f, EBI_LOCK);
	231	writel(tmp, EBI_CSR1);
	232	writel(0, EBI_LOCK);
	233	}
	234	}
	235
667f390b	236	static void ap_flash_set_vpp(struct platform_device *pdev, int on)
1da177e4	237	{
83feba51 LW	238	if (on)
	239	writel(INTEGRATOR_SC_CTRL_nFLVPPEN,
	240	ap_syscon_base + INTEGRATOR_SC_CTRLS_OFFSET);
	241	else
	242	writel(INTEGRATOR_SC_CTRL_nFLVPPEN,
	243	ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
1da177e4 LT	244	}
1da177e4 LT	245
f07e762e	246	static struct physmap_flash_data ap_flash_data = {
1da177e4 LT	247	.width = 4,
	248	.init = ap_flash_init,
	249	.exit = ap_flash_exit,
	250	.set_vpp = ap_flash_set_vpp,
	251	};
	252
6be4826e RK	253	/*
	254	* Where is the timer (VA)?
	255	*/
b7a3f8db AB	256	#define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
	257	#define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
	258	#define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)
6be4826e	259
6be4826e RK	260	static unsigned long timer_reload;
6be4826e RK	261
a9d6d151 LW	262	static u32 notrace integrator_read_sched_clock(void)
	263	{
	264	return -readl((void __iomem *) TIMER2_VA_BASE + TIMER_VALUE);
	265	}
	266
4980f9bc LW	267	static void integrator_clocksource_init(unsigned long inrate,
4980f9bc LW	268	void __iomem *base)
6be4826e	269	{
bb9ea778	270	u32 ctrl = TIMER_CTRL_ENABLE \| TIMER_CTRL_PERIODIC;
bb76079a	271	unsigned long rate = inrate;
6be4826e	272
bb76079a LW	273	if (rate >= 1500000) {
bb76079a LW	274	rate /= 16;
bb9ea778	275	ctrl \|= TIMER_CTRL_DIV16;
6be4826e RK	276	}
6be4826e RK	277
6be4826e	278	writel(0xffff, base + TIMER_LOAD);
bb9ea778	279	writel(ctrl, base + TIMER_CTRL);
6be4826e	280
c5039f52	281	clocksource_mmio_init(base + TIMER_VALUE, "timer2",
bb76079a	282	rate, 200, 16, clocksource_mmio_readl_down);
a9d6d151	283	setup_sched_clock(integrator_read_sched_clock, 16, rate);
6be4826e RK	284	}
6be4826e RK	285
4980f9bc	286	static void __iomem * clkevt_base;
6be4826e RK	287
	288	/*
	289	* IRQ handler for the timer
	290	*/
	291	static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id)
	292	{
	293	struct clock_event_device *evt = dev_id;
	294
	295	/* clear the interrupt */
	296	writel(1, clkevt_base + TIMER_INTCLR);
	297
	298	evt->event_handler(evt);
	299
	300	return IRQ_HANDLED;
	301	}
	302
	303	static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
	304	{
	305	u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
	306
02f56321 LW	307	/* Disable timer */
02f56321 LW	308	writel(ctrl, clkevt_base + TIMER_CTRL);
6be4826e	309
02f56321 LW	310	switch (mode) {
	311	case CLOCK_EVT_MODE_PERIODIC:
	312	/* Enable the timer and start the periodic tick */
6be4826e RK	313	writel(timer_reload, clkevt_base + TIMER_LOAD);
6be4826e RK	314	ctrl \|= TIMER_CTRL_PERIODIC \| TIMER_CTRL_ENABLE;
02f56321 LW	315	writel(ctrl, clkevt_base + TIMER_CTRL);
	316	break;
	317	case CLOCK_EVT_MODE_ONESHOT:
	318	/* Leave the timer disabled, .set_next_event will enable it */
	319	ctrl &= ~TIMER_CTRL_PERIODIC;
	320	writel(ctrl, clkevt_base + TIMER_CTRL);
	321	break;
	322	case CLOCK_EVT_MODE_UNUSED:
	323	case CLOCK_EVT_MODE_SHUTDOWN:
	324	case CLOCK_EVT_MODE_RESUME:
	325	default:
	326	/* Just leave in disabled state */
	327	break;
6be4826e RK	328	}
6be4826e RK	329
6be4826e RK	330	}
	331
	332	static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt)
	333	{
	334	unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
	335
	336	writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
	337	writel(next, clkevt_base + TIMER_LOAD);
	338	writel(ctrl \| TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
	339
	340	return 0;
	341	}
	342
	343	static struct clock_event_device integrator_clockevent = {
	344	.name = "timer1",
02f56321	345	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
6be4826e RK	346	.set_mode = clkevt_set_mode,
	347	.set_next_event = clkevt_set_next_event,
	348	.rating = 300,
6be4826e RK	349	};
	350
	351	static struct irqaction integrator_timer_irq = {
	352	.name = "timer",
	353	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL,
	354	.handler = integrator_timer_interrupt,
	355	.dev_id = &integrator_clockevent,
	356	};
	357
4980f9bc LW	358	static void integrator_clockevent_init(unsigned long inrate,
4980f9bc LW	359	void __iomem *base, int irq)
6be4826e	360	{
bb76079a	361	unsigned long rate = inrate;
6be4826e RK	362	unsigned int ctrl = 0;
6be4826e RK	363
4980f9bc	364	clkevt_base = base;
6d8ce712	365	/* Calculate and program a divisor */
bb76079a LW	366	if (rate > 0x100000 * HZ) {
bb76079a LW	367	rate /= 256;
6be4826e	368	ctrl \|= TIMER_CTRL_DIV256;
bb76079a LW	369	} else if (rate > 0x10000 * HZ) {
bb76079a LW	370	rate /= 16;
6be4826e RK	371	ctrl \|= TIMER_CTRL_DIV16;
6be4826e RK	372	}
bb76079a	373	timer_reload = rate / HZ;
6be4826e RK	374	writel(ctrl, clkevt_base + TIMER_CTRL);
6be4826e RK	375
4980f9bc	376	setup_irq(irq, &integrator_timer_irq);
6d8ce712	377	clockevents_config_and_register(&integrator_clockevent,
bb76079a	378	rate,
6d8ce712 LW	379	1,
6d8ce712 LW	380	0xffffU);
6be4826e RK	381	}
6be4826e RK	382
a613163d LW	383	void __init ap_init_early(void)
	384	{
	385	}
	386
4980f9bc LW	387	#ifdef CONFIG_OF
	388
	389	static void __init ap_init_timer_of(void)
	390	{
	391	struct device_node *node;
	392	const char *path;
	393	void __iomem *base;
	394	int err;
	395	int irq;
	396	struct clk *clk;
	397	unsigned long rate;
	398
	399	clk = clk_get_sys("ap_timer", NULL);
	400	BUG_ON(IS_ERR(clk));
	401	clk_prepare_enable(clk);
	402	rate = clk_get_rate(clk);
	403
	404	err = of_property_read_string(of_aliases,
	405	"arm,timer-primary", &path);
	406	if (WARN_ON(err))
	407	return;
	408	node = of_find_node_by_path(path);
	409	base = of_iomap(node, 0);
	410	if (WARN_ON(!base))
	411	return;
	412	writel(0, base + TIMER_CTRL);
	413	integrator_clocksource_init(rate, base);
	414
	415	err = of_property_read_string(of_aliases,
	416	"arm,timer-secondary", &path);
	417	if (WARN_ON(err))
	418	return;
	419	node = of_find_node_by_path(path);
	420	base = of_iomap(node, 0);
	421	if (WARN_ON(!base))
	422	return;
	423	irq = irq_of_parse_and_map(node, 0);
	424	writel(0, base + TIMER_CTRL);
	425	integrator_clockevent_init(rate, base, irq);
	426	}
	427
	428	static struct sys_timer ap_of_timer = {
	429	.init = ap_init_timer_of,
	430	};
	431
	432	static const struct of_device_id fpga_irq_of_match[] __initconst = {
	433	{ .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
	434	{ /* Sentinel */ }
	435	};
	436
	437	static void __init ap_init_irq_of(void)
	438	{
	439	/* disable core module IRQs */
	440	writel(0xffffffffU, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
	441	of_irq_init(fpga_irq_of_match);
	442	integrator_clk_init(false);
	443	}
	444
4672cddf LW	445	/* For the Device Tree, add in the UART callbacks as AUXDATA */
	446	static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = {
	447	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
	448	"rtc", NULL),
	449	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
	450	"uart0", &integrator_uart_data),
	451	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
	452	"uart1", &integrator_uart_data),
	453	OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
	454	"kmi0", NULL),
	455	OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
	456	"kmi1", NULL),
73efd530 LW	457	OF_DEV_AUXDATA("cfi-flash", INTEGRATOR_FLASH_BASE,
73efd530 LW	458	"physmap-flash", &ap_flash_data),
4672cddf LW	459	{ /* sentinel */ },
	460	};
	461
	462	static void __init ap_init_of(void)
	463	{
	464	unsigned long sc_dec;
e67ae6be LW	465	struct device_node *root;
	466	struct device_node *syscon;
	467	struct device *parent;
	468	struct soc_device *soc_dev;
	469	struct soc_device_attribute *soc_dev_attr;
	470	u32 ap_sc_id;
	471	int err;
4672cddf LW	472	int i;
4672cddf LW	473
e67ae6be LW	474	/* Here we create an SoC device for the root node */
	475	root = of_find_node_by_path("/");
	476	if (!root)
	477	return;
	478	syscon = of_find_node_by_path("/syscon");
	479	if (!syscon)
	480	return;
	481
	482	ap_syscon_base = of_iomap(syscon, 0);
	483	if (!ap_syscon_base)
	484	return;
	485
	486	ap_sc_id = readl(ap_syscon_base);
	487
	488	soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
	489	if (!soc_dev_attr)
	490	return;
	491
	492	err = of_property_read_string(root, "compatible",
	493	&soc_dev_attr->soc_id);
	494	if (err)
	495	return;
	496	err = of_property_read_string(root, "model", &soc_dev_attr->machine);
	497	if (err)
	498	return;
	499	soc_dev_attr->family = "Integrator";
	500	soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c",
	501	'A' + (ap_sc_id & 0x0f));
	502
	503	soc_dev = soc_device_register(soc_dev_attr);
	504	if (IS_ERR_OR_NULL(soc_dev)) {
	505	kfree(soc_dev_attr->revision);
	506	kfree(soc_dev_attr);
	507	return;
	508	}
	509
	510	parent = soc_device_to_device(soc_dev);
	511
	512	if (!IS_ERR_OR_NULL(parent))
	513	integrator_init_sysfs(parent, ap_sc_id);
	514
	515	of_platform_populate(root, of_default_bus_match_table,
	516	ap_auxdata_lookup, parent);
4672cddf	517
83feba51	518	sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET);
4672cddf LW	519	for (i = 0; i < 4; i++) {
	520	struct lm_device *lmdev;
	521
	522	if ((sc_dec & (16 << i)) == 0)
	523	continue;
	524
	525	lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
	526	if (!lmdev)
	527	continue;
	528
	529	lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
	530	lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
	531	lmdev->resource.flags = IORESOURCE_MEM;
	532	lmdev->irq = IRQ_AP_EXPINT0 + i;
	533	lmdev->id = i;
	534
	535	lm_device_register(lmdev);
	536	}
	537	}
	538
4980f9bc LW	539	static const char * ap_dt_board_compat[] = {
	540	"arm,integrator-ap",
	541	NULL,
	542	};
	543
	544	DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
	545	.reserve = integrator_reserve,
	546	.map_io = ap_map_io,
	547	.nr_irqs = NR_IRQS_INTEGRATOR_AP,
	548	.init_early = ap_init_early,
	549	.init_irq = ap_init_irq_of,
	550	.handle_irq = fpga_handle_irq,
	551	.timer = &ap_of_timer,
4672cddf	552	.init_machine = ap_init_of,
4980f9bc LW	553	.restart = integrator_restart,
	554	.dt_compat = ap_dt_board_compat,
	555	MACHINE_END
	556
	557	#endif
	558
	559	#ifdef CONFIG_ATAGS
	560
83feba51 LW	561	/*
	562	* For the ATAG boot some static mappings are needed. This will
	563	* go away with the ATAG support down the road.
	564	*/
	565
	566	static struct map_desc ap_io_desc_atag[] __initdata = {
	567	{
	568	.virtual = IO_ADDRESS(INTEGRATOR_SC_BASE),
	569	.pfn = __phys_to_pfn(INTEGRATOR_SC_BASE),
	570	.length = SZ_4K,
	571	.type = MT_DEVICE
	572	},
	573	};
	574
	575	static void __init ap_map_io_atag(void)
	576	{
	577	iotable_init(ap_io_desc_atag, ARRAY_SIZE(ap_io_desc_atag));
	578	ap_syscon_base = __io_address(INTEGRATOR_SC_BASE);
	579	ap_map_io();
	580	}
	581
6be4826e	582	/*
4980f9bc LW	583	* This is where non-devicetree initialization code is collected and stashed
4980f9bc LW	584	* for eventual deletion.
6be4826e	585	*/
4980f9bc	586
73efd530 LW	587	static struct resource cfi_flash_resource = {
	588	.start = INTEGRATOR_FLASH_BASE,
	589	.end = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
	590	.flags = IORESOURCE_MEM,
	591	};
	592
	593	static struct platform_device cfi_flash_device = {
	594	.name = "physmap-flash",
	595	.id = 0,
	596	.dev = {
	597	.platform_data = &ap_flash_data,
	598	},
	599	.num_resources = 1,
	600	.resource = &cfi_flash_resource,
	601	};
	602
1da177e4 LT	603	static void __init ap_init_timer(void)
1da177e4 LT	604	{
bb76079a LW	605	struct clk *clk;
	606	unsigned long rate;
	607
	608	clk = clk_get_sys("ap_timer", NULL);
	609	BUG_ON(IS_ERR(clk));
8bb8148c	610	clk_prepare_enable(clk);
bb76079a	611	rate = clk_get_rate(clk);
6be4826e RK	612
	613	writel(0, TIMER0_VA_BASE + TIMER_CTRL);
	614	writel(0, TIMER1_VA_BASE + TIMER_CTRL);
	615	writel(0, TIMER2_VA_BASE + TIMER_CTRL);
	616
4980f9bc LW	617	integrator_clocksource_init(rate, (void __iomem *)TIMER2_VA_BASE);
	618	integrator_clockevent_init(rate, (void __iomem *)TIMER1_VA_BASE,
	619	IRQ_TIMERINT1);
1da177e4 LT	620	}
	621
	622	static struct sys_timer ap_timer = {
	623	.init = ap_init_timer,
1da177e4 LT	624	};
1da177e4 LT	625
4980f9bc LW	626	#define INTEGRATOR_SC_VALID_INT 0x003fffff
	627
	628	static void __init ap_init_irq(void)
	629	{
	630	/* Disable all interrupts initially. */
	631	/* Do the core module ones */
	632	writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
	633
	634	/* do the header card stuff next */
	635	writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
	636	writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
	637
	638	fpga_irq_init(VA_IC_BASE, "SC", IRQ_PIC_START,
	639	-1, INTEGRATOR_SC_VALID_INT, NULL);
	640	integrator_clk_init(false);
	641	}
	642
4672cddf LW	643	static void __init ap_init(void)
	644	{
	645	unsigned long sc_dec;
	646	int i;
	647
	648	platform_device_register(&cfi_flash_device);
	649
83feba51	650	sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET);
4672cddf LW	651	for (i = 0; i < 4; i++) {
	652	struct lm_device *lmdev;
	653
	654	if ((sc_dec & (16 << i)) == 0)
	655	continue;
	656
	657	lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
	658	if (!lmdev)
	659	continue;
	660
	661	lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
	662	lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
	663	lmdev->resource.flags = IORESOURCE_MEM;
	664	lmdev->irq = IRQ_AP_EXPINT0 + i;
	665	lmdev->id = i;
	666
	667	lm_device_register(lmdev);
	668	}
	669
	670	integrator_init(false);
	671	}
	672
1da177e4	673	MACHINE_START(INTEGRATOR, "ARM-Integrator")
e9dea0c6	674	/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
c5e587a2	675	.atag_offset = 0x100,
98c672cf	676	.reserve = integrator_reserve,
83feba51	677	.map_io = ap_map_io_atag,
695436e3	678	.nr_irqs = NR_IRQS_INTEGRATOR_AP,
a613163d	679	.init_early = ap_init_early,
e9dea0c6	680	.init_irq = ap_init_irq,
3108e6ab	681	.handle_irq = fpga_handle_irq,
1da177e4	682	.timer = &ap_timer,
e9dea0c6	683	.init_machine = ap_init,
6338b66f	684	.restart = integrator_restart,
1da177e4	685	MACHINE_END
4980f9bc LW	686
4980f9bc LW	687	#endif