[deliverable/linux.git] / arch / arm / mach-integrator / integrator_ap.c

/*
 *  linux/arch/arm/mach-integrator/integrator_ap.c
 *
 *  Copyright (C) 2000-2003 Deep Blue Solutions Ltd
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/syscore_ops.h>
#include <linux/amba/bus.h>
#include <linux/amba/kmi.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/mtd/physmap.h>
#include <linux/clk.h>

#include <mach/hardware.h>
#include <mach/platform.h>
#include <asm/hardware/arm_timer.h>
#include <asm/irq.h>
#include <asm/setup.h>
#include <asm/param.h>		/* HZ */
#include <asm/mach-types.h>

#include <mach/lm.h>

#include <asm/mach/arch.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>

#include <plat/fpga-irq.h>

#include "common.h"

/* 
 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
 * is the (PA >> 12).
 *
 * Setup a VA for the Integrator interrupt controller (for header #0,
 * just for now).
 */
#define VA_IC_BASE	__io_address(INTEGRATOR_IC_BASE)
#define VA_SC_BASE	__io_address(INTEGRATOR_SC_BASE)
#define VA_EBI_BASE	__io_address(INTEGRATOR_EBI_BASE)
#define VA_CMIC_BASE	__io_address(INTEGRATOR_HDR_IC)

/*
 * Logical      Physical
 * e8000000	40000000	PCI memory		PHYS_PCI_MEM_BASE	(max 512M)
 * ec000000	61000000	PCI config space	PHYS_PCI_CONFIG_BASE	(max 16M)
 * ed000000	62000000	PCI V3 regs		PHYS_PCI_V3_BASE	(max 64k)
 * ee000000	60000000	PCI IO			PHYS_PCI_IO_BASE	(max 16M)
 * ef000000			Cache flush
 * f1000000	10000000	Core module registers
 * f1100000	11000000	System controller registers
 * f1200000	12000000	EBI registers
 * f1300000	13000000	Counter/Timer
 * f1400000	14000000	Interrupt controller
 * f1600000	16000000	UART 0
 * f1700000	17000000	UART 1
 * f1a00000	1a000000	Debug LEDs
 * f1b00000	1b000000	GPIO
 */

static struct map_desc ap_io_desc[] __initdata = {
	{
		.virtual	= IO_ADDRESS(INTEGRATOR_HDR_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_HDR_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_SC_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_SC_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_EBI_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_EBI_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_CT_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_CT_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_IC_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_IC_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_UART0_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_UART0_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_UART1_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_UART1_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_DBG_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_DBG_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= PCI_MEMORY_VADDR,
		.pfn		= __phys_to_pfn(PHYS_PCI_MEM_BASE),
		.length		= SZ_16M,
		.type		= MT_DEVICE
	}, {
		.virtual	= PCI_CONFIG_VADDR,
		.pfn		= __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
		.length		= SZ_16M,
		.type		= MT_DEVICE
	}, {
		.virtual	= PCI_V3_VADDR,
		.pfn		= __phys_to_pfn(PHYS_PCI_V3_BASE),
		.length		= SZ_64K,
		.type		= MT_DEVICE
	}, {
		.virtual	= PCI_IO_VADDR,
		.pfn		= __phys_to_pfn(PHYS_PCI_IO_BASE),
		.length		= SZ_64K,
		.type		= MT_DEVICE
	}
};

static void __init ap_map_io(void)
{
	iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
}

#define INTEGRATOR_SC_VALID_INT	0x003fffff

static struct fpga_irq_data sc_irq_data = {
	.base		= VA_IC_BASE,
	.irq_start	= 0,
	.chip.name	= "SC",
};

static void __init ap_init_irq(void)
{
	/* Disable all interrupts initially. */
	/* Do the core module ones */
	writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);

	/* do the header card stuff next */
	writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
	writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);

	fpga_irq_init(-1, INTEGRATOR_SC_VALID_INT, &sc_irq_data);
}

#ifdef CONFIG_PM
static unsigned long ic_irq_enable;

static int irq_suspend(void)
{
	ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
	return 0;
}

static void irq_resume(void)
{
	/* disable all irq sources */
	writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
	writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
	writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);

	writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
}
#else
#define irq_suspend NULL
#define irq_resume NULL
#endif

static struct syscore_ops irq_syscore_ops = {
	.suspend	= irq_suspend,
	.resume		= irq_resume,
};

static int __init irq_syscore_init(void)
{
	register_syscore_ops(&irq_syscore_ops);

	return 0;
}

device_initcall(irq_syscore_init);

/*
 * Flash handling.
 */
#define SC_CTRLC (VA_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
#define SC_CTRLS (VA_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
#define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
#define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)

static int ap_flash_init(struct platform_device *dev)
{
	u32 tmp;

	writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);

	tmp = readl(EBI_CSR1) | INTEGRATOR_EBI_WRITE_ENABLE;
	writel(tmp, EBI_CSR1);

	if (!(readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) {
		writel(0xa05f, EBI_LOCK);
		writel(tmp, EBI_CSR1);
		writel(0, EBI_LOCK);
	}
	return 0;
}

static void ap_flash_exit(struct platform_device *dev)
{
	u32 tmp;

	writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);

	tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE;
	writel(tmp, EBI_CSR1);

	if (readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) {
		writel(0xa05f, EBI_LOCK);
		writel(tmp, EBI_CSR1);
		writel(0, EBI_LOCK);
	}
}

static void ap_flash_set_vpp(struct platform_device *pdev, int on)
{
	void __iomem *reg = on ? SC_CTRLS : SC_CTRLC;

	writel(INTEGRATOR_SC_CTRL_nFLVPPEN, reg);
}

static struct physmap_flash_data ap_flash_data = {
	.width		= 4,
	.init		= ap_flash_init,
	.exit		= ap_flash_exit,
	.set_vpp	= ap_flash_set_vpp,
};

static struct resource cfi_flash_resource = {
	.start		= INTEGRATOR_FLASH_BASE,
	.end		= INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
	.flags		= IORESOURCE_MEM,
};

static struct platform_device cfi_flash_device = {
	.name		= "physmap-flash",
	.id		= 0,
	.dev		= {
		.platform_data	= &ap_flash_data,
	},
	.num_resources	= 1,
	.resource	= &cfi_flash_resource,
};

static void __init ap_init(void)
{
	unsigned long sc_dec;
	int i;

	platform_device_register(&cfi_flash_device);

	sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
	for (i = 0; i < 4; i++) {
		struct lm_device *lmdev;

		if ((sc_dec & (16 << i)) == 0)
			continue;

		lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
		if (!lmdev)
			continue;

		lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
		lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
		lmdev->resource.flags = IORESOURCE_MEM;
		lmdev->irq = IRQ_AP_EXPINT0 + i;
		lmdev->id = i;

		lm_device_register(lmdev);
	}
}

/*
 * Where is the timer (VA)?
 */
#define TIMER0_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER0_BASE)
#define TIMER1_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER1_BASE)
#define TIMER2_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER2_BASE)

static unsigned long timer_reload;

static void integrator_clocksource_init(unsigned long inrate)
{
	void __iomem *base = (void __iomem *)TIMER2_VA_BASE;
	u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC;
	unsigned long rate = inrate;

	if (rate >= 1500000) {
		rate /= 16;
		ctrl |= TIMER_CTRL_DIV16;
	}

	writel(0xffff, base + TIMER_LOAD);
	writel(ctrl, base + TIMER_CTRL);

	clocksource_mmio_init(base + TIMER_VALUE, "timer2",
			rate, 200, 16, clocksource_mmio_readl_down);
}

static void __iomem * const clkevt_base = (void __iomem *)TIMER1_VA_BASE;

/*
 * IRQ handler for the timer
 */
static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	/* clear the interrupt */
	writel(1, clkevt_base + TIMER_INTCLR);

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
{
	u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;

	/* Disable timer */
	writel(ctrl, clkevt_base + TIMER_CTRL);

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		/* Enable the timer and start the periodic tick */
		writel(timer_reload, clkevt_base + TIMER_LOAD);
		ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
		writel(ctrl, clkevt_base + TIMER_CTRL);
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		/* Leave the timer disabled, .set_next_event will enable it */
		ctrl &= ~TIMER_CTRL_PERIODIC;
		writel(ctrl, clkevt_base + TIMER_CTRL);
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_RESUME:
	default:
		/* Just leave in disabled state */
		break;
	}

}

static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt)
{
	unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);

	writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
	writel(next, clkevt_base + TIMER_LOAD);
	writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);

	return 0;
}

static struct clock_event_device integrator_clockevent = {
	.name		= "timer1",
	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.set_mode	= clkevt_set_mode,
	.set_next_event	= clkevt_set_next_event,
	.rating		= 300,
};

static struct irqaction integrator_timer_irq = {
	.name		= "timer",
	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= integrator_timer_interrupt,
	.dev_id		= &integrator_clockevent,
};

static void integrator_clockevent_init(unsigned long inrate)
{
	unsigned long rate = inrate;
	unsigned int ctrl = 0;

	/* Calculate and program a divisor */
	if (rate > 0x100000 * HZ) {
		rate /= 256;
		ctrl |= TIMER_CTRL_DIV256;
	} else if (rate > 0x10000 * HZ) {
		rate /= 16;
		ctrl |= TIMER_CTRL_DIV16;
	}
	timer_reload = rate / HZ;
	writel(ctrl, clkevt_base + TIMER_CTRL);

	setup_irq(IRQ_TIMERINT1, &integrator_timer_irq);
	clockevents_config_and_register(&integrator_clockevent,
					rate,
					1,
					0xffffU);
}

/*
 * Set up timer(s).
 */
static void __init ap_init_timer(void)
{
	struct clk *clk;
	unsigned long rate;

	clk = clk_get_sys("ap_timer", NULL);
	BUG_ON(IS_ERR(clk));
	clk_enable(clk);
	rate = clk_get_rate(clk);

	writel(0, TIMER0_VA_BASE + TIMER_CTRL);
	writel(0, TIMER1_VA_BASE + TIMER_CTRL);
	writel(0, TIMER2_VA_BASE + TIMER_CTRL);

	integrator_clocksource_init(rate);
	integrator_clockevent_init(rate);
}

static struct sys_timer ap_timer = {
	.init		= ap_init_timer,
};

MACHINE_START(INTEGRATOR, "ARM-Integrator")
	/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
	.boot_params	= 0x00000100,
	.reserve	= integrator_reserve,
	.map_io		= ap_map_io,
	.init_early	= integrator_init_early,
	.init_irq	= ap_init_irq,
	.timer		= &ap_timer,
	.init_machine	= ap_init,
MACHINE_END
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-integrator/integrator_ap.c
	3	*
	4	* Copyright (C) 2000-2003 Deep Blue Solutions Ltd
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20	#include <linux/types.h>
	21	#include <linux/kernel.h>
	22	#include <linux/init.h>
	23	#include <linux/list.h>
d052d1be	24	#include <linux/platform_device.h>
1da177e4 LT	25	#include <linux/slab.h>
1da177e4 LT	26	#include <linux/string.h>
b7808056	27	#include <linux/syscore_ops.h>
a62c80e5 RK	28	#include <linux/amba/bus.h>
a62c80e5 RK	29	#include <linux/amba/kmi.h>
6be4826e RK	30	#include <linux/clocksource.h>
	31	#include <linux/clockchips.h>
	32	#include <linux/interrupt.h>
fced80c7	33	#include <linux/io.h>
f07e762e	34	#include <linux/mtd/physmap.h>
bb76079a	35	#include <linux/clk.h>
1da177e4	36
a09e64fb	37	#include <mach/hardware.h>
a285edcf	38	#include <mach/platform.h>
6be4826e	39	#include <asm/hardware/arm_timer.h>
1da177e4 LT	40	#include <asm/irq.h>
1da177e4 LT	41	#include <asm/setup.h>
4e57b681	42	#include <asm/param.h> /* HZ */
1da177e4	43	#include <asm/mach-types.h>
1da177e4	44
a09e64fb	45	#include <mach/lm.h>
1da177e4 LT	46
1da177e4 LT	47	#include <asm/mach/arch.h>
1da177e4 LT	48	#include <asm/mach/irq.h>
	49	#include <asm/mach/map.h>
	50	#include <asm/mach/time.h>
	51
c41b16f8 RK	52	#include <plat/fpga-irq.h>
c41b16f8 RK	53
98c672cf RK	54	#include "common.h"
98c672cf RK	55
1da177e4 LT	56	/*
	57	* All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
	58	* is the (PA >> 12).
	59	*
	60	* Setup a VA for the Integrator interrupt controller (for header #0,
	61	* just for now).
	62	*/
c41b16f8 RK	63	#define VA_IC_BASE __io_address(INTEGRATOR_IC_BASE)
	64	#define VA_SC_BASE __io_address(INTEGRATOR_SC_BASE)
	65	#define VA_EBI_BASE __io_address(INTEGRATOR_EBI_BASE)
	66	#define VA_CMIC_BASE __io_address(INTEGRATOR_HDR_IC)
1da177e4 LT	67
	68	/*
	69	* Logical Physical
	70	* e8000000 40000000 PCI memory PHYS_PCI_MEM_BASE (max 512M)
	71	* ec000000 61000000 PCI config space PHYS_PCI_CONFIG_BASE (max 16M)
	72	* ed000000 62000000 PCI V3 regs PHYS_PCI_V3_BASE (max 64k)
	73	* ee000000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M)
	74	* ef000000 Cache flush
	75	* f1000000 10000000 Core module registers
	76	* f1100000 11000000 System controller registers
	77	* f1200000 12000000 EBI registers
	78	* f1300000 13000000 Counter/Timer
	79	* f1400000 14000000 Interrupt controller
	80	* f1600000 16000000 UART 0
	81	* f1700000 17000000 UART 1
	82	* f1a00000 1a000000 Debug LEDs
	83	* f1b00000 1b000000 GPIO
	84	*/
	85
	86	static struct map_desc ap_io_desc[] __initdata = {
c8d27298 DS	87	{
	88	.virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
	89	.pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE),
	90	.length = SZ_4K,
	91	.type = MT_DEVICE
	92	}, {
	93	.virtual = IO_ADDRESS(INTEGRATOR_SC_BASE),
	94	.pfn = __phys_to_pfn(INTEGRATOR_SC_BASE),
	95	.length = SZ_4K,
	96	.type = MT_DEVICE
	97	}, {
	98	.virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE),
	99	.pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE),
	100	.length = SZ_4K,
	101	.type = MT_DEVICE
	102	}, {
	103	.virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
	104	.pfn = __phys_to_pfn(INTEGRATOR_CT_BASE),
	105	.length = SZ_4K,
	106	.type = MT_DEVICE
	107	}, {
	108	.virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
	109	.pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
	110	.length = SZ_4K,
	111	.type = MT_DEVICE
	112	}, {
	113	.virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
	114	.pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
	115	.length = SZ_4K,
	116	.type = MT_DEVICE
	117	}, {
	118	.virtual = IO_ADDRESS(INTEGRATOR_UART1_BASE),
	119	.pfn = __phys_to_pfn(INTEGRATOR_UART1_BASE),
	120	.length = SZ_4K,
	121	.type = MT_DEVICE
	122	}, {
	123	.virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
	124	.pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
	125	.length = SZ_4K,
	126	.type = MT_DEVICE
	127	}, {
da7ba956 RK	128	.virtual = IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE),
da7ba956 RK	129	.pfn = __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE),
c8d27298 DS	130	.length = SZ_4K,
	131	.type = MT_DEVICE
	132	}, {
	133	.virtual = PCI_MEMORY_VADDR,
	134	.pfn = __phys_to_pfn(PHYS_PCI_MEM_BASE),
	135	.length = SZ_16M,
	136	.type = MT_DEVICE
	137	}, {
	138	.virtual = PCI_CONFIG_VADDR,
	139	.pfn = __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
	140	.length = SZ_16M,
	141	.type = MT_DEVICE
	142	}, {
	143	.virtual = PCI_V3_VADDR,
	144	.pfn = __phys_to_pfn(PHYS_PCI_V3_BASE),
	145	.length = SZ_64K,
	146	.type = MT_DEVICE
	147	}, {
	148	.virtual = PCI_IO_VADDR,
	149	.pfn = __phys_to_pfn(PHYS_PCI_IO_BASE),
	150	.length = SZ_64K,
	151	.type = MT_DEVICE
	152	}
1da177e4 LT	153	};
	154
	155	static void __init ap_map_io(void)
	156	{
	157	iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
	158	}
	159
	160	#define INTEGRATOR_SC_VALID_INT 0x003fffff
	161
c41b16f8 RK	162	static struct fpga_irq_data sc_irq_data = {
	163	.base = VA_IC_BASE,
	164	.irq_start = 0,
	165	.chip.name = "SC",
1da177e4 LT	166	};
	167
	168	static void __init ap_init_irq(void)
	169	{
1da177e4 LT	170	/* Disable all interrupts initially. */
	171	/* Do the core module ones */
	172	writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
	173
	174	/* do the header card stuff next */
	175	writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
	176	writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
	177
c41b16f8	178	fpga_irq_init(-1, INTEGRATOR_SC_VALID_INT, &sc_irq_data);
1da177e4 LT	179	}
	180
	181	#ifdef CONFIG_PM
	182	static unsigned long ic_irq_enable;
	183
b7808056	184	static int irq_suspend(void)
1da177e4 LT	185	{
	186	ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
	187	return 0;
	188	}
	189
b7808056	190	static void irq_resume(void)
1da177e4 LT	191	{
	192	/* disable all irq sources */
	193	writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
	194	writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
	195	writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
	196
	197	writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
1da177e4 LT	198	}
	199	#else
	200	#define irq_suspend NULL
	201	#define irq_resume NULL
	202	#endif
	203
b7808056	204	static struct syscore_ops irq_syscore_ops = {
1da177e4 LT	205	.suspend = irq_suspend,
	206	.resume = irq_resume,
	207	};
	208
b7808056	209	static int __init irq_syscore_init(void)
1da177e4	210	{
b7808056 RW	211	register_syscore_ops(&irq_syscore_ops);
	212
	213	return 0;
1da177e4 LT	214	}
1da177e4 LT	215
b7808056	216	device_initcall(irq_syscore_init);
1da177e4 LT	217
	218	/*
	219	* Flash handling.
	220	*/
	221	#define SC_CTRLC (VA_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
	222	#define SC_CTRLS (VA_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
	223	#define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
	224	#define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
	225
f07e762e	226	static int ap_flash_init(struct platform_device *dev)
1da177e4 LT	227	{
	228	u32 tmp;
	229
	230	writel(INTEGRATOR_SC_CTRL_nFLVPPEN \| INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
	231
	232	tmp = readl(EBI_CSR1) \| INTEGRATOR_EBI_WRITE_ENABLE;
	233	writel(tmp, EBI_CSR1);
	234
	235	if (!(readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) {
	236	writel(0xa05f, EBI_LOCK);
	237	writel(tmp, EBI_CSR1);
	238	writel(0, EBI_LOCK);
	239	}
	240	return 0;
	241	}
	242
f07e762e	243	static void ap_flash_exit(struct platform_device *dev)
1da177e4 LT	244	{
	245	u32 tmp;
	246
	247	writel(INTEGRATOR_SC_CTRL_nFLVPPEN \| INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
	248
	249	tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE;
	250	writel(tmp, EBI_CSR1);
	251
	252	if (readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) {
	253	writel(0xa05f, EBI_LOCK);
	254	writel(tmp, EBI_CSR1);
	255	writel(0, EBI_LOCK);
	256	}
	257	}
	258
667f390b	259	static void ap_flash_set_vpp(struct platform_device *pdev, int on)
1da177e4	260	{
c41b16f8	261	void __iomem *reg = on ? SC_CTRLS : SC_CTRLC;
1da177e4 LT	262
	263	writel(INTEGRATOR_SC_CTRL_nFLVPPEN, reg);
	264	}
	265
f07e762e	266	static struct physmap_flash_data ap_flash_data = {
1da177e4 LT	267	.width = 4,
	268	.init = ap_flash_init,
	269	.exit = ap_flash_exit,
	270	.set_vpp = ap_flash_set_vpp,
	271	};
	272
	273	static struct resource cfi_flash_resource = {
	274	.start = INTEGRATOR_FLASH_BASE,
	275	.end = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
	276	.flags = IORESOURCE_MEM,
	277	};
	278
	279	static struct platform_device cfi_flash_device = {
f07e762e	280	.name = "physmap-flash",
1da177e4 LT	281	.id = 0,
	282	.dev = {
	283	.platform_data = &ap_flash_data,
	284	},
	285	.num_resources = 1,
	286	.resource = &cfi_flash_resource,
	287	};
	288
	289	static void __init ap_init(void)
	290	{
	291	unsigned long sc_dec;
	292	int i;
	293
	294	platform_device_register(&cfi_flash_device);
	295
	296	sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
	297	for (i = 0; i < 4; i++) {
	298	struct lm_device *lmdev;
	299
	300	if ((sc_dec & (16 << i)) == 0)
	301	continue;
	302
d2a02b93	303	lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
1da177e4 LT	304	if (!lmdev)
	305	continue;
	306
1da177e4 LT	307	lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
	308	lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
	309	lmdev->resource.flags = IORESOURCE_MEM;
	310	lmdev->irq = IRQ_AP_EXPINT0 + i;
	311	lmdev->id = i;
	312
	313	lm_device_register(lmdev);
	314	}
	315	}
	316
6be4826e RK	317	/*
	318	* Where is the timer (VA)?
	319	*/
	320	#define TIMER0_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER0_BASE)
	321	#define TIMER1_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER1_BASE)
	322	#define TIMER2_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER2_BASE)
	323
6be4826e RK	324	static unsigned long timer_reload;
6be4826e RK	325
bb76079a	326	static void integrator_clocksource_init(unsigned long inrate)
6be4826e	327	{
c5039f52	328	void __iomem base = (void __iomem )TIMER2_VA_BASE;
bb9ea778	329	u32 ctrl = TIMER_CTRL_ENABLE \| TIMER_CTRL_PERIODIC;
bb76079a	330	unsigned long rate = inrate;
6be4826e	331
bb76079a LW	332	if (rate >= 1500000) {
bb76079a LW	333	rate /= 16;
bb9ea778	334	ctrl \|= TIMER_CTRL_DIV16;
6be4826e RK	335	}
6be4826e RK	336
6be4826e	337	writel(0xffff, base + TIMER_LOAD);
bb9ea778	338	writel(ctrl, base + TIMER_CTRL);
6be4826e	339
c5039f52	340	clocksource_mmio_init(base + TIMER_VALUE, "timer2",
bb76079a	341	rate, 200, 16, clocksource_mmio_readl_down);
6be4826e RK	342	}
	343
	344	static void __iomem * const clkevt_base = (void __iomem *)TIMER1_VA_BASE;
	345
	346	/*
	347	* IRQ handler for the timer
	348	*/
	349	static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id)
	350	{
	351	struct clock_event_device *evt = dev_id;
	352
	353	/* clear the interrupt */
	354	writel(1, clkevt_base + TIMER_INTCLR);
	355
	356	evt->event_handler(evt);
	357
	358	return IRQ_HANDLED;
	359	}
	360
	361	static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
	362	{
	363	u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
	364
02f56321 LW	365	/* Disable timer */
02f56321 LW	366	writel(ctrl, clkevt_base + TIMER_CTRL);
6be4826e	367
02f56321 LW	368	switch (mode) {
	369	case CLOCK_EVT_MODE_PERIODIC:
	370	/* Enable the timer and start the periodic tick */
6be4826e RK	371	writel(timer_reload, clkevt_base + TIMER_LOAD);
6be4826e RK	372	ctrl \|= TIMER_CTRL_PERIODIC \| TIMER_CTRL_ENABLE;
02f56321 LW	373	writel(ctrl, clkevt_base + TIMER_CTRL);
	374	break;
	375	case CLOCK_EVT_MODE_ONESHOT:
	376	/* Leave the timer disabled, .set_next_event will enable it */
	377	ctrl &= ~TIMER_CTRL_PERIODIC;
	378	writel(ctrl, clkevt_base + TIMER_CTRL);
	379	break;
	380	case CLOCK_EVT_MODE_UNUSED:
	381	case CLOCK_EVT_MODE_SHUTDOWN:
	382	case CLOCK_EVT_MODE_RESUME:
	383	default:
	384	/* Just leave in disabled state */
	385	break;
6be4826e RK	386	}
6be4826e RK	387
6be4826e RK	388	}
	389
	390	static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt)
	391	{
	392	unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
	393
	394	writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
	395	writel(next, clkevt_base + TIMER_LOAD);
	396	writel(ctrl \| TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
	397
	398	return 0;
	399	}
	400
	401	static struct clock_event_device integrator_clockevent = {
	402	.name = "timer1",
02f56321	403	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
6be4826e RK	404	.set_mode = clkevt_set_mode,
	405	.set_next_event = clkevt_set_next_event,
	406	.rating = 300,
6be4826e RK	407	};
	408
	409	static struct irqaction integrator_timer_irq = {
	410	.name = "timer",
	411	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL,
	412	.handler = integrator_timer_interrupt,
	413	.dev_id = &integrator_clockevent,
	414	};
	415
bb76079a	416	static void integrator_clockevent_init(unsigned long inrate)
6be4826e	417	{
bb76079a	418	unsigned long rate = inrate;
6be4826e RK	419	unsigned int ctrl = 0;
6be4826e RK	420
6d8ce712	421	/* Calculate and program a divisor */
bb76079a LW	422	if (rate > 0x100000 * HZ) {
bb76079a LW	423	rate /= 256;
6be4826e	424	ctrl \|= TIMER_CTRL_DIV256;
bb76079a LW	425	} else if (rate > 0x10000 * HZ) {
bb76079a LW	426	rate /= 16;
6be4826e RK	427	ctrl \|= TIMER_CTRL_DIV16;
6be4826e RK	428	}
bb76079a	429	timer_reload = rate / HZ;
6be4826e RK	430	writel(ctrl, clkevt_base + TIMER_CTRL);
6be4826e RK	431
6be4826e	432	setup_irq(IRQ_TIMERINT1, &integrator_timer_irq);
6d8ce712	433	clockevents_config_and_register(&integrator_clockevent,
bb76079a	434	rate,
6d8ce712 LW	435	1,
6d8ce712 LW	436	0xffffU);
6be4826e RK	437	}
	438
	439	/*
	440	* Set up timer(s).
	441	*/
1da177e4 LT	442	static void __init ap_init_timer(void)
1da177e4 LT	443	{
bb76079a LW	444	struct clk *clk;
	445	unsigned long rate;
	446
	447	clk = clk_get_sys("ap_timer", NULL);
	448	BUG_ON(IS_ERR(clk));
	449	clk_enable(clk);
	450	rate = clk_get_rate(clk);
6be4826e RK	451
	452	writel(0, TIMER0_VA_BASE + TIMER_CTRL);
	453	writel(0, TIMER1_VA_BASE + TIMER_CTRL);
	454	writel(0, TIMER2_VA_BASE + TIMER_CTRL);
	455
bb76079a LW	456	integrator_clocksource_init(rate);
bb76079a LW	457	integrator_clockevent_init(rate);
1da177e4 LT	458	}
	459
	460	static struct sys_timer ap_timer = {
	461	.init = ap_init_timer,
1da177e4 LT	462	};
	463
	464	MACHINE_START(INTEGRATOR, "ARM-Integrator")
e9dea0c6	465	/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
e9dea0c6	466	.boot_params = 0x00000100,
98c672cf	467	.reserve = integrator_reserve,
c735c987 RK	468	.map_io = ap_map_io,
c735c987 RK	469	.init_early = integrator_init_early,
e9dea0c6	470	.init_irq = ap_init_irq,
1da177e4	471	.timer = &ap_timer,
e9dea0c6	472	.init_machine = ap_init,
1da177e4	473	MACHINE_END