Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mach-integrator/integrator_cp.c | |
3 | * | |
4 | * Copyright (C) 2003 Deep Blue Solutions Ltd | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License. | |
9 | */ | |
10 | #include <linux/types.h> | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/list.h> | |
d052d1be | 14 | #include <linux/platform_device.h> |
1da177e4 | 15 | #include <linux/dma-mapping.h> |
1da177e4 | 16 | #include <linux/string.h> |
edbaa603 | 17 | #include <linux/device.h> |
a62c80e5 RK |
18 | #include <linux/amba/bus.h> |
19 | #include <linux/amba/kmi.h> | |
20 | #include <linux/amba/clcd.h> | |
6ef297f8 | 21 | #include <linux/amba/mmci.h> |
fced80c7 | 22 | #include <linux/io.h> |
2389d501 | 23 | #include <linux/irqchip/versatile-fpga.h> |
5a0e3ad6 | 24 | #include <linux/gfp.h> |
046dfa0a | 25 | #include <linux/mtd/physmap.h> |
a613163d | 26 | #include <linux/platform_data/clk-integrator.h> |
4980f9bc LW |
27 | #include <linux/of_irq.h> |
28 | #include <linux/of_address.h> | |
4672cddf | 29 | #include <linux/of_platform.h> |
64100a03 | 30 | #include <linux/sys_soc.h> |
1da177e4 | 31 | |
a09e64fb | 32 | #include <mach/hardware.h> |
a285edcf | 33 | #include <mach/platform.h> |
1da177e4 LT |
34 | #include <asm/setup.h> |
35 | #include <asm/mach-types.h> | |
5a46334a | 36 | #include <asm/hardware/arm_timer.h> |
c5a0adb5 | 37 | #include <asm/hardware/icst.h> |
1da177e4 | 38 | |
a09e64fb RK |
39 | #include <mach/cm.h> |
40 | #include <mach/lm.h> | |
695436e3 | 41 | #include <mach/irqs.h> |
1da177e4 LT |
42 | |
43 | #include <asm/mach/arch.h> | |
1da177e4 | 44 | #include <asm/mach/irq.h> |
1da177e4 LT |
45 | #include <asm/mach/map.h> |
46 | #include <asm/mach/time.h> | |
47 | ||
8a9618f5 | 48 | #include <asm/hardware/timer-sp.h> |
5a46334a | 49 | |
9dfec4fe | 50 | #include <plat/clcd.h> |
d77e270c | 51 | #include <plat/sched_clock.h> |
9dfec4fe | 52 | |
98c672cf RK |
53 | #include "common.h" |
54 | ||
e6fae083 LW |
55 | /* Base address to the CP controller */ |
56 | static void __iomem *intcp_con_base; | |
57 | ||
1da177e4 | 58 | #define INTCP_PA_FLASH_BASE 0x24000000 |
1da177e4 LT |
59 | |
60 | #define INTCP_PA_CLCD_BASE 0xc0000000 | |
61 | ||
1da177e4 LT |
62 | #define INTCP_FLASHPROG 0x04 |
63 | #define CINTEGRATOR_FLASHPROG_FLVPPEN (1 << 0) | |
64 | #define CINTEGRATOR_FLASHPROG_FLWREN (1 << 1) | |
65 | ||
66 | /* | |
67 | * Logical Physical | |
68 | * f1000000 10000000 Core module registers | |
69 | * f1100000 11000000 System controller registers | |
70 | * f1200000 12000000 EBI registers | |
71 | * f1300000 13000000 Counter/Timer | |
72 | * f1400000 14000000 Interrupt controller | |
73 | * f1600000 16000000 UART 0 | |
74 | * f1700000 17000000 UART 1 | |
75 | * f1a00000 1a000000 Debug LEDs | |
da7ba956 RK |
76 | * fc900000 c9000000 GPIO |
77 | * fca00000 ca000000 SIC | |
78 | * fcb00000 cb000000 CP system control | |
1da177e4 LT |
79 | */ |
80 | ||
060fd1be | 81 | static struct map_desc intcp_io_desc[] __initdata __maybe_unused = { |
c8d27298 DS |
82 | { |
83 | .virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE), | |
84 | .pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE), | |
85 | .length = SZ_4K, | |
86 | .type = MT_DEVICE | |
c8d27298 DS |
87 | }, { |
88 | .virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE), | |
89 | .pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE), | |
90 | .length = SZ_4K, | |
91 | .type = MT_DEVICE | |
92 | }, { | |
93 | .virtual = IO_ADDRESS(INTEGRATOR_CT_BASE), | |
94 | .pfn = __phys_to_pfn(INTEGRATOR_CT_BASE), | |
95 | .length = SZ_4K, | |
96 | .type = MT_DEVICE | |
97 | }, { | |
98 | .virtual = IO_ADDRESS(INTEGRATOR_IC_BASE), | |
99 | .pfn = __phys_to_pfn(INTEGRATOR_IC_BASE), | |
100 | .length = SZ_4K, | |
101 | .type = MT_DEVICE | |
102 | }, { | |
103 | .virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE), | |
104 | .pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE), | |
105 | .length = SZ_4K, | |
106 | .type = MT_DEVICE | |
c8d27298 DS |
107 | }, { |
108 | .virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE), | |
109 | .pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE), | |
110 | .length = SZ_4K, | |
111 | .type = MT_DEVICE | |
112 | }, { | |
da7ba956 RK |
113 | .virtual = IO_ADDRESS(INTEGRATOR_CP_GPIO_BASE), |
114 | .pfn = __phys_to_pfn(INTEGRATOR_CP_GPIO_BASE), | |
c8d27298 DS |
115 | .length = SZ_4K, |
116 | .type = MT_DEVICE | |
117 | }, { | |
da7ba956 RK |
118 | .virtual = IO_ADDRESS(INTEGRATOR_CP_SIC_BASE), |
119 | .pfn = __phys_to_pfn(INTEGRATOR_CP_SIC_BASE), | |
c8d27298 DS |
120 | .length = SZ_4K, |
121 | .type = MT_DEVICE | |
c8d27298 | 122 | } |
1da177e4 LT |
123 | }; |
124 | ||
125 | static void __init intcp_map_io(void) | |
126 | { | |
127 | iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc)); | |
128 | } | |
129 | ||
1da177e4 LT |
130 | /* |
131 | * Flash handling. | |
132 | */ | |
046dfa0a | 133 | static int intcp_flash_init(struct platform_device *dev) |
1da177e4 LT |
134 | { |
135 | u32 val; | |
136 | ||
e6fae083 | 137 | val = readl(intcp_con_base + INTCP_FLASHPROG); |
1da177e4 | 138 | val |= CINTEGRATOR_FLASHPROG_FLWREN; |
e6fae083 | 139 | writel(val, intcp_con_base + INTCP_FLASHPROG); |
1da177e4 LT |
140 | |
141 | return 0; | |
142 | } | |
143 | ||
046dfa0a | 144 | static void intcp_flash_exit(struct platform_device *dev) |
1da177e4 LT |
145 | { |
146 | u32 val; | |
147 | ||
e6fae083 | 148 | val = readl(intcp_con_base + INTCP_FLASHPROG); |
1da177e4 | 149 | val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN); |
e6fae083 | 150 | writel(val, intcp_con_base + INTCP_FLASHPROG); |
1da177e4 LT |
151 | } |
152 | ||
667f390b | 153 | static void intcp_flash_set_vpp(struct platform_device *pdev, int on) |
1da177e4 LT |
154 | { |
155 | u32 val; | |
156 | ||
e6fae083 | 157 | val = readl(intcp_con_base + INTCP_FLASHPROG); |
1da177e4 LT |
158 | if (on) |
159 | val |= CINTEGRATOR_FLASHPROG_FLVPPEN; | |
160 | else | |
161 | val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN; | |
e6fae083 | 162 | writel(val, intcp_con_base + INTCP_FLASHPROG); |
1da177e4 LT |
163 | } |
164 | ||
046dfa0a | 165 | static struct physmap_flash_data intcp_flash_data = { |
1da177e4 LT |
166 | .width = 4, |
167 | .init = intcp_flash_init, | |
168 | .exit = intcp_flash_exit, | |
169 | .set_vpp = intcp_flash_set_vpp, | |
170 | }; | |
171 | ||
1da177e4 LT |
172 | /* |
173 | * It seems that the card insertion interrupt remains active after | |
174 | * we've acknowledged it. We therefore ignore the interrupt, and | |
175 | * rely on reading it from the SIC. This also means that we must | |
176 | * clear the latched interrupt. | |
177 | */ | |
178 | static unsigned int mmc_status(struct device *dev) | |
179 | { | |
b7a3f8db | 180 | unsigned int status = readl(__io_address(0xca000000 + 4)); |
e6fae083 | 181 | writel(8, intcp_con_base + 8); |
1da177e4 LT |
182 | |
183 | return status & 8; | |
184 | } | |
185 | ||
6ef297f8 | 186 | static struct mmci_platform_data mmc_data = { |
1da177e4 LT |
187 | .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, |
188 | .status = mmc_status, | |
7fb2bbf4 RK |
189 | .gpio_wp = -1, |
190 | .gpio_cd = -1, | |
1da177e4 LT |
191 | }; |
192 | ||
1da177e4 LT |
193 | /* |
194 | * CLCD support | |
195 | */ | |
1da177e4 LT |
196 | /* |
197 | * Ensure VGA is selected. | |
198 | */ | |
199 | static void cp_clcd_enable(struct clcd_fb *fb) | |
200 | { | |
e6b9c1f8 RK |
201 | struct fb_var_screeninfo *var = &fb->fb.var; |
202 | u32 val = CM_CTRL_STATIC1 | CM_CTRL_STATIC2; | |
4774e226 | 203 | |
e6b9c1f8 RK |
204 | if (var->bits_per_pixel <= 8 || |
205 | (var->bits_per_pixel == 16 && var->green.length == 5)) | |
206 | /* Pseudocolor, RGB555, BGR555 */ | |
207 | val |= CM_CTRL_LCDMUXSEL_VGA555_TFT555; | |
4774e226 | 208 | else if (fb->fb.var.bits_per_pixel <= 16) |
e6b9c1f8 RK |
209 | /* truecolor RGB565 */ |
210 | val |= CM_CTRL_LCDMUXSEL_VGA565_TFT555; | |
4774e226 RK |
211 | else |
212 | val = 0; /* no idea for this, don't trust the docs */ | |
213 | ||
214 | cm_control(CM_CTRL_LCDMUXSEL_MASK| | |
215 | CM_CTRL_LCDEN0| | |
216 | CM_CTRL_LCDEN1| | |
217 | CM_CTRL_STATIC1| | |
218 | CM_CTRL_STATIC2| | |
219 | CM_CTRL_STATIC| | |
220 | CM_CTRL_n24BITEN, val); | |
1da177e4 LT |
221 | } |
222 | ||
1da177e4 LT |
223 | static int cp_clcd_setup(struct clcd_fb *fb) |
224 | { | |
9dfec4fe RK |
225 | fb->panel = versatile_clcd_get_panel("VGA"); |
226 | if (!fb->panel) | |
227 | return -EINVAL; | |
1da177e4 | 228 | |
9dfec4fe | 229 | return versatile_clcd_setup_dma(fb, SZ_1M); |
1da177e4 LT |
230 | } |
231 | ||
232 | static struct clcd_board clcd_data = { | |
233 | .name = "Integrator/CP", | |
9dfec4fe | 234 | .caps = CLCD_CAP_5551 | CLCD_CAP_RGB565 | CLCD_CAP_888, |
1da177e4 LT |
235 | .check = clcdfb_check, |
236 | .decode = clcdfb_decode, | |
237 | .enable = cp_clcd_enable, | |
238 | .setup = cp_clcd_setup, | |
9dfec4fe RK |
239 | .mmap = versatile_clcd_mmap_dma, |
240 | .remove = versatile_clcd_remove_dma, | |
1da177e4 LT |
241 | }; |
242 | ||
d77e270c RK |
243 | #define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28) |
244 | ||
c735c987 RK |
245 | static void __init intcp_init_early(void) |
246 | { | |
d77e270c RK |
247 | #ifdef CONFIG_PLAT_VERSATILE_SCHED_CLOCK |
248 | versatile_sched_clock_init(REFCOUNTER, 24000000); | |
249 | #endif | |
c735c987 RK |
250 | } |
251 | ||
6e3a78d9 | 252 | #ifdef CONFIG_OF |
4980f9bc LW |
253 | static const struct of_device_id fpga_irq_of_match[] __initconst = { |
254 | { .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, }, | |
255 | { /* Sentinel */ } | |
256 | }; | |
257 | ||
258 | static void __init intcp_init_irq_of(void) | |
1da177e4 | 259 | { |
4980f9bc LW |
260 | of_irq_init(fpga_irq_of_match); |
261 | integrator_clk_init(true); | |
262 | } | |
1da177e4 | 263 | |
4672cddf LW |
264 | /* |
265 | * For the Device Tree, add in the UART, MMC and CLCD specifics as AUXDATA | |
266 | * and enforce the bus names since these are used for clock lookups. | |
267 | */ | |
268 | static struct of_dev_auxdata intcp_auxdata_lookup[] __initdata = { | |
269 | OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE, | |
270 | "rtc", NULL), | |
271 | OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE, | |
379df279 | 272 | "uart0", NULL), |
4672cddf | 273 | OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE, |
379df279 | 274 | "uart1", NULL), |
4672cddf LW |
275 | OF_DEV_AUXDATA("arm,primecell", KMI0_BASE, |
276 | "kmi0", NULL), | |
277 | OF_DEV_AUXDATA("arm,primecell", KMI1_BASE, | |
278 | "kmi1", NULL), | |
279 | OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_MMC_BASE, | |
280 | "mmci", &mmc_data), | |
281 | OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_AACI_BASE, | |
282 | "aaci", &mmc_data), | |
283 | OF_DEV_AUXDATA("arm,primecell", INTCP_PA_CLCD_BASE, | |
284 | "clcd", &clcd_data), | |
73efd530 LW |
285 | OF_DEV_AUXDATA("cfi-flash", INTCP_PA_FLASH_BASE, |
286 | "physmap-flash", &intcp_flash_data), | |
4672cddf LW |
287 | { /* sentinel */ }, |
288 | }; | |
289 | ||
290 | static void __init intcp_init_of(void) | |
291 | { | |
64100a03 LW |
292 | struct device_node *root; |
293 | struct device_node *cpcon; | |
294 | struct device *parent; | |
295 | struct soc_device *soc_dev; | |
296 | struct soc_device_attribute *soc_dev_attr; | |
297 | u32 intcp_sc_id; | |
298 | int err; | |
299 | ||
300 | /* Here we create an SoC device for the root node */ | |
301 | root = of_find_node_by_path("/"); | |
302 | if (!root) | |
303 | return; | |
304 | cpcon = of_find_node_by_path("/cpcon"); | |
305 | if (!cpcon) | |
306 | return; | |
307 | ||
308 | intcp_con_base = of_iomap(cpcon, 0); | |
309 | if (!intcp_con_base) | |
310 | return; | |
311 | ||
312 | intcp_sc_id = readl(intcp_con_base); | |
313 | ||
314 | soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); | |
315 | if (!soc_dev_attr) | |
316 | return; | |
317 | ||
318 | err = of_property_read_string(root, "compatible", | |
319 | &soc_dev_attr->soc_id); | |
320 | if (err) | |
321 | return; | |
322 | err = of_property_read_string(root, "model", &soc_dev_attr->machine); | |
323 | if (err) | |
324 | return; | |
325 | soc_dev_attr->family = "Integrator"; | |
326 | soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c", | |
327 | 'A' + (intcp_sc_id & 0x0f)); | |
328 | ||
329 | soc_dev = soc_device_register(soc_dev_attr); | |
b269b170 | 330 | if (IS_ERR(soc_dev)) { |
64100a03 LW |
331 | kfree(soc_dev_attr->revision); |
332 | kfree(soc_dev_attr); | |
333 | return; | |
334 | } | |
335 | ||
336 | parent = soc_device_to_device(soc_dev); | |
b269b170 | 337 | integrator_init_sysfs(parent, intcp_sc_id); |
64100a03 LW |
338 | of_platform_populate(root, of_default_bus_match_table, |
339 | intcp_auxdata_lookup, parent); | |
4672cddf LW |
340 | } |
341 | ||
4980f9bc LW |
342 | static const char * intcp_dt_board_compat[] = { |
343 | "arm,integrator-cp", | |
344 | NULL, | |
345 | }; | |
1da177e4 | 346 | |
4980f9bc LW |
347 | DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)") |
348 | .reserve = integrator_reserve, | |
349 | .map_io = intcp_map_io, | |
4980f9bc LW |
350 | .init_early = intcp_init_early, |
351 | .init_irq = intcp_init_irq_of, | |
352 | .handle_irq = fpga_handle_irq, | |
4672cddf | 353 | .init_machine = intcp_init_of, |
4980f9bc LW |
354 | .restart = integrator_restart, |
355 | .dt_compat = intcp_dt_board_compat, | |
356 | MACHINE_END | |
357 | ||
358 | #endif | |
359 | ||
360 | #ifdef CONFIG_ATAGS | |
361 | ||
e6fae083 LW |
362 | /* |
363 | * For the ATAG boot some static mappings are needed. This will | |
364 | * go away with the ATAG support down the road. | |
365 | */ | |
366 | ||
367 | static struct map_desc intcp_io_desc_atag[] __initdata = { | |
368 | { | |
369 | .virtual = IO_ADDRESS(INTEGRATOR_CP_CTL_BASE), | |
370 | .pfn = __phys_to_pfn(INTEGRATOR_CP_CTL_BASE), | |
371 | .length = SZ_4K, | |
372 | .type = MT_DEVICE | |
373 | }, | |
374 | }; | |
375 | ||
376 | static void __init intcp_map_io_atag(void) | |
377 | { | |
378 | iotable_init(intcp_io_desc_atag, ARRAY_SIZE(intcp_io_desc_atag)); | |
379 | intcp_con_base = __io_address(INTEGRATOR_CP_CTL_BASE); | |
380 | intcp_map_io(); | |
381 | } | |
382 | ||
383 | ||
4980f9bc LW |
384 | /* |
385 | * This is where non-devicetree initialization code is collected and stashed | |
386 | * for eventual deletion. | |
387 | */ | |
388 | ||
73efd530 LW |
389 | #define INTCP_FLASH_SIZE SZ_32M |
390 | ||
391 | static struct resource intcp_flash_resource = { | |
392 | .start = INTCP_PA_FLASH_BASE, | |
393 | .end = INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1, | |
394 | .flags = IORESOURCE_MEM, | |
395 | }; | |
396 | ||
397 | static struct platform_device intcp_flash_device = { | |
398 | .name = "physmap-flash", | |
399 | .id = 0, | |
400 | .dev = { | |
401 | .platform_data = &intcp_flash_data, | |
402 | }, | |
403 | .num_resources = 1, | |
404 | .resource = &intcp_flash_resource, | |
405 | }; | |
406 | ||
407 | #define INTCP_ETH_SIZE 0x10 | |
408 | ||
409 | static struct resource smc91x_resources[] = { | |
410 | [0] = { | |
411 | .start = INTEGRATOR_CP_ETH_BASE, | |
412 | .end = INTEGRATOR_CP_ETH_BASE + INTCP_ETH_SIZE - 1, | |
413 | .flags = IORESOURCE_MEM, | |
414 | }, | |
415 | [1] = { | |
416 | .start = IRQ_CP_ETHINT, | |
417 | .end = IRQ_CP_ETHINT, | |
418 | .flags = IORESOURCE_IRQ, | |
419 | }, | |
420 | }; | |
421 | ||
422 | static struct platform_device smc91x_device = { | |
423 | .name = "smc91x", | |
424 | .id = 0, | |
425 | .num_resources = ARRAY_SIZE(smc91x_resources), | |
426 | .resource = smc91x_resources, | |
427 | }; | |
428 | ||
429 | static struct platform_device *intcp_devs[] __initdata = { | |
430 | &intcp_flash_device, | |
431 | &smc91x_device, | |
432 | }; | |
433 | ||
4980f9bc LW |
434 | #define INTCP_VA_CIC_BASE __io_address(INTEGRATOR_HDR_BASE + 0x40) |
435 | #define INTCP_VA_PIC_BASE __io_address(INTEGRATOR_IC_BASE) | |
436 | #define INTCP_VA_SIC_BASE __io_address(INTEGRATOR_CP_SIC_BASE) | |
437 | ||
438 | static void __init intcp_init_irq(void) | |
439 | { | |
440 | u32 pic_mask, cic_mask, sic_mask; | |
441 | ||
442 | /* These masks are for the HW IRQ registers */ | |
da72a66b | 443 | pic_mask = ~((~0u) << (11 - 0)); |
4980f9bc LW |
444 | pic_mask |= (~((~0u) << (29 - 22))) << 22; |
445 | cic_mask = ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START)); | |
446 | sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START)); | |
447 | ||
448 | /* | |
449 | * Disable all interrupt sources | |
450 | */ | |
451 | writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR); | |
452 | writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR); | |
453 | writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR); | |
454 | writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR); | |
455 | writel(sic_mask, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR); | |
456 | writel(sic_mask, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR); | |
457 | ||
458 | fpga_irq_init(INTCP_VA_PIC_BASE, "PIC", IRQ_PIC_START, | |
459 | -1, pic_mask, NULL); | |
460 | ||
461 | fpga_irq_init(INTCP_VA_CIC_BASE, "CIC", IRQ_CIC_START, | |
462 | -1, cic_mask, NULL); | |
463 | ||
464 | fpga_irq_init(INTCP_VA_SIC_BASE, "SIC", IRQ_SIC_START, | |
465 | IRQ_CP_CPPLDINT, sic_mask, NULL); | |
466 | ||
467 | integrator_clk_init(true); | |
1da177e4 LT |
468 | } |
469 | ||
5a46334a RK |
470 | #define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE) |
471 | #define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE) | |
472 | #define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE) | |
1da177e4 | 473 | |
6bb27d73 | 474 | static void __init cp_timer_init(void) |
1da177e4 | 475 | { |
5a46334a RK |
476 | writel(0, TIMER0_VA_BASE + TIMER_CTRL); |
477 | writel(0, TIMER1_VA_BASE + TIMER_CTRL); | |
478 | writel(0, TIMER2_VA_BASE + TIMER_CTRL); | |
479 | ||
fb593cf3 | 480 | sp804_clocksource_init(TIMER2_VA_BASE, "timer2"); |
57cc4f7d | 481 | sp804_clockevents_init(TIMER1_VA_BASE, IRQ_TIMERINT1, "timer1"); |
1da177e4 LT |
482 | } |
483 | ||
4672cddf LW |
484 | #define INTEGRATOR_CP_MMC_IRQS { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 } |
485 | #define INTEGRATOR_CP_AACI_IRQS { IRQ_CP_AACIINT } | |
486 | ||
487 | static AMBA_APB_DEVICE(mmc, "mmci", 0, INTEGRATOR_CP_MMC_BASE, | |
488 | INTEGRATOR_CP_MMC_IRQS, &mmc_data); | |
489 | ||
490 | static AMBA_APB_DEVICE(aaci, "aaci", 0, INTEGRATOR_CP_AACI_BASE, | |
491 | INTEGRATOR_CP_AACI_IRQS, NULL); | |
492 | ||
493 | static AMBA_AHB_DEVICE(clcd, "clcd", 0, INTCP_PA_CLCD_BASE, | |
494 | { IRQ_CP_CLCDCINT }, &clcd_data); | |
495 | ||
496 | static struct amba_device *amba_devs[] __initdata = { | |
497 | &mmc_device, | |
498 | &aaci_device, | |
499 | &clcd_device, | |
500 | }; | |
501 | ||
502 | static void __init intcp_init(void) | |
503 | { | |
504 | int i; | |
505 | ||
506 | platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs)); | |
507 | ||
508 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { | |
509 | struct amba_device *d = amba_devs[i]; | |
510 | amba_device_register(d, &iomem_resource); | |
511 | } | |
512 | integrator_init(true); | |
513 | } | |
514 | ||
1da177e4 | 515 | MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP") |
e9dea0c6 | 516 | /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ |
c5e587a2 | 517 | .atag_offset = 0x100, |
98c672cf | 518 | .reserve = integrator_reserve, |
e6fae083 | 519 | .map_io = intcp_map_io_atag, |
c735c987 | 520 | .init_early = intcp_init_early, |
e9dea0c6 | 521 | .init_irq = intcp_init_irq, |
3108e6ab | 522 | .handle_irq = fpga_handle_irq, |
6bb27d73 | 523 | .init_time = cp_timer_init, |
e9dea0c6 | 524 | .init_machine = intcp_init, |
6338b66f | 525 | .restart = integrator_restart, |
1da177e4 | 526 | MACHINE_END |
4980f9bc LW |
527 | |
528 | #endif |