[deliverable/linux.git] / arch / arm / mach-integrator / integrator_cp.c

/*
 *  linux/arch/arm/mach-integrator/integrator_cp.c
 *
 *  Copyright (C) 2003 Deep Blue Solutions Ltd
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License.
 */
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/string.h>
#include <linux/device.h>
#include <linux/amba/bus.h>
#include <linux/amba/kmi.h>
#include <linux/amba/clcd.h>
#include <linux/platform_data/video-clcd-versatile.h>
#include <linux/amba/mmci.h>
#include <linux/io.h>
#include <linux/irqchip/versatile-fpga.h>
#include <linux/gfp.h>
#include <linux/mtd/physmap.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/sys_soc.h>
#include <linux/sched_clock.h>

#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>

#include "hardware.h"
#include "cm.h"
#include "common.h"

/* Base address to the CP controller */
static void __iomem *intcp_con_base;

#define INTCP_PA_FLASH_BASE		0x24000000

#define INTCP_PA_CLCD_BASE		0xc0000000

#define INTCP_FLASHPROG			0x04
#define CINTEGRATOR_FLASHPROG_FLVPPEN	(1 << 0)
#define CINTEGRATOR_FLASHPROG_FLWREN	(1 << 1)

/*
 * Logical      Physical
 * f1000000	10000000	Core module registers
 * f1300000	13000000	Counter/Timer
 * f1400000	14000000	Interrupt controller
 * f1600000	16000000	UART 0
 * f1700000	17000000	UART 1
 * f1a00000	1a000000	Debug LEDs
 * fc900000	c9000000	GPIO
 * fca00000	ca000000	SIC
 */

static struct map_desc intcp_io_desc[] __initdata __maybe_unused = {
	{
		.virtual	= IO_ADDRESS(INTEGRATOR_HDR_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_HDR_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_CT_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_CT_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_IC_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_IC_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_UART0_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_UART0_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_DBG_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_DBG_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_CP_GPIO_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_CP_GPIO_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_CP_SIC_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_CP_SIC_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}
};

static void __init intcp_map_io(void)
{
	iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
}

/*
 * Flash handling.
 */
static int intcp_flash_init(struct platform_device *dev)
{
	u32 val;

	val = readl(intcp_con_base + INTCP_FLASHPROG);
	val |= CINTEGRATOR_FLASHPROG_FLWREN;
	writel(val, intcp_con_base + INTCP_FLASHPROG);

	return 0;
}

static void intcp_flash_exit(struct platform_device *dev)
{
	u32 val;

	val = readl(intcp_con_base + INTCP_FLASHPROG);
	val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN);
	writel(val, intcp_con_base + INTCP_FLASHPROG);
}

static void intcp_flash_set_vpp(struct platform_device *pdev, int on)
{
	u32 val;

	val = readl(intcp_con_base + INTCP_FLASHPROG);
	if (on)
		val |= CINTEGRATOR_FLASHPROG_FLVPPEN;
	else
		val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
	writel(val, intcp_con_base + INTCP_FLASHPROG);
}

static struct physmap_flash_data intcp_flash_data = {
	.width		= 4,
	.init		= intcp_flash_init,
	.exit		= intcp_flash_exit,
	.set_vpp	= intcp_flash_set_vpp,
};

/*
 * It seems that the card insertion interrupt remains active after
 * we've acknowledged it.  We therefore ignore the interrupt, and
 * rely on reading it from the SIC.  This also means that we must
 * clear the latched interrupt.
 */
static unsigned int mmc_status(struct device *dev)
{
	unsigned int status = readl(__io_address(0xca000000 + 4));
	writel(8, intcp_con_base + 8);

	return status & 8;
}

static struct mmci_platform_data mmc_data = {
	.ocr_mask	= MMC_VDD_32_33|MMC_VDD_33_34,
	.status		= mmc_status,
	.gpio_wp	= -1,
	.gpio_cd	= -1,
};

/*
 * CLCD support
 */
/*
 * Ensure VGA is selected.
 */
static void cp_clcd_enable(struct clcd_fb *fb)
{
	struct fb_var_screeninfo *var = &fb->fb.var;
	u32 val = CM_CTRL_STATIC1 | CM_CTRL_STATIC2
			| CM_CTRL_LCDEN0 | CM_CTRL_LCDEN1;

	if (var->bits_per_pixel <= 8 ||
	    (var->bits_per_pixel == 16 && var->green.length == 5))
		/* Pseudocolor, RGB555, BGR555 */
		val |= CM_CTRL_LCDMUXSEL_VGA555_TFT555;
	else if (fb->fb.var.bits_per_pixel <= 16)
		/* truecolor RGB565 */
		val |= CM_CTRL_LCDMUXSEL_VGA565_TFT555;
	else
		val = 0; /* no idea for this, don't trust the docs */

	cm_control(CM_CTRL_LCDMUXSEL_MASK|
		   CM_CTRL_LCDEN0|
		   CM_CTRL_LCDEN1|
		   CM_CTRL_STATIC1|
		   CM_CTRL_STATIC2|
		   CM_CTRL_STATIC|
		   CM_CTRL_n24BITEN, val);
}

static int cp_clcd_setup(struct clcd_fb *fb)
{
	fb->panel = versatile_clcd_get_panel("VGA");
	if (!fb->panel)
		return -EINVAL;

	return versatile_clcd_setup_dma(fb, SZ_1M);
}

static struct clcd_board clcd_data = {
	.name		= "Integrator/CP",
	.caps		= CLCD_CAP_5551 | CLCD_CAP_RGB565 | CLCD_CAP_888,
	.check		= clcdfb_check,
	.decode		= clcdfb_decode,
	.enable		= cp_clcd_enable,
	.setup		= cp_clcd_setup,
	.mmap		= versatile_clcd_mmap_dma,
	.remove		= versatile_clcd_remove_dma,
};

#define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28)

static u64 notrace intcp_read_sched_clock(void)
{
	return readl(REFCOUNTER);
}

static void __init intcp_init_early(void)
{
	sched_clock_register(intcp_read_sched_clock, 32, 24000000);
}

static const struct of_device_id fpga_irq_of_match[] __initconst = {
	{ .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
	{ /* Sentinel */ }
};

static void __init intcp_init_irq_of(void)
{
	cm_init();
	of_irq_init(fpga_irq_of_match);
}

/*
 * For the Device Tree, add in the UART, MMC and CLCD specifics as AUXDATA
 * and enforce the bus names since these are used for clock lookups.
 */
static struct of_dev_auxdata intcp_auxdata_lookup[] __initdata = {
	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
		"rtc", NULL),
	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
		"uart0", NULL),
	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
		"uart1", NULL),
	OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
		"kmi0", NULL),
	OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
		"kmi1", NULL),
	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_MMC_BASE,
		"mmci", &mmc_data),
	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_AACI_BASE,
		"aaci", &mmc_data),
	OF_DEV_AUXDATA("arm,primecell", INTCP_PA_CLCD_BASE,
		"clcd", &clcd_data),
	OF_DEV_AUXDATA("cfi-flash", INTCP_PA_FLASH_BASE,
		"physmap-flash", &intcp_flash_data),
	{ /* sentinel */ },
};

static const struct of_device_id intcp_syscon_match[] = {
	{ .compatible = "arm,integrator-cp-syscon"},
	{ },
};

static void __init intcp_init_of(void)
{
	struct device_node *root;
	struct device_node *cpcon;
	struct device *parent;
	struct soc_device *soc_dev;
	struct soc_device_attribute *soc_dev_attr;
	u32 intcp_sc_id;
	int err;

	/* Here we create an SoC device for the root node */
	root = of_find_node_by_path("/");
	if (!root)
		return;

	cpcon = of_find_matching_node(root, intcp_syscon_match);
	if (!cpcon)
		return;

	intcp_con_base = of_iomap(cpcon, 0);
	if (!intcp_con_base)
		return;

	intcp_sc_id = readl(intcp_con_base);

	soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
	if (!soc_dev_attr)
		return;

	err = of_property_read_string(root, "compatible",
				      &soc_dev_attr->soc_id);
	if (err)
		return;
	err = of_property_read_string(root, "model", &soc_dev_attr->machine);
	if (err)
		return;
	soc_dev_attr->family = "Integrator";
	soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c",
					   'A' + (intcp_sc_id & 0x0f));

	soc_dev = soc_device_register(soc_dev_attr);
	if (IS_ERR(soc_dev)) {
		kfree(soc_dev_attr->revision);
		kfree(soc_dev_attr);
		return;
	}

	parent = soc_device_to_device(soc_dev);
	integrator_init_sysfs(parent, intcp_sc_id);
	of_platform_populate(root, of_default_bus_match_table,
			intcp_auxdata_lookup, parent);
}

static const char * intcp_dt_board_compat[] = {
	"arm,integrator-cp",
	NULL,
};

DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
	.reserve	= integrator_reserve,
	.map_io		= intcp_map_io,
	.init_early	= intcp_init_early,
	.init_irq	= intcp_init_irq_of,
	.handle_irq	= fpga_handle_irq,
	.init_machine	= intcp_init_of,
	.restart	= integrator_restart,
	.dt_compat      = intcp_dt_board_compat,
MACHINE_END
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-integrator/integrator_cp.c
	3	*
	4	* Copyright (C) 2003 Deep Blue Solutions Ltd
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License.
	9	*/
	10	#include <linux/types.h>
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
	13	#include <linux/list.h>
d052d1be	14	#include <linux/platform_device.h>
1da177e4	15	#include <linux/dma-mapping.h>
1da177e4	16	#include <linux/string.h>
edbaa603	17	#include <linux/device.h>
a62c80e5 RK	18	#include <linux/amba/bus.h>
	19	#include <linux/amba/kmi.h>
	20	#include <linux/amba/clcd.h>
11c32d7b	21	#include <linux/platform_data/video-clcd-versatile.h>
6ef297f8	22	#include <linux/amba/mmci.h>
fced80c7	23	#include <linux/io.h>
2389d501	24	#include <linux/irqchip/versatile-fpga.h>
5a0e3ad6	25	#include <linux/gfp.h>
046dfa0a	26	#include <linux/mtd/physmap.h>
4980f9bc LW	27	#include <linux/of_irq.h>
4980f9bc LW	28	#include <linux/of_address.h>
4672cddf	29	#include <linux/of_platform.h>
64100a03	30	#include <linux/sys_soc.h>
a79528e9	31	#include <linux/sched_clock.h>
1da177e4	32
1da177e4 LT	33	#include <asm/setup.h>
1da177e4 LT	34	#include <asm/mach-types.h>
1da177e4	35	#include <asm/mach/arch.h>
1da177e4	36	#include <asm/mach/irq.h>
1da177e4 LT	37	#include <asm/mach/map.h>
	38	#include <asm/mach/time.h>
	39
1b1ef755	40	#include "hardware.h"
bb4dbefe	41	#include "cm.h"
98c672cf RK	42	#include "common.h"
98c672cf RK	43
e6fae083 LW	44	/* Base address to the CP controller */
	45	static void __iomem *intcp_con_base;
	46
1da177e4	47	#define INTCP_PA_FLASH_BASE 0x24000000
1da177e4 LT	48
	49	#define INTCP_PA_CLCD_BASE 0xc0000000
	50
1da177e4 LT	51	#define INTCP_FLASHPROG 0x04
	52	#define CINTEGRATOR_FLASHPROG_FLVPPEN (1 << 0)
	53	#define CINTEGRATOR_FLASHPROG_FLWREN (1 << 1)
	54
	55	/*
	56	* Logical Physical
608914b3	57	* f1000000 10000000 Core module registers
1da177e4 LT	58	* f1300000 13000000 Counter/Timer
	59	* f1400000 14000000 Interrupt controller
	60	* f1600000 16000000 UART 0
	61	* f1700000 17000000 UART 1
	62	* f1a00000 1a000000 Debug LEDs
da7ba956 RK	63	* fc900000 c9000000 GPIO
da7ba956 RK	64	* fca00000 ca000000 SIC
1da177e4 LT	65	*/
1da177e4 LT	66
060fd1be	67	static struct map_desc intcp_io_desc[] __initdata __maybe_unused = {
c8d27298	68	{
608914b3 LW	69	.virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
	70	.pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE),
	71	.length = SZ_4K,
	72	.type = MT_DEVICE
	73	}, {
c8d27298 DS	74	.virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
	75	.pfn = __phys_to_pfn(INTEGRATOR_CT_BASE),
	76	.length = SZ_4K,
	77	.type = MT_DEVICE
	78	}, {
	79	.virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
	80	.pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
	81	.length = SZ_4K,
	82	.type = MT_DEVICE
	83	}, {
	84	.virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
	85	.pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
	86	.length = SZ_4K,
	87	.type = MT_DEVICE
c8d27298 DS	88	}, {
	89	.virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
	90	.pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
	91	.length = SZ_4K,
	92	.type = MT_DEVICE
	93	}, {
da7ba956 RK	94	.virtual = IO_ADDRESS(INTEGRATOR_CP_GPIO_BASE),
da7ba956 RK	95	.pfn = __phys_to_pfn(INTEGRATOR_CP_GPIO_BASE),
c8d27298 DS	96	.length = SZ_4K,
	97	.type = MT_DEVICE
	98	}, {
da7ba956 RK	99	.virtual = IO_ADDRESS(INTEGRATOR_CP_SIC_BASE),
da7ba956 RK	100	.pfn = __phys_to_pfn(INTEGRATOR_CP_SIC_BASE),
c8d27298 DS	101	.length = SZ_4K,
c8d27298 DS	102	.type = MT_DEVICE
c8d27298	103	}
1da177e4 LT	104	};
	105
	106	static void __init intcp_map_io(void)
	107	{
	108	iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
	109	}
	110
1da177e4 LT	111	/*
	112	* Flash handling.
	113	*/
046dfa0a	114	static int intcp_flash_init(struct platform_device *dev)
1da177e4 LT	115	{
	116	u32 val;
	117
e6fae083	118	val = readl(intcp_con_base + INTCP_FLASHPROG);
1da177e4	119	val \|= CINTEGRATOR_FLASHPROG_FLWREN;
e6fae083	120	writel(val, intcp_con_base + INTCP_FLASHPROG);
1da177e4 LT	121
	122	return 0;
	123	}
	124
046dfa0a	125	static void intcp_flash_exit(struct platform_device *dev)
1da177e4 LT	126	{
	127	u32 val;
	128
e6fae083	129	val = readl(intcp_con_base + INTCP_FLASHPROG);
1da177e4	130	val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN\|CINTEGRATOR_FLASHPROG_FLWREN);
e6fae083	131	writel(val, intcp_con_base + INTCP_FLASHPROG);
1da177e4 LT	132	}
1da177e4 LT	133
667f390b	134	static void intcp_flash_set_vpp(struct platform_device *pdev, int on)
1da177e4 LT	135	{
	136	u32 val;
	137
e6fae083	138	val = readl(intcp_con_base + INTCP_FLASHPROG);
1da177e4 LT	139	if (on)
	140	val \|= CINTEGRATOR_FLASHPROG_FLVPPEN;
	141	else
	142	val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
e6fae083	143	writel(val, intcp_con_base + INTCP_FLASHPROG);
1da177e4 LT	144	}
1da177e4 LT	145
046dfa0a	146	static struct physmap_flash_data intcp_flash_data = {
1da177e4 LT	147	.width = 4,
	148	.init = intcp_flash_init,
	149	.exit = intcp_flash_exit,
	150	.set_vpp = intcp_flash_set_vpp,
	151	};
	152
1da177e4 LT	153	/*
	154	* It seems that the card insertion interrupt remains active after
	155	* we've acknowledged it. We therefore ignore the interrupt, and
	156	* rely on reading it from the SIC. This also means that we must
	157	* clear the latched interrupt.
	158	*/
	159	static unsigned int mmc_status(struct device *dev)
	160	{
b7a3f8db	161	unsigned int status = readl(__io_address(0xca000000 + 4));
e6fae083	162	writel(8, intcp_con_base + 8);
1da177e4 LT	163
	164	return status & 8;
	165	}
	166
6ef297f8	167	static struct mmci_platform_data mmc_data = {
1da177e4 LT	168	.ocr_mask = MMC_VDD_32_33\|MMC_VDD_33_34,
1da177e4 LT	169	.status = mmc_status,
7fb2bbf4 RK	170	.gpio_wp = -1,
7fb2bbf4 RK	171	.gpio_cd = -1,
1da177e4 LT	172	};
1da177e4 LT	173
1da177e4 LT	174	/*
	175	* CLCD support
	176	*/
1da177e4 LT	177	/*
	178	* Ensure VGA is selected.
	179	*/
	180	static void cp_clcd_enable(struct clcd_fb *fb)
	181	{
e6b9c1f8	182	struct fb_var_screeninfo *var = &fb->fb.var;
30aeadd4 JA	183	u32 val = CM_CTRL_STATIC1 \| CM_CTRL_STATIC2
30aeadd4 JA	184	\| CM_CTRL_LCDEN0 \| CM_CTRL_LCDEN1;
4774e226	185
e6b9c1f8 RK	186	if (var->bits_per_pixel <= 8 \|\|
	187	(var->bits_per_pixel == 16 && var->green.length == 5))
	188	/* Pseudocolor, RGB555, BGR555 */
	189	val \|= CM_CTRL_LCDMUXSEL_VGA555_TFT555;
4774e226	190	else if (fb->fb.var.bits_per_pixel <= 16)
e6b9c1f8 RK	191	/* truecolor RGB565 */
e6b9c1f8 RK	192	val \|= CM_CTRL_LCDMUXSEL_VGA565_TFT555;
4774e226 RK	193	else
	194	val = 0; /* no idea for this, don't trust the docs */
	195
	196	cm_control(CM_CTRL_LCDMUXSEL_MASK\|
	197	CM_CTRL_LCDEN0\|
	198	CM_CTRL_LCDEN1\|
	199	CM_CTRL_STATIC1\|
	200	CM_CTRL_STATIC2\|
	201	CM_CTRL_STATIC\|
	202	CM_CTRL_n24BITEN, val);
1da177e4 LT	203	}
1da177e4 LT	204
1da177e4 LT	205	static int cp_clcd_setup(struct clcd_fb *fb)
1da177e4 LT	206	{
9dfec4fe RK	207	fb->panel = versatile_clcd_get_panel("VGA");
	208	if (!fb->panel)
	209	return -EINVAL;
1da177e4	210
9dfec4fe	211	return versatile_clcd_setup_dma(fb, SZ_1M);
1da177e4 LT	212	}
	213
	214	static struct clcd_board clcd_data = {
	215	.name = "Integrator/CP",
9dfec4fe	216	.caps = CLCD_CAP_5551 \| CLCD_CAP_RGB565 \| CLCD_CAP_888,
1da177e4 LT	217	.check = clcdfb_check,
	218	.decode = clcdfb_decode,
	219	.enable = cp_clcd_enable,
	220	.setup = cp_clcd_setup,
9dfec4fe RK	221	.mmap = versatile_clcd_mmap_dma,
9dfec4fe RK	222	.remove = versatile_clcd_remove_dma,
1da177e4 LT	223	};
1da177e4 LT	224
d77e270c RK	225	#define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28)
d77e270c RK	226
a79528e9 LW	227	static u64 notrace intcp_read_sched_clock(void)
	228	{
	229	return readl(REFCOUNTER);
	230	}
	231
c735c987 RK	232	static void __init intcp_init_early(void)
c735c987 RK	233	{
a79528e9	234	sched_clock_register(intcp_read_sched_clock, 32, 24000000);
c735c987 RK	235	}
c735c987 RK	236
4980f9bc LW	237	static const struct of_device_id fpga_irq_of_match[] __initconst = {
	238	{ .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
	239	{ /* Sentinel */ }
	240	};
	241
	242	static void __init intcp_init_irq_of(void)
1da177e4	243	{
bb4dbefe	244	cm_init();
4980f9bc	245	of_irq_init(fpga_irq_of_match);
4980f9bc	246	}
1da177e4	247
4672cddf LW	248	/*
	249	* For the Device Tree, add in the UART, MMC and CLCD specifics as AUXDATA
	250	* and enforce the bus names since these are used for clock lookups.
	251	*/
	252	static struct of_dev_auxdata intcp_auxdata_lookup[] __initdata = {
	253	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
	254	"rtc", NULL),
	255	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
379df279	256	"uart0", NULL),
4672cddf	257	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
379df279	258	"uart1", NULL),
4672cddf LW	259	OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
	260	"kmi0", NULL),
	261	OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
	262	"kmi1", NULL),
	263	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_MMC_BASE,
	264	"mmci", &mmc_data),
	265	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_AACI_BASE,
	266	"aaci", &mmc_data),
	267	OF_DEV_AUXDATA("arm,primecell", INTCP_PA_CLCD_BASE,
	268	"clcd", &clcd_data),
73efd530 LW	269	OF_DEV_AUXDATA("cfi-flash", INTCP_PA_FLASH_BASE,
73efd530 LW	270	"physmap-flash", &intcp_flash_data),
4672cddf LW	271	{ /* sentinel */ },
	272	};
	273
df36680f LW	274	static const struct of_device_id intcp_syscon_match[] = {
	275	{ .compatible = "arm,integrator-cp-syscon"},
	276	{ },
	277	};
	278
4672cddf LW	279	static void __init intcp_init_of(void)
4672cddf LW	280	{
64100a03 LW	281	struct device_node *root;
	282	struct device_node *cpcon;
	283	struct device *parent;
	284	struct soc_device *soc_dev;
	285	struct soc_device_attribute *soc_dev_attr;
	286	u32 intcp_sc_id;
	287	int err;
	288
	289	/* Here we create an SoC device for the root node */
	290	root = of_find_node_by_path("/");
	291	if (!root)
	292	return;
df36680f LW	293
df36680f LW	294	cpcon = of_find_matching_node(root, intcp_syscon_match);
64100a03 LW	295	if (!cpcon)
	296	return;
	297
	298	intcp_con_base = of_iomap(cpcon, 0);
	299	if (!intcp_con_base)
	300	return;
	301
	302	intcp_sc_id = readl(intcp_con_base);
	303
	304	soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
	305	if (!soc_dev_attr)
	306	return;
	307
	308	err = of_property_read_string(root, "compatible",
	309	&soc_dev_attr->soc_id);
	310	if (err)
	311	return;
	312	err = of_property_read_string(root, "model", &soc_dev_attr->machine);
	313	if (err)
	314	return;
	315	soc_dev_attr->family = "Integrator";
	316	soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c",
	317	'A' + (intcp_sc_id & 0x0f));
	318
	319	soc_dev = soc_device_register(soc_dev_attr);
b269b170	320	if (IS_ERR(soc_dev)) {
64100a03 LW	321	kfree(soc_dev_attr->revision);
	322	kfree(soc_dev_attr);
	323	return;
	324	}
	325
	326	parent = soc_device_to_device(soc_dev);
b269b170	327	integrator_init_sysfs(parent, intcp_sc_id);
64100a03 LW	328	of_platform_populate(root, of_default_bus_match_table,
64100a03 LW	329	intcp_auxdata_lookup, parent);
4672cddf LW	330	}
4672cddf LW	331
4980f9bc LW	332	static const char * intcp_dt_board_compat[] = {
	333	"arm,integrator-cp",
	334	NULL,
	335	};
1da177e4	336
4980f9bc LW	337	DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
	338	.reserve = integrator_reserve,
	339	.map_io = intcp_map_io,
4980f9bc LW	340	.init_early = intcp_init_early,
	341	.init_irq = intcp_init_irq_of,
	342	.handle_irq = fpga_handle_irq,
4672cddf	343	.init_machine = intcp_init_of,
4980f9bc LW	344	.restart = integrator_restart,
	345	.dt_compat = intcp_dt_board_compat,
	346	MACHINE_END