[deliverable/linux.git] / arch / arm / mach-integrator / integrator_cp.c

/*
 *  linux/arch/arm/mach-integrator/integrator_cp.c
 *
 *  Copyright (C) 2003 Deep Blue Solutions Ltd
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License.
 */
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/string.h>
#include <linux/device.h>
#include <linux/amba/bus.h>
#include <linux/amba/kmi.h>
#include <linux/amba/clcd.h>
#include <linux/amba/mmci.h>
#include <linux/io.h>
#include <linux/gfp.h>
#include <linux/mtd/physmap.h>
#include <linux/platform_data/clk-integrator.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>

#include <mach/hardware.h>
#include <mach/platform.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/hardware/arm_timer.h>
#include <asm/hardware/icst.h>

#include <mach/cm.h>
#include <mach/lm.h>
#include <mach/irqs.h>

#include <asm/mach/arch.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>

#include <asm/hardware/timer-sp.h>

#include <plat/clcd.h>
#include <plat/fpga-irq.h>
#include <plat/sched_clock.h>

#include "common.h"

#define INTCP_PA_FLASH_BASE		0x24000000

#define INTCP_PA_CLCD_BASE		0xc0000000

#define INTCP_VA_CTRL_BASE		__io_address(INTEGRATOR_CP_CTL_BASE)
#define INTCP_FLASHPROG			0x04
#define CINTEGRATOR_FLASHPROG_FLVPPEN	(1 << 0)
#define CINTEGRATOR_FLASHPROG_FLWREN	(1 << 1)

/*
 * Logical      Physical
 * f1000000	10000000	Core module registers
 * f1100000	11000000	System controller registers
 * f1200000	12000000	EBI registers
 * f1300000	13000000	Counter/Timer
 * f1400000	14000000	Interrupt controller
 * f1600000	16000000	UART 0
 * f1700000	17000000	UART 1
 * f1a00000	1a000000	Debug LEDs
 * fc900000	c9000000	GPIO
 * fca00000	ca000000	SIC
 * fcb00000	cb000000	CP system control
 */

static struct map_desc intcp_io_desc[] __initdata = {
	{
		.virtual	= IO_ADDRESS(INTEGRATOR_HDR_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_HDR_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_SC_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_SC_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_EBI_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_EBI_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_CT_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_CT_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_IC_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_IC_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_UART0_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_UART0_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_UART1_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_UART1_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_DBG_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_DBG_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_CP_GPIO_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_CP_GPIO_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_CP_SIC_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_CP_SIC_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_CP_CTL_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_CP_CTL_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}
};

static void __init intcp_map_io(void)
{
	iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
}

/*
 * Flash handling.
 */
static int intcp_flash_init(struct platform_device *dev)
{
	u32 val;

	val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
	val |= CINTEGRATOR_FLASHPROG_FLWREN;
	writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);

	return 0;
}

static void intcp_flash_exit(struct platform_device *dev)
{
	u32 val;

	val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
	val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN);
	writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
}

static void intcp_flash_set_vpp(struct platform_device *pdev, int on)
{
	u32 val;

	val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
	if (on)
		val |= CINTEGRATOR_FLASHPROG_FLVPPEN;
	else
		val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
	writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
}

static struct physmap_flash_data intcp_flash_data = {
	.width		= 4,
	.init		= intcp_flash_init,
	.exit		= intcp_flash_exit,
	.set_vpp	= intcp_flash_set_vpp,
};

/*
 * It seems that the card insertion interrupt remains active after
 * we've acknowledged it.  We therefore ignore the interrupt, and
 * rely on reading it from the SIC.  This also means that we must
 * clear the latched interrupt.
 */
static unsigned int mmc_status(struct device *dev)
{
	unsigned int status = readl(__io_address(0xca000000 + 4));
	writel(8, __io_address(INTEGRATOR_CP_CTL_BASE + 8));

	return status & 8;
}

static struct mmci_platform_data mmc_data = {
	.ocr_mask	= MMC_VDD_32_33|MMC_VDD_33_34,
	.status		= mmc_status,
	.gpio_wp	= -1,
	.gpio_cd	= -1,
};

/*
 * CLCD support
 */
/*
 * Ensure VGA is selected.
 */
static void cp_clcd_enable(struct clcd_fb *fb)
{
	struct fb_var_screeninfo *var = &fb->fb.var;
	u32 val = CM_CTRL_STATIC1 | CM_CTRL_STATIC2;

	if (var->bits_per_pixel <= 8 ||
	    (var->bits_per_pixel == 16 && var->green.length == 5))
		/* Pseudocolor, RGB555, BGR555 */
		val |= CM_CTRL_LCDMUXSEL_VGA555_TFT555;
	else if (fb->fb.var.bits_per_pixel <= 16)
		/* truecolor RGB565 */
		val |= CM_CTRL_LCDMUXSEL_VGA565_TFT555;
	else
		val = 0; /* no idea for this, don't trust the docs */

	cm_control(CM_CTRL_LCDMUXSEL_MASK|
		   CM_CTRL_LCDEN0|
		   CM_CTRL_LCDEN1|
		   CM_CTRL_STATIC1|
		   CM_CTRL_STATIC2|
		   CM_CTRL_STATIC|
		   CM_CTRL_n24BITEN, val);
}

static int cp_clcd_setup(struct clcd_fb *fb)
{
	fb->panel = versatile_clcd_get_panel("VGA");
	if (!fb->panel)
		return -EINVAL;

	return versatile_clcd_setup_dma(fb, SZ_1M);
}

static struct clcd_board clcd_data = {
	.name		= "Integrator/CP",
	.caps		= CLCD_CAP_5551 | CLCD_CAP_RGB565 | CLCD_CAP_888,
	.check		= clcdfb_check,
	.decode		= clcdfb_decode,
	.enable		= cp_clcd_enable,
	.setup		= cp_clcd_setup,
	.mmap		= versatile_clcd_mmap_dma,
	.remove		= versatile_clcd_remove_dma,
};

#define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28)

static void __init intcp_init_early(void)
{
#ifdef CONFIG_PLAT_VERSATILE_SCHED_CLOCK
	versatile_sched_clock_init(REFCOUNTER, 24000000);
#endif
}

#ifdef CONFIG_OF

static void __init intcp_timer_init_of(void)
{
	struct device_node *node;
	const char *path;
	void __iomem *base;
	int err;
	int irq;

	err = of_property_read_string(of_aliases,
				"arm,timer-primary", &path);
	if (WARN_ON(err))
		return;
	node = of_find_node_by_path(path);
	base = of_iomap(node, 0);
	if (WARN_ON(!base))
		return;
	writel(0, base + TIMER_CTRL);
	sp804_clocksource_init(base, node->name);

	err = of_property_read_string(of_aliases,
				"arm,timer-secondary", &path);
	if (WARN_ON(err))
		return;
	node = of_find_node_by_path(path);
	base = of_iomap(node, 0);
	if (WARN_ON(!base))
		return;
	irq = irq_of_parse_and_map(node, 0);
	writel(0, base + TIMER_CTRL);
	sp804_clockevents_init(base, irq, node->name);
}

static struct sys_timer cp_of_timer = {
	.init		= intcp_timer_init_of,
};

static const struct of_device_id fpga_irq_of_match[] __initconst = {
	{ .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
	{ /* Sentinel */ }
};

static void __init intcp_init_irq_of(void)
{
	of_irq_init(fpga_irq_of_match);
	integrator_clk_init(true);
}

/*
 * For the Device Tree, add in the UART, MMC and CLCD specifics as AUXDATA
 * and enforce the bus names since these are used for clock lookups.
 */
static struct of_dev_auxdata intcp_auxdata_lookup[] __initdata = {
	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
		"rtc", NULL),
	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
		"uart0", &integrator_uart_data),
	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
		"uart1", &integrator_uart_data),
	OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
		"kmi0", NULL),
	OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
		"kmi1", NULL),
	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_MMC_BASE,
		"mmci", &mmc_data),
	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_AACI_BASE,
		"aaci", &mmc_data),
	OF_DEV_AUXDATA("arm,primecell", INTCP_PA_CLCD_BASE,
		"clcd", &clcd_data),
	OF_DEV_AUXDATA("cfi-flash", INTCP_PA_FLASH_BASE,
		"physmap-flash", &intcp_flash_data),
	{ /* sentinel */ },
};

static void __init intcp_init_of(void)
{
	of_platform_populate(NULL, of_default_bus_match_table,
			intcp_auxdata_lookup, NULL);
}

static const char * intcp_dt_board_compat[] = {
	"arm,integrator-cp",
	NULL,
};

DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
	.reserve	= integrator_reserve,
	.map_io		= intcp_map_io,
	.nr_irqs	= NR_IRQS_INTEGRATOR_CP,
	.init_early	= intcp_init_early,
	.init_irq	= intcp_init_irq_of,
	.handle_irq	= fpga_handle_irq,
	.timer		= &cp_of_timer,
	.init_machine	= intcp_init_of,
	.restart	= integrator_restart,
	.dt_compat      = intcp_dt_board_compat,
MACHINE_END

#endif

#ifdef CONFIG_ATAGS

/*
 * This is where non-devicetree initialization code is collected and stashed
 * for eventual deletion.
 */

#define INTCP_FLASH_SIZE		SZ_32M

static struct resource intcp_flash_resource = {
	.start		= INTCP_PA_FLASH_BASE,
	.end		= INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1,
	.flags		= IORESOURCE_MEM,
};

static struct platform_device intcp_flash_device = {
	.name		= "physmap-flash",
	.id		= 0,
	.dev		= {
		.platform_data	= &intcp_flash_data,
	},
	.num_resources	= 1,
	.resource	= &intcp_flash_resource,
};

#define INTCP_ETH_SIZE			0x10

static struct resource smc91x_resources[] = {
	[0] = {
		.start	= INTEGRATOR_CP_ETH_BASE,
		.end	= INTEGRATOR_CP_ETH_BASE + INTCP_ETH_SIZE - 1,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= IRQ_CP_ETHINT,
		.end	= IRQ_CP_ETHINT,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device smc91x_device = {
	.name		= "smc91x",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(smc91x_resources),
	.resource	= smc91x_resources,
};

static struct platform_device *intcp_devs[] __initdata = {
	&intcp_flash_device,
	&smc91x_device,
};

#define INTCP_VA_CIC_BASE		__io_address(INTEGRATOR_HDR_BASE + 0x40)
#define INTCP_VA_PIC_BASE		__io_address(INTEGRATOR_IC_BASE)
#define INTCP_VA_SIC_BASE		__io_address(INTEGRATOR_CP_SIC_BASE)

static void __init intcp_init_irq(void)
{
	u32 pic_mask, cic_mask, sic_mask;

	/* These masks are for the HW IRQ registers */
	pic_mask = ~((~0u) << (11 - IRQ_PIC_START));
	pic_mask |= (~((~0u) << (29 - 22))) << 22;
	cic_mask = ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START));
	sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START));

	/*
	 * Disable all interrupt sources
	 */
	writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
	writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
	writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
	writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
	writel(sic_mask, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
	writel(sic_mask, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);

	fpga_irq_init(INTCP_VA_PIC_BASE, "PIC", IRQ_PIC_START,
		      -1, pic_mask, NULL);

	fpga_irq_init(INTCP_VA_CIC_BASE, "CIC", IRQ_CIC_START,
		      -1, cic_mask, NULL);

	fpga_irq_init(INTCP_VA_SIC_BASE, "SIC", IRQ_SIC_START,
		      IRQ_CP_CPPLDINT, sic_mask, NULL);

	integrator_clk_init(true);
}

#define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
#define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
#define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)

static void __init intcp_timer_init(void)
{
	writel(0, TIMER0_VA_BASE + TIMER_CTRL);
	writel(0, TIMER1_VA_BASE + TIMER_CTRL);
	writel(0, TIMER2_VA_BASE + TIMER_CTRL);

	sp804_clocksource_init(TIMER2_VA_BASE, "timer2");
	sp804_clockevents_init(TIMER1_VA_BASE, IRQ_TIMERINT1, "timer1");
}

static struct sys_timer cp_timer = {
	.init		= intcp_timer_init,
};

#define INTEGRATOR_CP_MMC_IRQS	{ IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 }
#define INTEGRATOR_CP_AACI_IRQS	{ IRQ_CP_AACIINT }

static AMBA_APB_DEVICE(mmc, "mmci", 0, INTEGRATOR_CP_MMC_BASE,
	INTEGRATOR_CP_MMC_IRQS, &mmc_data);

static AMBA_APB_DEVICE(aaci, "aaci", 0, INTEGRATOR_CP_AACI_BASE,
	INTEGRATOR_CP_AACI_IRQS, NULL);

static AMBA_AHB_DEVICE(clcd, "clcd", 0, INTCP_PA_CLCD_BASE,
	{ IRQ_CP_CLCDCINT }, &clcd_data);

static struct amba_device *amba_devs[] __initdata = {
	&mmc_device,
	&aaci_device,
	&clcd_device,
};

static void __init intcp_init(void)
{
	int i;

	platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));

	for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
		struct amba_device *d = amba_devs[i];
		amba_device_register(d, &iomem_resource);
	}
	integrator_init(true);
}

MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
	/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
	.atag_offset	= 0x100,
	.reserve	= integrator_reserve,
	.map_io		= intcp_map_io,
	.nr_irqs	= NR_IRQS_INTEGRATOR_CP,
	.init_early	= intcp_init_early,
	.init_irq	= intcp_init_irq,
	.handle_irq	= fpga_handle_irq,
	.timer		= &cp_timer,
	.init_machine	= intcp_init,
	.restart	= integrator_restart,
MACHINE_END

#endif
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-integrator/integrator_cp.c
	3	*
	4	* Copyright (C) 2003 Deep Blue Solutions Ltd
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License.
	9	*/
	10	#include <linux/types.h>
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
	13	#include <linux/list.h>
d052d1be	14	#include <linux/platform_device.h>
1da177e4	15	#include <linux/dma-mapping.h>
1da177e4	16	#include <linux/string.h>
edbaa603	17	#include <linux/device.h>
a62c80e5 RK	18	#include <linux/amba/bus.h>
	19	#include <linux/amba/kmi.h>
	20	#include <linux/amba/clcd.h>
6ef297f8	21	#include <linux/amba/mmci.h>
fced80c7	22	#include <linux/io.h>
5a0e3ad6	23	#include <linux/gfp.h>
046dfa0a	24	#include <linux/mtd/physmap.h>
a613163d	25	#include <linux/platform_data/clk-integrator.h>
4980f9bc LW	26	#include <linux/of_irq.h>
4980f9bc LW	27	#include <linux/of_address.h>
4672cddf	28	#include <linux/of_platform.h>
1da177e4	29
a09e64fb	30	#include <mach/hardware.h>
a285edcf	31	#include <mach/platform.h>
1da177e4 LT	32	#include <asm/setup.h>
1da177e4 LT	33	#include <asm/mach-types.h>
5a46334a	34	#include <asm/hardware/arm_timer.h>
c5a0adb5	35	#include <asm/hardware/icst.h>
1da177e4	36
a09e64fb RK	37	#include <mach/cm.h>
a09e64fb RK	38	#include <mach/lm.h>
695436e3	39	#include <mach/irqs.h>
1da177e4 LT	40
1da177e4 LT	41	#include <asm/mach/arch.h>
1da177e4	42	#include <asm/mach/irq.h>
1da177e4 LT	43	#include <asm/mach/map.h>
	44	#include <asm/mach/time.h>
	45
8a9618f5	46	#include <asm/hardware/timer-sp.h>
5a46334a	47
9dfec4fe	48	#include <plat/clcd.h>
c41b16f8	49	#include <plat/fpga-irq.h>
d77e270c	50	#include <plat/sched_clock.h>
9dfec4fe	51
98c672cf RK	52	#include "common.h"
98c672cf RK	53
1da177e4	54	#define INTCP_PA_FLASH_BASE 0x24000000
1da177e4 LT	55
	56	#define INTCP_PA_CLCD_BASE 0xc0000000
	57
b7a3f8db	58	#define INTCP_VA_CTRL_BASE __io_address(INTEGRATOR_CP_CTL_BASE)
1da177e4 LT	59	#define INTCP_FLASHPROG 0x04
	60	#define CINTEGRATOR_FLASHPROG_FLVPPEN (1 << 0)
	61	#define CINTEGRATOR_FLASHPROG_FLWREN (1 << 1)
	62
	63	/*
	64	* Logical Physical
	65	* f1000000 10000000 Core module registers
	66	* f1100000 11000000 System controller registers
	67	* f1200000 12000000 EBI registers
	68	* f1300000 13000000 Counter/Timer
	69	* f1400000 14000000 Interrupt controller
	70	* f1600000 16000000 UART 0
	71	* f1700000 17000000 UART 1
	72	* f1a00000 1a000000 Debug LEDs
da7ba956 RK	73	* fc900000 c9000000 GPIO
	74	* fca00000 ca000000 SIC
	75	* fcb00000 cb000000 CP system control
1da177e4 LT	76	*/
	77
	78	static struct map_desc intcp_io_desc[] __initdata = {
c8d27298 DS	79	{
	80	.virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
	81	.pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE),
	82	.length = SZ_4K,
	83	.type = MT_DEVICE
	84	}, {
	85	.virtual = IO_ADDRESS(INTEGRATOR_SC_BASE),
	86	.pfn = __phys_to_pfn(INTEGRATOR_SC_BASE),
	87	.length = SZ_4K,
	88	.type = MT_DEVICE
	89	}, {
	90	.virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE),
	91	.pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE),
	92	.length = SZ_4K,
	93	.type = MT_DEVICE
	94	}, {
	95	.virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
	96	.pfn = __phys_to_pfn(INTEGRATOR_CT_BASE),
	97	.length = SZ_4K,
	98	.type = MT_DEVICE
	99	}, {
	100	.virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
	101	.pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
	102	.length = SZ_4K,
	103	.type = MT_DEVICE
	104	}, {
	105	.virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
	106	.pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
	107	.length = SZ_4K,
	108	.type = MT_DEVICE
	109	}, {
	110	.virtual = IO_ADDRESS(INTEGRATOR_UART1_BASE),
	111	.pfn = __phys_to_pfn(INTEGRATOR_UART1_BASE),
	112	.length = SZ_4K,
	113	.type = MT_DEVICE
	114	}, {
	115	.virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
	116	.pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
	117	.length = SZ_4K,
	118	.type = MT_DEVICE
	119	}, {
da7ba956 RK	120	.virtual = IO_ADDRESS(INTEGRATOR_CP_GPIO_BASE),
da7ba956 RK	121	.pfn = __phys_to_pfn(INTEGRATOR_CP_GPIO_BASE),
c8d27298 DS	122	.length = SZ_4K,
	123	.type = MT_DEVICE
	124	}, {
da7ba956 RK	125	.virtual = IO_ADDRESS(INTEGRATOR_CP_SIC_BASE),
da7ba956 RK	126	.pfn = __phys_to_pfn(INTEGRATOR_CP_SIC_BASE),
c8d27298 DS	127	.length = SZ_4K,
	128	.type = MT_DEVICE
	129	}, {
da7ba956 RK	130	.virtual = IO_ADDRESS(INTEGRATOR_CP_CTL_BASE),
da7ba956 RK	131	.pfn = __phys_to_pfn(INTEGRATOR_CP_CTL_BASE),
c8d27298 DS	132	.length = SZ_4K,
	133	.type = MT_DEVICE
	134	}
1da177e4 LT	135	};
	136
	137	static void __init intcp_map_io(void)
	138	{
	139	iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
	140	}
	141
1da177e4 LT	142	/*
	143	* Flash handling.
	144	*/
046dfa0a	145	static int intcp_flash_init(struct platform_device *dev)
1da177e4 LT	146	{
	147	u32 val;
	148
	149	val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
	150	val \|= CINTEGRATOR_FLASHPROG_FLWREN;
	151	writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
	152
	153	return 0;
	154	}
	155
046dfa0a	156	static void intcp_flash_exit(struct platform_device *dev)
1da177e4 LT	157	{
	158	u32 val;
	159
	160	val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
	161	val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN\|CINTEGRATOR_FLASHPROG_FLWREN);
	162	writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
	163	}
	164
667f390b	165	static void intcp_flash_set_vpp(struct platform_device *pdev, int on)
1da177e4 LT	166	{
	167	u32 val;
	168
	169	val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
	170	if (on)
	171	val \|= CINTEGRATOR_FLASHPROG_FLVPPEN;
	172	else
	173	val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
	174	writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
	175	}
	176
046dfa0a	177	static struct physmap_flash_data intcp_flash_data = {
1da177e4 LT	178	.width = 4,
	179	.init = intcp_flash_init,
	180	.exit = intcp_flash_exit,
	181	.set_vpp = intcp_flash_set_vpp,
	182	};
	183
1da177e4 LT	184	/*
	185	* It seems that the card insertion interrupt remains active after
	186	* we've acknowledged it. We therefore ignore the interrupt, and
	187	* rely on reading it from the SIC. This also means that we must
	188	* clear the latched interrupt.
	189	*/
	190	static unsigned int mmc_status(struct device *dev)
	191	{
b7a3f8db AB	192	unsigned int status = readl(__io_address(0xca000000 + 4));
b7a3f8db AB	193	writel(8, __io_address(INTEGRATOR_CP_CTL_BASE + 8));
1da177e4 LT	194
	195	return status & 8;
	196	}
	197
6ef297f8	198	static struct mmci_platform_data mmc_data = {
1da177e4 LT	199	.ocr_mask = MMC_VDD_32_33\|MMC_VDD_33_34,
1da177e4 LT	200	.status = mmc_status,
7fb2bbf4 RK	201	.gpio_wp = -1,
7fb2bbf4 RK	202	.gpio_cd = -1,
1da177e4 LT	203	};
1da177e4 LT	204
1da177e4 LT	205	/*
	206	* CLCD support
	207	*/
1da177e4 LT	208	/*
	209	* Ensure VGA is selected.
	210	*/
	211	static void cp_clcd_enable(struct clcd_fb *fb)
	212	{
e6b9c1f8 RK	213	struct fb_var_screeninfo *var = &fb->fb.var;
e6b9c1f8 RK	214	u32 val = CM_CTRL_STATIC1 \| CM_CTRL_STATIC2;
4774e226	215
e6b9c1f8 RK	216	if (var->bits_per_pixel <= 8 \|\|
	217	(var->bits_per_pixel == 16 && var->green.length == 5))
	218	/* Pseudocolor, RGB555, BGR555 */
	219	val \|= CM_CTRL_LCDMUXSEL_VGA555_TFT555;
4774e226	220	else if (fb->fb.var.bits_per_pixel <= 16)
e6b9c1f8 RK	221	/* truecolor RGB565 */
e6b9c1f8 RK	222	val \|= CM_CTRL_LCDMUXSEL_VGA565_TFT555;
4774e226 RK	223	else
	224	val = 0; /* no idea for this, don't trust the docs */
	225
	226	cm_control(CM_CTRL_LCDMUXSEL_MASK\|
	227	CM_CTRL_LCDEN0\|
	228	CM_CTRL_LCDEN1\|
	229	CM_CTRL_STATIC1\|
	230	CM_CTRL_STATIC2\|
	231	CM_CTRL_STATIC\|
	232	CM_CTRL_n24BITEN, val);
1da177e4 LT	233	}
1da177e4 LT	234
1da177e4 LT	235	static int cp_clcd_setup(struct clcd_fb *fb)
1da177e4 LT	236	{
9dfec4fe RK	237	fb->panel = versatile_clcd_get_panel("VGA");
	238	if (!fb->panel)
	239	return -EINVAL;
1da177e4	240
9dfec4fe	241	return versatile_clcd_setup_dma(fb, SZ_1M);
1da177e4 LT	242	}
	243
	244	static struct clcd_board clcd_data = {
	245	.name = "Integrator/CP",
9dfec4fe	246	.caps = CLCD_CAP_5551 \| CLCD_CAP_RGB565 \| CLCD_CAP_888,
1da177e4 LT	247	.check = clcdfb_check,
	248	.decode = clcdfb_decode,
	249	.enable = cp_clcd_enable,
	250	.setup = cp_clcd_setup,
9dfec4fe RK	251	.mmap = versatile_clcd_mmap_dma,
9dfec4fe RK	252	.remove = versatile_clcd_remove_dma,
1da177e4 LT	253	};
1da177e4 LT	254
d77e270c RK	255	#define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28)
d77e270c RK	256
c735c987 RK	257	static void __init intcp_init_early(void)
c735c987 RK	258	{
d77e270c RK	259	#ifdef CONFIG_PLAT_VERSATILE_SCHED_CLOCK
	260	versatile_sched_clock_init(REFCOUNTER, 24000000);
	261	#endif
c735c987 RK	262	}
c735c987 RK	263
6e3a78d9 OJ	264	#ifdef CONFIG_OF
6e3a78d9 OJ	265
4980f9bc	266	static void __init intcp_timer_init_of(void)
1da177e4	267	{
4980f9bc LW	268	struct device_node *node;
	269	const char *path;
	270	void __iomem *base;
	271	int err;
	272	int irq;
	273
	274	err = of_property_read_string(of_aliases,
	275	"arm,timer-primary", &path);
	276	if (WARN_ON(err))
	277	return;
	278	node = of_find_node_by_path(path);
	279	base = of_iomap(node, 0);
	280	if (WARN_ON(!base))
	281	return;
	282	writel(0, base + TIMER_CTRL);
	283	sp804_clocksource_init(base, node->name);
	284
	285	err = of_property_read_string(of_aliases,
	286	"arm,timer-secondary", &path);
	287	if (WARN_ON(err))
	288	return;
	289	node = of_find_node_by_path(path);
	290	base = of_iomap(node, 0);
	291	if (WARN_ON(!base))
	292	return;
	293	irq = irq_of_parse_and_map(node, 0);
	294	writel(0, base + TIMER_CTRL);
	295	sp804_clockevents_init(base, irq, node->name);
	296	}
1da177e4	297
4980f9bc LW	298	static struct sys_timer cp_of_timer = {
	299	.init = intcp_timer_init_of,
	300	};
1da177e4	301
4980f9bc LW	302	static const struct of_device_id fpga_irq_of_match[] __initconst = {
	303	{ .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
	304	{ /* Sentinel */ }
	305	};
	306
	307	static void __init intcp_init_irq_of(void)
1da177e4	308	{
4980f9bc LW	309	of_irq_init(fpga_irq_of_match);
	310	integrator_clk_init(true);
	311	}
1da177e4	312
4672cddf LW	313	/*
	314	* For the Device Tree, add in the UART, MMC and CLCD specifics as AUXDATA
	315	* and enforce the bus names since these are used for clock lookups.
	316	*/
	317	static struct of_dev_auxdata intcp_auxdata_lookup[] __initdata = {
	318	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
	319	"rtc", NULL),
	320	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
	321	"uart0", &integrator_uart_data),
	322	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
	323	"uart1", &integrator_uart_data),
	324	OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
	325	"kmi0", NULL),
	326	OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
	327	"kmi1", NULL),
	328	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_MMC_BASE,
	329	"mmci", &mmc_data),
	330	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_AACI_BASE,
	331	"aaci", &mmc_data),
	332	OF_DEV_AUXDATA("arm,primecell", INTCP_PA_CLCD_BASE,
	333	"clcd", &clcd_data),
73efd530 LW	334	OF_DEV_AUXDATA("cfi-flash", INTCP_PA_FLASH_BASE,
73efd530 LW	335	"physmap-flash", &intcp_flash_data),
4672cddf LW	336	{ /* sentinel */ },
	337	};
	338
	339	static void __init intcp_init_of(void)
	340	{
	341	of_platform_populate(NULL, of_default_bus_match_table,
	342	intcp_auxdata_lookup, NULL);
4672cddf LW	343	}
4672cddf LW	344
4980f9bc LW	345	static const char * intcp_dt_board_compat[] = {
	346	"arm,integrator-cp",
	347	NULL,
	348	};
1da177e4	349
4980f9bc LW	350	DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
	351	.reserve = integrator_reserve,
	352	.map_io = intcp_map_io,
	353	.nr_irqs = NR_IRQS_INTEGRATOR_CP,
	354	.init_early = intcp_init_early,
	355	.init_irq = intcp_init_irq_of,
	356	.handle_irq = fpga_handle_irq,
	357	.timer = &cp_of_timer,
4672cddf	358	.init_machine = intcp_init_of,
4980f9bc LW	359	.restart = integrator_restart,
	360	.dt_compat = intcp_dt_board_compat,
	361	MACHINE_END
	362
	363	#endif
	364
	365	#ifdef CONFIG_ATAGS
	366
	367	/*
	368	* This is where non-devicetree initialization code is collected and stashed
	369	* for eventual deletion.
	370	*/
	371
73efd530 LW	372	#define INTCP_FLASH_SIZE SZ_32M
	373
	374	static struct resource intcp_flash_resource = {
	375	.start = INTCP_PA_FLASH_BASE,
	376	.end = INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1,
	377	.flags = IORESOURCE_MEM,
	378	};
	379
	380	static struct platform_device intcp_flash_device = {
	381	.name = "physmap-flash",
	382	.id = 0,
	383	.dev = {
	384	.platform_data = &intcp_flash_data,
	385	},
	386	.num_resources = 1,
	387	.resource = &intcp_flash_resource,
	388	};
	389
	390	#define INTCP_ETH_SIZE 0x10
	391
	392	static struct resource smc91x_resources[] = {
	393	[0] = {
	394	.start = INTEGRATOR_CP_ETH_BASE,
	395	.end = INTEGRATOR_CP_ETH_BASE + INTCP_ETH_SIZE - 1,
	396	.flags = IORESOURCE_MEM,
	397	},
	398	[1] = {
	399	.start = IRQ_CP_ETHINT,
	400	.end = IRQ_CP_ETHINT,
	401	.flags = IORESOURCE_IRQ,
	402	},
	403	};
	404
	405	static struct platform_device smc91x_device = {
	406	.name = "smc91x",
	407	.id = 0,
	408	.num_resources = ARRAY_SIZE(smc91x_resources),
	409	.resource = smc91x_resources,
	410	};
	411
	412	static struct platform_device *intcp_devs[] __initdata = {
	413	&intcp_flash_device,
	414	&smc91x_device,
	415	};
	416
4980f9bc LW	417	#define INTCP_VA_CIC_BASE __io_address(INTEGRATOR_HDR_BASE + 0x40)
	418	#define INTCP_VA_PIC_BASE __io_address(INTEGRATOR_IC_BASE)
	419	#define INTCP_VA_SIC_BASE __io_address(INTEGRATOR_CP_SIC_BASE)
	420
	421	static void __init intcp_init_irq(void)
	422	{
	423	u32 pic_mask, cic_mask, sic_mask;
	424
	425	/* These masks are for the HW IRQ registers */
	426	pic_mask = ~((~0u) << (11 - IRQ_PIC_START));
	427	pic_mask \|= (~((~0u) << (29 - 22))) << 22;
	428	cic_mask = ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START));
	429	sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START));
	430
	431	/*
	432	* Disable all interrupt sources
	433	*/
	434	writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
	435	writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
	436	writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
	437	writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
	438	writel(sic_mask, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
	439	writel(sic_mask, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
	440
	441	fpga_irq_init(INTCP_VA_PIC_BASE, "PIC", IRQ_PIC_START,
	442	-1, pic_mask, NULL);
	443
	444	fpga_irq_init(INTCP_VA_CIC_BASE, "CIC", IRQ_CIC_START,
	445	-1, cic_mask, NULL);
	446
	447	fpga_irq_init(INTCP_VA_SIC_BASE, "SIC", IRQ_SIC_START,
	448	IRQ_CP_CPPLDINT, sic_mask, NULL);
	449
	450	integrator_clk_init(true);
1da177e4 LT	451	}
1da177e4 LT	452
5a46334a RK	453	#define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
	454	#define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
	455	#define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)
1da177e4 LT	456
	457	static void __init intcp_timer_init(void)
	458	{
5a46334a RK	459	writel(0, TIMER0_VA_BASE + TIMER_CTRL);
	460	writel(0, TIMER1_VA_BASE + TIMER_CTRL);
	461	writel(0, TIMER2_VA_BASE + TIMER_CTRL);
	462
fb593cf3	463	sp804_clocksource_init(TIMER2_VA_BASE, "timer2");
57cc4f7d	464	sp804_clockevents_init(TIMER1_VA_BASE, IRQ_TIMERINT1, "timer1");
1da177e4 LT	465	}
	466
	467	static struct sys_timer cp_timer = {
	468	.init = intcp_timer_init,
1da177e4 LT	469	};
1da177e4 LT	470
4672cddf LW	471	#define INTEGRATOR_CP_MMC_IRQS { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 }
	472	#define INTEGRATOR_CP_AACI_IRQS { IRQ_CP_AACIINT }
	473
	474	static AMBA_APB_DEVICE(mmc, "mmci", 0, INTEGRATOR_CP_MMC_BASE,
	475	INTEGRATOR_CP_MMC_IRQS, &mmc_data);
	476
	477	static AMBA_APB_DEVICE(aaci, "aaci", 0, INTEGRATOR_CP_AACI_BASE,
	478	INTEGRATOR_CP_AACI_IRQS, NULL);
	479
	480	static AMBA_AHB_DEVICE(clcd, "clcd", 0, INTCP_PA_CLCD_BASE,
	481	{ IRQ_CP_CLCDCINT }, &clcd_data);
	482
	483	static struct amba_device *amba_devs[] __initdata = {
	484	&mmc_device,
	485	&aaci_device,
	486	&clcd_device,
	487	};
	488
	489	static void __init intcp_init(void)
	490	{
	491	int i;
	492
	493	platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
	494
	495	for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
	496	struct amba_device *d = amba_devs[i];
	497	amba_device_register(d, &iomem_resource);
	498	}
	499	integrator_init(true);
	500	}
	501
1da177e4	502	MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
e9dea0c6	503	/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
c5e587a2	504	.atag_offset = 0x100,
98c672cf	505	.reserve = integrator_reserve,
c735c987	506	.map_io = intcp_map_io,
695436e3	507	.nr_irqs = NR_IRQS_INTEGRATOR_CP,
c735c987	508	.init_early = intcp_init_early,
e9dea0c6	509	.init_irq = intcp_init_irq,
3108e6ab	510	.handle_irq = fpga_handle_irq,
1da177e4	511	.timer = &cp_timer,
e9dea0c6	512	.init_machine = intcp_init,
6338b66f	513	.restart = integrator_restart,
1da177e4	514	MACHINE_END
4980f9bc LW	515
4980f9bc LW	516	#endif