[deliverable/linux.git] / arch / arm / mach-integrator / integrator_cp.c

/*
 *  linux/arch/arm/mach-integrator/integrator_cp.c
 *
 *  Copyright (C) 2003 Deep Blue Solutions Ltd
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License.
 */
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/string.h>
#include <linux/sysdev.h>
#include <linux/amba/bus.h>
#include <linux/amba/kmi.h>
#include <linux/amba/clcd.h>
#include <linux/amba/mmci.h>
#include <linux/io.h>
#include <linux/gfp.h>
#include <linux/clkdev.h>

#include <mach/hardware.h>
#include <mach/platform.h>
#include <asm/irq.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/hardware/arm_timer.h>
#include <asm/hardware/icst.h>

#include <mach/cm.h>
#include <mach/lm.h>

#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>

#include <asm/hardware/timer-sp.h>

#include <plat/clcd.h>
#include <plat/fpga-irq.h>
#include <plat/sched_clock.h>

#include "common.h"

#define INTCP_PA_FLASH_BASE		0x24000000
#define INTCP_FLASH_SIZE		SZ_32M

#define INTCP_PA_CLCD_BASE		0xc0000000

#define INTCP_VA_CIC_BASE		__io_address(INTEGRATOR_HDR_BASE + 0x40)
#define INTCP_VA_PIC_BASE		__io_address(INTEGRATOR_IC_BASE)
#define INTCP_VA_SIC_BASE		__io_address(INTEGRATOR_CP_SIC_BASE)

#define INTCP_ETH_SIZE			0x10

#define INTCP_VA_CTRL_BASE		IO_ADDRESS(INTEGRATOR_CP_CTL_BASE)
#define INTCP_FLASHPROG			0x04
#define CINTEGRATOR_FLASHPROG_FLVPPEN	(1 << 0)
#define CINTEGRATOR_FLASHPROG_FLWREN	(1 << 1)

/*
 * Logical      Physical
 * f1000000	10000000	Core module registers
 * f1100000	11000000	System controller registers
 * f1200000	12000000	EBI registers
 * f1300000	13000000	Counter/Timer
 * f1400000	14000000	Interrupt controller
 * f1600000	16000000	UART 0
 * f1700000	17000000	UART 1
 * f1a00000	1a000000	Debug LEDs
 * fc900000	c9000000	GPIO
 * fca00000	ca000000	SIC
 * fcb00000	cb000000	CP system control
 */

static struct map_desc intcp_io_desc[] __initdata = {
	{
		.virtual	= IO_ADDRESS(INTEGRATOR_HDR_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_HDR_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_SC_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_SC_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_EBI_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_EBI_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_CT_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_CT_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_IC_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_IC_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_UART0_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_UART0_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_UART1_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_UART1_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_DBG_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_DBG_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_CP_GPIO_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_CP_GPIO_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_CP_SIC_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_CP_SIC_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_CP_CTL_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_CP_CTL_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}
};

static void __init intcp_map_io(void)
{
	iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
}

static struct fpga_irq_data cic_irq_data = {
	.base		= INTCP_VA_CIC_BASE,
	.irq_start	= IRQ_CIC_START,
	.chip.name	= "CIC",
};

static struct fpga_irq_data pic_irq_data = {
	.base		= INTCP_VA_PIC_BASE,
	.irq_start	= IRQ_PIC_START,
	.chip.name	= "PIC",
};

static struct fpga_irq_data sic_irq_data = {
	.base		= INTCP_VA_SIC_BASE,
	.irq_start	= IRQ_SIC_START,
	.chip.name	= "SIC",
};

static void __init intcp_init_irq(void)
{
	u32 pic_mask, sic_mask;

	pic_mask = ~((~0u) << (11 - IRQ_PIC_START));
	pic_mask |= (~((~0u) << (29 - 22))) << 22;
	sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START));

	/*
	 * Disable all interrupt sources
	 */
	writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
	writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
	writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
	writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
	writel(sic_mask, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
	writel(sic_mask, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);

	fpga_irq_init(-1, pic_mask, &pic_irq_data);

	fpga_irq_init(-1, ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START)),
		&cic_irq_data);

	fpga_irq_init(IRQ_CP_CPPLDINT, sic_mask, &sic_irq_data);
}

/*
 * Clock handling
 */
#define CM_LOCK		(__io_address(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_LOCK_OFFSET)
#define CM_AUXOSC	(__io_address(INTEGRATOR_HDR_BASE)+0x1c)

static const struct icst_params cp_auxvco_params = {
	.ref		= 24000000,
	.vco_max	= ICST525_VCO_MAX_5V,
	.vco_min	= ICST525_VCO_MIN,
	.vd_min 	= 8,
	.vd_max 	= 263,
	.rd_min 	= 3,
	.rd_max 	= 65,
	.s2div		= icst525_s2div,
	.idx2s		= icst525_idx2s,
};

static void cp_auxvco_set(struct clk *clk, struct icst_vco vco)
{
	u32 val;

	val = readl(clk->vcoreg) & ~0x7ffff;
	val |= vco.v | (vco.r << 9) | (vco.s << 16);

	writel(0xa05f, CM_LOCK);
	writel(val, clk->vcoreg);
	writel(0, CM_LOCK);
}

static const struct clk_ops cp_auxclk_ops = {
	.round	= icst_clk_round,
	.set	= icst_clk_set,
	.setvco	= cp_auxvco_set,
};

static struct clk cp_auxclk = {
	.ops	= &cp_auxclk_ops,
	.params	= &cp_auxvco_params,
	.vcoreg	= CM_AUXOSC,
};

static struct clk_lookup cp_lookups[] = {
	{	/* CLCD */
		.dev_id		= "mb:c0",
		.clk		= &cp_auxclk,
	},
};

/*
 * Flash handling.
 */
static int intcp_flash_init(void)
{
	u32 val;

	val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
	val |= CINTEGRATOR_FLASHPROG_FLWREN;
	writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);

	return 0;
}

static void intcp_flash_exit(void)
{
	u32 val;

	val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
	val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN);
	writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
}

static void intcp_flash_set_vpp(int on)
{
	u32 val;

	val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
	if (on)
		val |= CINTEGRATOR_FLASHPROG_FLVPPEN;
	else
		val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
	writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
}

static struct flash_platform_data intcp_flash_data = {
	.map_name	= "cfi_probe",
	.width		= 4,
	.init		= intcp_flash_init,
	.exit		= intcp_flash_exit,
	.set_vpp	= intcp_flash_set_vpp,
};

static struct resource intcp_flash_resource = {
	.start		= INTCP_PA_FLASH_BASE,
	.end		= INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1,
	.flags		= IORESOURCE_MEM,
};

static struct platform_device intcp_flash_device = {
	.name		= "armflash",
	.id		= 0,
	.dev		= {
		.platform_data	= &intcp_flash_data,
	},
	.num_resources	= 1,
	.resource	= &intcp_flash_resource,
};

static struct resource smc91x_resources[] = {
	[0] = {
		.start	= INTEGRATOR_CP_ETH_BASE,
		.end	= INTEGRATOR_CP_ETH_BASE + INTCP_ETH_SIZE - 1,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= IRQ_CP_ETHINT,
		.end	= IRQ_CP_ETHINT,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device smc91x_device = {
	.name		= "smc91x",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(smc91x_resources),
	.resource	= smc91x_resources,
};

static struct platform_device *intcp_devs[] __initdata = {
	&intcp_flash_device,
	&smc91x_device,
};

/*
 * It seems that the card insertion interrupt remains active after
 * we've acknowledged it.  We therefore ignore the interrupt, and
 * rely on reading it from the SIC.  This also means that we must
 * clear the latched interrupt.
 */
static unsigned int mmc_status(struct device *dev)
{
	unsigned int status = readl(IO_ADDRESS(0xca000000 + 4));
	writel(8, IO_ADDRESS(INTEGRATOR_CP_CTL_BASE + 8));

	return status & 8;
}

static struct mmci_platform_data mmc_data = {
	.ocr_mask	= MMC_VDD_32_33|MMC_VDD_33_34,
	.status		= mmc_status,
	.gpio_wp	= -1,
	.gpio_cd	= -1,
};

static struct amba_device mmc_device = {
	.dev		= {
		.init_name = "mb:1c",
		.platform_data = &mmc_data,
	},
	.res		= {
		.start	= INTEGRATOR_CP_MMC_BASE,
		.end	= INTEGRATOR_CP_MMC_BASE + SZ_4K - 1,
		.flags	= IORESOURCE_MEM,
	},
	.irq		= { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 },
	.periphid	= 0,
};

static struct amba_device aaci_device = {
	.dev		= {
		.init_name = "mb:1d",
	},
	.res		= {
		.start	= INTEGRATOR_CP_AACI_BASE,
		.end	= INTEGRATOR_CP_AACI_BASE + SZ_4K - 1,
		.flags	= IORESOURCE_MEM,
	},
	.irq		= { IRQ_CP_AACIINT, NO_IRQ },
	.periphid	= 0,
};


/*
 * CLCD support
 */
/*
 * Ensure VGA is selected.
 */
static void cp_clcd_enable(struct clcd_fb *fb)
{
	struct fb_var_screeninfo *var = &fb->fb.var;
	u32 val = CM_CTRL_STATIC1 | CM_CTRL_STATIC2;

	if (var->bits_per_pixel <= 8 ||
	    (var->bits_per_pixel == 16 && var->green.length == 5))
		/* Pseudocolor, RGB555, BGR555 */
		val |= CM_CTRL_LCDMUXSEL_VGA555_TFT555;
	else if (fb->fb.var.bits_per_pixel <= 16)
		/* truecolor RGB565 */
		val |= CM_CTRL_LCDMUXSEL_VGA565_TFT555;
	else
		val = 0; /* no idea for this, don't trust the docs */

	cm_control(CM_CTRL_LCDMUXSEL_MASK|
		   CM_CTRL_LCDEN0|
		   CM_CTRL_LCDEN1|
		   CM_CTRL_STATIC1|
		   CM_CTRL_STATIC2|
		   CM_CTRL_STATIC|
		   CM_CTRL_n24BITEN, val);
}

static int cp_clcd_setup(struct clcd_fb *fb)
{
	fb->panel = versatile_clcd_get_panel("VGA");
	if (!fb->panel)
		return -EINVAL;

	return versatile_clcd_setup_dma(fb, SZ_1M);
}

static struct clcd_board clcd_data = {
	.name		= "Integrator/CP",
	.caps		= CLCD_CAP_5551 | CLCD_CAP_RGB565 | CLCD_CAP_888,
	.check		= clcdfb_check,
	.decode		= clcdfb_decode,
	.enable		= cp_clcd_enable,
	.setup		= cp_clcd_setup,
	.mmap		= versatile_clcd_mmap_dma,
	.remove		= versatile_clcd_remove_dma,
};

static struct amba_device clcd_device = {
	.dev		= {
		.init_name = "mb:c0",
		.coherent_dma_mask = ~0,
		.platform_data = &clcd_data,
	},
	.res		= {
		.start	= INTCP_PA_CLCD_BASE,
		.end	= INTCP_PA_CLCD_BASE + SZ_4K - 1,
		.flags	= IORESOURCE_MEM,
	},
	.dma_mask	= ~0,
	.irq		= { IRQ_CP_CLCDCINT, NO_IRQ },
	.periphid	= 0,
};

static struct amba_device *amba_devs[] __initdata = {
	&mmc_device,
	&aaci_device,
	&clcd_device,
};

#define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28)

static void __init intcp_init_early(void)
{
	clkdev_add_table(cp_lookups, ARRAY_SIZE(cp_lookups));

	integrator_init_early();

#ifdef CONFIG_PLAT_VERSATILE_SCHED_CLOCK
	versatile_sched_clock_init(REFCOUNTER, 24000000);
#endif
}

static void __init intcp_init(void)
{
	int i;

	platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));

	for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
		struct amba_device *d = amba_devs[i];
		amba_device_register(d, &iomem_resource);
	}
}

#define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
#define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
#define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)

static void __init intcp_timer_init(void)
{
	writel(0, TIMER0_VA_BASE + TIMER_CTRL);
	writel(0, TIMER1_VA_BASE + TIMER_CTRL);
	writel(0, TIMER2_VA_BASE + TIMER_CTRL);

	sp804_clocksource_init(TIMER2_VA_BASE);
	sp804_clockevents_init(TIMER1_VA_BASE, IRQ_TIMERINT1);
}

static struct sys_timer cp_timer = {
	.init		= intcp_timer_init,
};

MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
	/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
	.boot_params	= 0x00000100,
	.reserve	= integrator_reserve,
	.map_io		= intcp_map_io,
	.init_early	= intcp_init_early,
	.init_irq	= intcp_init_irq,
	.timer		= &cp_timer,
	.init_machine	= intcp_init,
MACHINE_END
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-integrator/integrator_cp.c
	3	*
	4	* Copyright (C) 2003 Deep Blue Solutions Ltd
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License.
	9	*/
	10	#include <linux/types.h>
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
	13	#include <linux/list.h>
d052d1be	14	#include <linux/platform_device.h>
1da177e4	15	#include <linux/dma-mapping.h>
1da177e4 LT	16	#include <linux/string.h>
1da177e4 LT	17	#include <linux/sysdev.h>
a62c80e5 RK	18	#include <linux/amba/bus.h>
	19	#include <linux/amba/kmi.h>
	20	#include <linux/amba/clcd.h>
6ef297f8	21	#include <linux/amba/mmci.h>
fced80c7	22	#include <linux/io.h>
5a0e3ad6	23	#include <linux/gfp.h>
6d803ba7	24	#include <linux/clkdev.h>
1da177e4	25
a09e64fb	26	#include <mach/hardware.h>
a285edcf	27	#include <mach/platform.h>
1da177e4 LT	28	#include <asm/irq.h>
	29	#include <asm/setup.h>
	30	#include <asm/mach-types.h>
5a46334a	31	#include <asm/hardware/arm_timer.h>
c5a0adb5	32	#include <asm/hardware/icst.h>
1da177e4	33
a09e64fb RK	34	#include <mach/cm.h>
a09e64fb RK	35	#include <mach/lm.h>
1da177e4 LT	36
	37	#include <asm/mach/arch.h>
	38	#include <asm/mach/flash.h>
	39	#include <asm/mach/irq.h>
1da177e4 LT	40	#include <asm/mach/map.h>
	41	#include <asm/mach/time.h>
	42
8a9618f5	43	#include <asm/hardware/timer-sp.h>
5a46334a	44
9dfec4fe	45	#include <plat/clcd.h>
c41b16f8	46	#include <plat/fpga-irq.h>
d77e270c	47	#include <plat/sched_clock.h>
9dfec4fe	48
98c672cf RK	49	#include "common.h"
98c672cf RK	50
1da177e4 LT	51	#define INTCP_PA_FLASH_BASE 0x24000000
	52	#define INTCP_FLASH_SIZE SZ_32M
	53
	54	#define INTCP_PA_CLCD_BASE 0xc0000000
	55
c41b16f8 RK	56	#define INTCP_VA_CIC_BASE __io_address(INTEGRATOR_HDR_BASE + 0x40)
	57	#define INTCP_VA_PIC_BASE __io_address(INTEGRATOR_IC_BASE)
	58	#define INTCP_VA_SIC_BASE __io_address(INTEGRATOR_CP_SIC_BASE)
1da177e4	59
1da177e4 LT	60	#define INTCP_ETH_SIZE 0x10
1da177e4 LT	61
da7ba956	62	#define INTCP_VA_CTRL_BASE IO_ADDRESS(INTEGRATOR_CP_CTL_BASE)
1da177e4 LT	63	#define INTCP_FLASHPROG 0x04
	64	#define CINTEGRATOR_FLASHPROG_FLVPPEN (1 << 0)
	65	#define CINTEGRATOR_FLASHPROG_FLWREN (1 << 1)
	66
	67	/*
	68	* Logical Physical
	69	* f1000000 10000000 Core module registers
	70	* f1100000 11000000 System controller registers
	71	* f1200000 12000000 EBI registers
	72	* f1300000 13000000 Counter/Timer
	73	* f1400000 14000000 Interrupt controller
	74	* f1600000 16000000 UART 0
	75	* f1700000 17000000 UART 1
	76	* f1a00000 1a000000 Debug LEDs
da7ba956 RK	77	* fc900000 c9000000 GPIO
	78	* fca00000 ca000000 SIC
	79	* fcb00000 cb000000 CP system control
1da177e4 LT	80	*/
	81
	82	static struct map_desc intcp_io_desc[] __initdata = {
c8d27298 DS	83	{
	84	.virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
	85	.pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE),
	86	.length = SZ_4K,
	87	.type = MT_DEVICE
	88	}, {
	89	.virtual = IO_ADDRESS(INTEGRATOR_SC_BASE),
	90	.pfn = __phys_to_pfn(INTEGRATOR_SC_BASE),
	91	.length = SZ_4K,
	92	.type = MT_DEVICE
	93	}, {
	94	.virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE),
	95	.pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE),
	96	.length = SZ_4K,
	97	.type = MT_DEVICE
	98	}, {
	99	.virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
	100	.pfn = __phys_to_pfn(INTEGRATOR_CT_BASE),
	101	.length = SZ_4K,
	102	.type = MT_DEVICE
	103	}, {
	104	.virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
	105	.pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
	106	.length = SZ_4K,
	107	.type = MT_DEVICE
	108	}, {
	109	.virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
	110	.pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
	111	.length = SZ_4K,
	112	.type = MT_DEVICE
	113	}, {
	114	.virtual = IO_ADDRESS(INTEGRATOR_UART1_BASE),
	115	.pfn = __phys_to_pfn(INTEGRATOR_UART1_BASE),
	116	.length = SZ_4K,
	117	.type = MT_DEVICE
	118	}, {
	119	.virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
	120	.pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
	121	.length = SZ_4K,
	122	.type = MT_DEVICE
	123	}, {
da7ba956 RK	124	.virtual = IO_ADDRESS(INTEGRATOR_CP_GPIO_BASE),
da7ba956 RK	125	.pfn = __phys_to_pfn(INTEGRATOR_CP_GPIO_BASE),
c8d27298 DS	126	.length = SZ_4K,
	127	.type = MT_DEVICE
	128	}, {
da7ba956 RK	129	.virtual = IO_ADDRESS(INTEGRATOR_CP_SIC_BASE),
da7ba956 RK	130	.pfn = __phys_to_pfn(INTEGRATOR_CP_SIC_BASE),
c8d27298 DS	131	.length = SZ_4K,
	132	.type = MT_DEVICE
	133	}, {
da7ba956 RK	134	.virtual = IO_ADDRESS(INTEGRATOR_CP_CTL_BASE),
da7ba956 RK	135	.pfn = __phys_to_pfn(INTEGRATOR_CP_CTL_BASE),
c8d27298 DS	136	.length = SZ_4K,
	137	.type = MT_DEVICE
	138	}
1da177e4 LT	139	};
	140
	141	static void __init intcp_map_io(void)
	142	{
	143	iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
	144	}
	145
c41b16f8 RK	146	static struct fpga_irq_data cic_irq_data = {
	147	.base = INTCP_VA_CIC_BASE,
	148	.irq_start = IRQ_CIC_START,
	149	.chip.name = "CIC",
1da177e4 LT	150	};
1da177e4 LT	151
c41b16f8 RK	152	static struct fpga_irq_data pic_irq_data = {
	153	.base = INTCP_VA_PIC_BASE,
	154	.irq_start = IRQ_PIC_START,
	155	.chip.name = "PIC",
1da177e4 LT	156	};
1da177e4 LT	157
c41b16f8 RK	158	static struct fpga_irq_data sic_irq_data = {
	159	.base = INTCP_VA_SIC_BASE,
	160	.irq_start = IRQ_SIC_START,
	161	.chip.name = "SIC",
1da177e4 LT	162	};
1da177e4 LT	163
1da177e4 LT	164	static void __init intcp_init_irq(void)
1da177e4 LT	165	{
c41b16f8 RK	166	u32 pic_mask, sic_mask;
	167
	168	pic_mask = ~((~0u) << (11 - IRQ_PIC_START));
	169	pic_mask \|= (~((~0u) << (29 - 22))) << 22;
	170	sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START));
1da177e4 LT	171
	172	/*
	173	* Disable all interrupt sources
	174	*/
c41b16f8 RK	175	writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
	176	writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
	177	writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
	178	writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
	179	writel(sic_mask, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
	180	writel(sic_mask, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
1da177e4	181
c41b16f8	182	fpga_irq_init(-1, pic_mask, &pic_irq_data);
1da177e4	183
c41b16f8 RK	184	fpga_irq_init(-1, ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START)),
c41b16f8 RK	185	&cic_irq_data);
1da177e4	186
c41b16f8	187	fpga_irq_init(IRQ_CP_CPPLDINT, sic_mask, &sic_irq_data);
1da177e4 LT	188	}
	189
	190	/*
	191	* Clock handling
	192	*/
d1914c7e RK	193	#define CM_LOCK (__io_address(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_LOCK_OFFSET)
d1914c7e RK	194	#define CM_AUXOSC (__io_address(INTEGRATOR_HDR_BASE)+0x1c)
1da177e4	195
39c0cb02	196	static const struct icst_params cp_auxvco_params = {
64fceb1d	197	.ref = 24000000,
4de2edbd	198	.vco_max = ICST525_VCO_MAX_5V,
e73a46a3	199	.vco_min = ICST525_VCO_MIN,
1da177e4 LT	200	.vd_min = 8,
	201	.vd_max = 263,
	202	.rd_min = 3,
	203	.rd_max = 65,
232eaf7f RK	204	.s2div = icst525_s2div,
232eaf7f RK	205	.idx2s = icst525_idx2s,
1da177e4 LT	206	};
1da177e4 LT	207
39c0cb02	208	static void cp_auxvco_set(struct clk *clk, struct icst_vco vco)
1da177e4 LT	209	{
	210	u32 val;
	211
d1914c7e	212	val = readl(clk->vcoreg) & ~0x7ffff;
1da177e4 LT	213	val \|= vco.v \| (vco.r << 9) \| (vco.s << 16);
	214
	215	writel(0xa05f, CM_LOCK);
d1914c7e	216	writel(val, clk->vcoreg);
1da177e4 LT	217	writel(0, CM_LOCK);
	218	}
	219
9bf5b2ef RK	220	static const struct clk_ops cp_auxclk_ops = {
	221	.round = icst_clk_round,
	222	.set = icst_clk_set,
	223	.setvco = cp_auxvco_set,
	224	};
	225
d72fbdf0	226	static struct clk cp_auxclk = {
9bf5b2ef	227	.ops = &cp_auxclk_ops,
1da177e4	228	.params = &cp_auxvco_params,
d1914c7e	229	.vcoreg = CM_AUXOSC,
1da177e4 LT	230	};
1da177e4 LT	231
d72fbdf0 RK	232	static struct clk_lookup cp_lookups[] = {
	233	{ /* CLCD */
	234	.dev_id = "mb:c0",
	235	.clk = &cp_auxclk,
	236	},
1da177e4 LT	237	};
	238
	239	/*
	240	* Flash handling.
	241	*/
	242	static int intcp_flash_init(void)
	243	{
	244	u32 val;
	245
	246	val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
	247	val \|= CINTEGRATOR_FLASHPROG_FLWREN;
	248	writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
	249
	250	return 0;
	251	}
	252
	253	static void intcp_flash_exit(void)
	254	{
	255	u32 val;
	256
	257	val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
	258	val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN\|CINTEGRATOR_FLASHPROG_FLWREN);
	259	writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
	260	}
	261
	262	static void intcp_flash_set_vpp(int on)
	263	{
	264	u32 val;
	265
	266	val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
	267	if (on)
	268	val \|= CINTEGRATOR_FLASHPROG_FLVPPEN;
	269	else
	270	val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
	271	writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
	272	}
	273
	274	static struct flash_platform_data intcp_flash_data = {
	275	.map_name = "cfi_probe",
	276	.width = 4,
	277	.init = intcp_flash_init,
	278	.exit = intcp_flash_exit,
	279	.set_vpp = intcp_flash_set_vpp,
	280	};
	281
	282	static struct resource intcp_flash_resource = {
	283	.start = INTCP_PA_FLASH_BASE,
	284	.end = INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1,
	285	.flags = IORESOURCE_MEM,
	286	};
	287
	288	static struct platform_device intcp_flash_device = {
	289	.name = "armflash",
	290	.id = 0,
	291	.dev = {
	292	.platform_data = &intcp_flash_data,
	293	},
	294	.num_resources = 1,
	295	.resource = &intcp_flash_resource,
	296	};
	297
	298	static struct resource smc91x_resources[] = {
	299	[0] = {
da7ba956 RK	300	.start = INTEGRATOR_CP_ETH_BASE,
da7ba956 RK	301	.end = INTEGRATOR_CP_ETH_BASE + INTCP_ETH_SIZE - 1,
1da177e4 LT	302	.flags = IORESOURCE_MEM,
	303	},
	304	[1] = {
	305	.start = IRQ_CP_ETHINT,
	306	.end = IRQ_CP_ETHINT,
	307	.flags = IORESOURCE_IRQ,
	308	},
	309	};
	310
	311	static struct platform_device smc91x_device = {
	312	.name = "smc91x",
	313	.id = 0,
	314	.num_resources = ARRAY_SIZE(smc91x_resources),
	315	.resource = smc91x_resources,
	316	};
	317
	318	static struct platform_device *intcp_devs[] __initdata = {
	319	&intcp_flash_device,
	320	&smc91x_device,
	321	};
	322
	323	/*
	324	* It seems that the card insertion interrupt remains active after
	325	* we've acknowledged it. We therefore ignore the interrupt, and
	326	* rely on reading it from the SIC. This also means that we must
	327	* clear the latched interrupt.
	328	*/
	329	static unsigned int mmc_status(struct device *dev)
	330	{
b830b9b5 RK	331	unsigned int status = readl(IO_ADDRESS(0xca000000 + 4));
b830b9b5 RK	332	writel(8, IO_ADDRESS(INTEGRATOR_CP_CTL_BASE + 8));
1da177e4 LT	333
	334	return status & 8;
	335	}
	336
6ef297f8	337	static struct mmci_platform_data mmc_data = {
1da177e4 LT	338	.ocr_mask = MMC_VDD_32_33\|MMC_VDD_33_34,
1da177e4 LT	339	.status = mmc_status,
7fb2bbf4 RK	340	.gpio_wp = -1,
7fb2bbf4 RK	341	.gpio_cd = -1,
1da177e4 LT	342	};
	343
	344	static struct amba_device mmc_device = {
	345	.dev = {
1d559e29	346	.init_name = "mb:1c",
1da177e4 LT	347	.platform_data = &mmc_data,
	348	},
	349	.res = {
da7ba956 RK	350	.start = INTEGRATOR_CP_MMC_BASE,
da7ba956 RK	351	.end = INTEGRATOR_CP_MMC_BASE + SZ_4K - 1,
1da177e4 LT	352	.flags = IORESOURCE_MEM,
	353	},
	354	.irq = { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 },
	355	.periphid = 0,
	356	};
	357
	358	static struct amba_device aaci_device = {
	359	.dev = {
1d559e29	360	.init_name = "mb:1d",
1da177e4 LT	361	},
1da177e4 LT	362	.res = {
da7ba956 RK	363	.start = INTEGRATOR_CP_AACI_BASE,
da7ba956 RK	364	.end = INTEGRATOR_CP_AACI_BASE + SZ_4K - 1,
1da177e4 LT	365	.flags = IORESOURCE_MEM,
	366	},
	367	.irq = { IRQ_CP_AACIINT, NO_IRQ },
	368	.periphid = 0,
	369	};
	370
	371
	372	/*
	373	* CLCD support
	374	*/
1da177e4 LT	375	/*
	376	* Ensure VGA is selected.
	377	*/
	378	static void cp_clcd_enable(struct clcd_fb *fb)
	379	{
e6b9c1f8 RK	380	struct fb_var_screeninfo *var = &fb->fb.var;
e6b9c1f8 RK	381	u32 val = CM_CTRL_STATIC1 \| CM_CTRL_STATIC2;
4774e226	382
e6b9c1f8 RK	383	if (var->bits_per_pixel <= 8 \|\|
	384	(var->bits_per_pixel == 16 && var->green.length == 5))
	385	/* Pseudocolor, RGB555, BGR555 */
	386	val \|= CM_CTRL_LCDMUXSEL_VGA555_TFT555;
4774e226	387	else if (fb->fb.var.bits_per_pixel <= 16)
e6b9c1f8 RK	388	/* truecolor RGB565 */
e6b9c1f8 RK	389	val \|= CM_CTRL_LCDMUXSEL_VGA565_TFT555;
4774e226 RK	390	else
	391	val = 0; /* no idea for this, don't trust the docs */
	392
	393	cm_control(CM_CTRL_LCDMUXSEL_MASK\|
	394	CM_CTRL_LCDEN0\|
	395	CM_CTRL_LCDEN1\|
	396	CM_CTRL_STATIC1\|
	397	CM_CTRL_STATIC2\|
	398	CM_CTRL_STATIC\|
	399	CM_CTRL_n24BITEN, val);
1da177e4 LT	400	}
1da177e4 LT	401
1da177e4 LT	402	static int cp_clcd_setup(struct clcd_fb *fb)
1da177e4 LT	403	{
9dfec4fe RK	404	fb->panel = versatile_clcd_get_panel("VGA");
	405	if (!fb->panel)
	406	return -EINVAL;
1da177e4	407
9dfec4fe	408	return versatile_clcd_setup_dma(fb, SZ_1M);
1da177e4 LT	409	}
	410
	411	static struct clcd_board clcd_data = {
	412	.name = "Integrator/CP",
9dfec4fe	413	.caps = CLCD_CAP_5551 \| CLCD_CAP_RGB565 \| CLCD_CAP_888,
1da177e4 LT	414	.check = clcdfb_check,
	415	.decode = clcdfb_decode,
	416	.enable = cp_clcd_enable,
	417	.setup = cp_clcd_setup,
9dfec4fe RK	418	.mmap = versatile_clcd_mmap_dma,
9dfec4fe RK	419	.remove = versatile_clcd_remove_dma,
1da177e4 LT	420	};
	421
	422	static struct amba_device clcd_device = {
	423	.dev = {
1d559e29	424	.init_name = "mb:c0",
1da177e4 LT	425	.coherent_dma_mask = ~0,
	426	.platform_data = &clcd_data,
	427	},
	428	.res = {
	429	.start = INTCP_PA_CLCD_BASE,
	430	.end = INTCP_PA_CLCD_BASE + SZ_4K - 1,
	431	.flags = IORESOURCE_MEM,
	432	},
	433	.dma_mask = ~0,
	434	.irq = { IRQ_CP_CLCDCINT, NO_IRQ },
	435	.periphid = 0,
	436	};
	437
	438	static struct amba_device *amba_devs[] __initdata = {
	439	&mmc_device,
	440	&aaci_device,
	441	&clcd_device,
	442	};
	443
d77e270c RK	444	#define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28)
d77e270c RK	445
c735c987 RK	446	static void __init intcp_init_early(void)
	447	{
	448	clkdev_add_table(cp_lookups, ARRAY_SIZE(cp_lookups));
	449
	450	integrator_init_early();
d77e270c RK	451
	452	#ifdef CONFIG_PLAT_VERSATILE_SCHED_CLOCK
	453	versatile_sched_clock_init(REFCOUNTER, 24000000);
	454	#endif
c735c987 RK	455	}
c735c987 RK	456
1da177e4 LT	457	static void __init intcp_init(void)
	458	{
	459	int i;
	460
1da177e4 LT	461	platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
	462
	463	for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
	464	struct amba_device *d = amba_devs[i];
	465	amba_device_register(d, &iomem_resource);
	466	}
	467	}
	468
5a46334a RK	469	#define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
	470	#define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
	471	#define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)
1da177e4 LT	472
	473	static void __init intcp_timer_init(void)
	474	{
5a46334a RK	475	writel(0, TIMER0_VA_BASE + TIMER_CTRL);
	476	writel(0, TIMER1_VA_BASE + TIMER_CTRL);
	477	writel(0, TIMER2_VA_BASE + TIMER_CTRL);
	478
	479	sp804_clocksource_init(TIMER2_VA_BASE);
	480	sp804_clockevents_init(TIMER1_VA_BASE, IRQ_TIMERINT1);
1da177e4 LT	481	}
	482
	483	static struct sys_timer cp_timer = {
	484	.init = intcp_timer_init,
1da177e4 LT	485	};
	486
	487	MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
e9dea0c6	488	/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
e9dea0c6	489	.boot_params = 0x00000100,
98c672cf	490	.reserve = integrator_reserve,
c735c987 RK	491	.map_io = intcp_map_io,
c735c987 RK	492	.init_early = intcp_init_early,
e9dea0c6	493	.init_irq = intcp_init_irq,
1da177e4	494	.timer = &cp_timer,
e9dea0c6	495	.init_machine = intcp_init,
1da177e4	496	MACHINE_END