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ARM: set vga memory base at run-time
[deliverable/linux.git] / arch / arm / mach-integrator / pci_v3.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/arch/arm/mach-integrator/pci_v3.c
3 *
4 * PCI functions for V3 host PCI bridge
5 *
6 * Copyright (C) 1999 ARM Limited
7 * Copyright (C) 2000-2001 Deep Blue Solutions Ltd
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
1da177e4
LT		 23#include <linux/kernel.h>
24#include <linux/pci.h>
1da177e4
LT		 25#include <linux/ioport.h>
26#include <linux/interrupt.h>
27#include <linux/spinlock.h>
28#include <linux/init.h>
fced80c7 29#include <linux/io.h>
cc22b4c1 30#include <video/vga.h>
1da177e4 31
a09e64fb 32#include <mach/hardware.h>
a285edcf 33#include <mach/platform.h>
1da177e4 34#include <asm/irq.h>
d43c36dc 35#include <asm/signal.h>
1da177e4
LT		 36#include <asm/system.h>
37#include <asm/mach/pci.h>
c6af66b9 38#include <asm/irq_regs.h>
1da177e4
LT		 39
40#include <asm/hardware/pci_v3.h>
41
42/*
43 * The V3 PCI interface chip in Integrator provides several windows from
44 * local bus memory into the PCI memory areas. Unfortunately, there
45 * are not really enough windows for our usage, therefore we reuse
46 * one of the windows for access to PCI configuration space. The
47 * memory map is as follows:
48 *
49 * Local Bus Memory Usage
50 *
51 * 40000000 - 4FFFFFFF PCI memory. 256M non-prefetchable
52 * 50000000 - 5FFFFFFF PCI memory. 256M prefetchable
53 * 60000000 - 60FFFFFF PCI IO. 16M
54 * 61000000 - 61FFFFFF PCI Configuration. 16M
55 *
56 * There are three V3 windows, each described by a pair of V3 registers.
57 * These are LB_BASE0/LB_MAP0, LB_BASE1/LB_MAP1 and LB_BASE2/LB_MAP2.
58 * Base0 and Base1 can be used for any type of PCI memory access. Base2
59 * can be used either for PCI I/O or for I20 accesses. By default, uHAL
60 * uses this only for PCI IO space.
61 *
62 * Normally these spaces are mapped using the following base registers:
63 *
64 * Usage Local Bus Memory Base/Map registers used
65 *
66 * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0
67 * Mem 50000000 - 5FFFFFFF LB_BASE1/LB_MAP1
68 * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2
69 * Cfg 61000000 - 61FFFFFF
70 *
71 * This means that I20 and PCI configuration space accesses will fail.
72 * When PCI configuration accesses are needed (via the uHAL PCI
73 * configuration space primitives) we must remap the spaces as follows:
74 *
75 * Usage Local Bus Memory Base/Map registers used
76 *
77 * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0
78 * Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0
79 * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2
80 * Cfg 61000000 - 61FFFFFF LB_BASE1/LB_MAP1
81 *
82 * To make this work, the code depends on overlapping windows working.
83 * The V3 chip translates an address by checking its range within
84 * each of the BASE/MAP pairs in turn (in ascending register number
85 * order). It will use the first matching pair. So, for example,
86 * if the same address is mapped by both LB_BASE0/LB_MAP0 and
87 * LB_BASE1/LB_MAP1, the V3 will use the translation from
88 * LB_BASE0/LB_MAP0.
89 *
90 * To allow PCI Configuration space access, the code enlarges the
91 * window mapped by LB_BASE0/LB_MAP0 from 256M to 512M. This occludes
92 * the windows currently mapped by LB_BASE1/LB_MAP1 so that it can
93 * be remapped for use by configuration cycles.
94 *
95 * At the end of the PCI Configuration space accesses,
96 * LB_BASE1/LB_MAP1 is reset to map PCI Memory. Finally the window
97 * mapped by LB_BASE0/LB_MAP0 is reduced in size from 512M to 256M to
98 * reveal the now restored LB_BASE1/LB_MAP1 window.
99 *
100 * NOTE: We do not set up I2O mapping. I suspect that this is only
101 * for an intelligent (target) device. Using I2O disables most of
102 * the mappings into PCI memory.
103 */
104
105// V3 access routines
106#define v3_writeb(o,v) __raw_writeb(v, PCI_V3_VADDR + (unsigned int)(o))
107#define v3_readb(o) (__raw_readb(PCI_V3_VADDR + (unsigned int)(o)))
108
109#define v3_writew(o,v) __raw_writew(v, PCI_V3_VADDR + (unsigned int)(o))
110#define v3_readw(o) (__raw_readw(PCI_V3_VADDR + (unsigned int)(o)))
111
112#define v3_writel(o,v) __raw_writel(v, PCI_V3_VADDR + (unsigned int)(o))
113#define v3_readl(o) (__raw_readl(PCI_V3_VADDR + (unsigned int)(o)))
114
115/*============================================================================
116 *
117 * routine: uHALir_PCIMakeConfigAddress()
118 *
119 * parameters: bus = which bus
120 * device = which device
121 * function = which function
122 * offset = configuration space register we are interested in
123 *
124 * description: this routine will generate a platform dependent config
125 * address.
126 *
127 * calls: none
128 *
129 * returns: configuration address to play on the PCI bus
130 *
131 * To generate the appropriate PCI configuration cycles in the PCI
132 * configuration address space, you present the V3 with the following pattern
133 * (which is very nearly a type 1 (except that the lower two bits are 00 and
134 * not 01). In order for this mapping to work you need to set up one of
135 * the local to PCI aperatures to 16Mbytes in length translating to
136 * PCI configuration space starting at 0x0000.0000.
137 *
138 * PCI configuration cycles look like this:
139 *
140 * Type 0:
141 *
142 * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
143 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
144 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
145 * | | |D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|0|
146 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
147 *
148 * 31:11 Device select bit.
149 * 10:8 Function number
150 * 7:2 Register number
151 *
152 * Type 1:
153 *
154 * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
155 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
156 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
157 * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1|
158 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
159 *
160 * 31:24 reserved
161 * 23:16 bus number (8 bits = 128 possible buses)
162 * 15:11 Device number (5 bits)
163 * 10:8 function number
164 * 7:2 register number
165 *
166 */
167static DEFINE_SPINLOCK(v3_lock);
168
169#define PCI_BUS_NONMEM_START 0x00000000
170#define PCI_BUS_NONMEM_SIZE SZ_256M
171
172#define PCI_BUS_PREMEM_START PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE
173#define PCI_BUS_PREMEM_SIZE SZ_256M
174
175#if PCI_BUS_NONMEM_START & 0x000fffff
176#error PCI_BUS_NONMEM_START must be megabyte aligned
177#endif
178#if PCI_BUS_PREMEM_START & 0x000fffff
179#error PCI_BUS_PREMEM_START must be megabyte aligned
180#endif
181
182#undef V3_LB_BASE_PREFETCH
183#define V3_LB_BASE_PREFETCH 0
184
185static unsigned long v3_open_config_window(struct pci_bus *bus,
186 unsigned int devfn, int offset)
187{
188 unsigned int address, mapaddress, busnr;
189
190 busnr = bus->number;
191
192 /*
193 * Trap out illegal values
194 */
195 if (offset > 255)
196 BUG();
197 if (busnr > 255)
198 BUG();
199 if (devfn > 255)
200 BUG();
201
202 if (busnr == 0) {
203 int slot = PCI_SLOT(devfn);
204
205 /*
206 * local bus segment so need a type 0 config cycle
207 *
208 * build the PCI configuration "address" with one-hot in
209 * A31-A11
210 *
211 * mapaddress:
212 * 3:1 = config cycle (101)
213 * 0 = PCI A1 & A0 are 0 (0)
214 */
215 address = PCI_FUNC(devfn) << 8;
216 mapaddress = V3_LB_MAP_TYPE_CONFIG;
217
218 if (slot > 12)
219 /*
220 * high order bits are handled by the MAP register
221 */
222 mapaddress |= 1 << (slot - 5);
223 else
224 /*
225 * low order bits handled directly in the address
226 */
227 address |= 1 << (slot + 11);
228 } else {
229 /*
230 * not the local bus segment so need a type 1 config cycle
231 *
232 * address:
233 * 23:16 = bus number
234 * 15:11 = slot number (7:3 of devfn)
235 * 10:8 = func number (2:0 of devfn)
236 *
237 * mapaddress:
238 * 3:1 = config cycle (101)
239 * 0 = PCI A1 & A0 from host bus (1)
240 */
241 mapaddress = V3_LB_MAP_TYPE_CONFIG | V3_LB_MAP_AD_LOW_EN;
242 address = (busnr << 16) | (devfn << 8);
243 }
244
245 /*
246 * Set up base0 to see all 512Mbytes of memory space (not
247 * prefetchable), this frees up base1 for re-use by
248 * configuration memory
249 */
250 v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
251 V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE);
252
253 /*
254 * Set up base1/map1 to point into configuration space.
255 */
256 v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_CONFIG_BASE) |
257 V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE);
258 v3_writew(V3_LB_MAP1, mapaddress);
259
260 return PCI_CONFIG_VADDR + address + offset;
261}
262
263static void v3_close_config_window(void)
264{
265 /*
266 * Reassign base1 for use by prefetchable PCI memory
267 */
268 v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) |
269 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
270 V3_LB_BASE_ENABLE);
271 v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) |
272 V3_LB_MAP_TYPE_MEM_MULTIPLE);
273
274 /*
275 * And shrink base0 back to a 256M window (NOTE: MAP0 already correct)
276 */
277 v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
278 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
279}
280
281static int v3_read_config(struct pci_bus *bus, unsigned int devfn, int where,
282 int size, u32 *val)
283{
284 unsigned long addr;
285 unsigned long flags;
286 u32 v;
287
288 spin_lock_irqsave(&v3_lock, flags);
289 addr = v3_open_config_window(bus, devfn, where);
290
291 switch (size) {
292 case 1:
293 v = __raw_readb(addr);
294 break;
295
296 case 2:
297 v = __raw_readw(addr);
298 break;
299
300 default:
301 v = __raw_readl(addr);
302 break;
303 }
304
305 v3_close_config_window();
306 spin_unlock_irqrestore(&v3_lock, flags);
307
308 *val = v;
309 return PCIBIOS_SUCCESSFUL;
310}
311
312static int v3_write_config(struct pci_bus *bus, unsigned int devfn, int where,
313 int size, u32 val)
314{
315 unsigned long addr;
316 unsigned long flags;
317
318 spin_lock_irqsave(&v3_lock, flags);
319 addr = v3_open_config_window(bus, devfn, where);
320
321 switch (size) {
322 case 1:
323 __raw_writeb((u8)val, addr);
324 __raw_readb(addr);
325 break;
326
327 case 2:
328 __raw_writew((u16)val, addr);
329 __raw_readw(addr);
330 break;
331
332 case 4:
333 __raw_writel(val, addr);
334 __raw_readl(addr);
335 break;
336 }
337
338 v3_close_config_window();
339 spin_unlock_irqrestore(&v3_lock, flags);
340
341 return PCIBIOS_SUCCESSFUL;
342}
343
344static struct pci_ops pci_v3_ops = {
345 .read = v3_read_config,
346 .write = v3_write_config,
347};
348
349static struct resource non_mem = {
350 .name = "PCI non-prefetchable",
351 .start = PHYS_PCI_MEM_BASE + PCI_BUS_NONMEM_START,
352 .end = PHYS_PCI_MEM_BASE + PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE - 1,
353 .flags = IORESOURCE_MEM,
354};
355
356static struct resource pre_mem = {
357 .name = "PCI prefetchable",
358 .start = PHYS_PCI_MEM_BASE + PCI_BUS_PREMEM_START,
359 .end = PHYS_PCI_MEM_BASE + PCI_BUS_PREMEM_START + PCI_BUS_PREMEM_SIZE - 1,
360 .flags = IORESOURCE_MEM | IORESOURCE_PREFETCH,
361};
362
363static int __init pci_v3_setup_resources(struct resource **resource)
364{
365 if (request_resource(&iomem_resource, &non_mem)) {
366 printk(KERN_ERR "PCI: unable to allocate non-prefetchable "
367 "memory region\n");
368 return -EBUSY;
369 }
370 if (request_resource(&iomem_resource, &pre_mem)) {
371 release_resource(&non_mem);
372 printk(KERN_ERR "PCI: unable to allocate prefetchable "
373 "memory region\n");
374 return -EBUSY;
375 }
376
377 /*
378 * bus->resource[0] is the IO resource for this bus
379 * bus->resource[1] is the mem resource for this bus
380 * bus->resource[2] is the prefetch mem resource for this bus
381 */
382 resource[0] = &ioport_resource;
383 resource[1] = &non_mem;
384 resource[2] = &pre_mem;
385
386 return 1;
387}
388
389/*
390 * These don't seem to be implemented on the Integrator I have, which
391 * means I can't get additional information on the reason for the pm2fb
392 * problems. I suppose I'll just have to mind-meld with the machine. ;)
393 */
b830b9b5
RK		 394#define SC_PCI IO_ADDRESS(INTEGRATOR_SC_PCIENABLE)
395#define SC_LBFADDR IO_ADDRESS(INTEGRATOR_SC_BASE + 0x20)
396#define SC_LBFCODE IO_ADDRESS(INTEGRATOR_SC_BASE + 0x24)
1da177e4
LT		 397
398static int
399v3_pci_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
400{
401 unsigned long pc = instruction_pointer(regs);
402 unsigned long instr = *(unsigned long *)pc;
403#if 0
404 char buf[128];
405
406 sprintf(buf, "V3 fault: addr 0x%08lx, FSR 0x%03x, PC 0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x ISTAT=%02x\n",
407 addr, fsr, pc, instr, __raw_readl(SC_LBFADDR), __raw_readl(SC_LBFCODE) & 255,
408 v3_readb(V3_LB_ISTAT));
409 printk(KERN_DEBUG "%s", buf);
1da177e4
LT		 410#endif
411
412 v3_writeb(V3_LB_ISTAT, 0);
413 __raw_writel(3, SC_PCI);
414
415 /*
416 * If the instruction being executed was a read,
417 * make it look like it read all-ones.
418 */
419 if ((instr & 0x0c100000) == 0x04100000) {
420 int reg = (instr >> 12) & 15;
421 unsigned long val;
422
423 if (instr & 0x00400000)
424 val = 255;
425 else
426 val = -1;
427
428 regs->uregs[reg] = val;
429 regs->ARM_pc += 4;
430 return 0;
431 }
432
433 if ((instr & 0x0e100090) == 0x00100090) {
434 int reg = (instr >> 12) & 15;
435
436 regs->uregs[reg] = -1;
437 regs->ARM_pc += 4;
438 return 0;
439 }
440
441 return 1;
442}
443
e8f2af17 444static irqreturn_t v3_irq(int dummy, void *devid)
1da177e4
LT		 445{
446#ifdef CONFIG_DEBUG_LL
0cd61b68 447 struct pt_regs *regs = get_irq_regs();
1da177e4
LT		 448 unsigned long pc = instruction_pointer(regs);
449 unsigned long instr = *(unsigned long *)pc;
450 char buf[128];
7c28472a 451 extern void printascii(const char *);
1da177e4 452
e8f2af17
JG		 453 sprintf(buf, "V3 int %d: pc=0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x "
454 "ISTAT=%02x\n", IRQ_AP_V3INT, pc, instr,
455 __raw_readl(SC_LBFADDR),
456 __raw_readl(SC_LBFCODE) & 255,
1da177e4
LT		 457 v3_readb(V3_LB_ISTAT));
458 printascii(buf);
459#endif
460
461 v3_writew(V3_PCI_STAT, 0xf000);
462 v3_writeb(V3_LB_ISTAT, 0);
463 __raw_writel(3, SC_PCI);
464
465#ifdef CONFIG_DEBUG_LL
466 /*
467 * If the instruction being executed was a read,
468 * make it look like it read all-ones.
469 */
470 if ((instr & 0x0c100000) == 0x04100000) {
471 int reg = (instr >> 16) & 15;
472 sprintf(buf, " reg%d = %08lx\n", reg, regs->uregs[reg]);
473 printascii(buf);
474 }
475#endif
476 return IRQ_HANDLED;
477}
478
479int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
480{
481 int ret = 0;
482
483 if (nr == 0) {
484 sys->mem_offset = PHYS_PCI_MEM_BASE;
485 ret = pci_v3_setup_resources(sys->resource);
486 }
487
488 return ret;
489}
490
7f8b7170 491struct pci_bus * __init pci_v3_scan_bus(int nr, struct pci_sys_data *sys)
1da177e4
LT		 492{
493 return pci_scan_bus(sys->busnr, &pci_v3_ops, sys);
494}
495
496/*
497 * V3_LB_BASE? - local bus address
498 * V3_LB_MAP? - pci bus address
499 */
500void __init pci_v3_preinit(void)
501{
502 unsigned long flags;
503 unsigned int temp;
504 int ret;
505
c9d95fbe
RH		 506 pcibios_min_io = 0x6000;
507 pcibios_min_mem = 0x00100000;
cc22b4c1 508 vga_base = PCI_MEMORY_VADDR;
c9d95fbe 509
1da177e4
LT		 510 /*
511 * Hook in our fault handler for PCI errors
512 */
6338a6aa
KS		 513 hook_fault_code(4, v3_pci_fault, SIGBUS, 0, "external abort on linefetch");
514 hook_fault_code(6, v3_pci_fault, SIGBUS, 0, "external abort on linefetch");
515 hook_fault_code(8, v3_pci_fault, SIGBUS, 0, "external abort on non-linefetch");
516 hook_fault_code(10, v3_pci_fault, SIGBUS, 0, "external abort on non-linefetch");
1da177e4
LT		 517
518 spin_lock_irqsave(&v3_lock, flags);
519
520 /*
521 * Unlock V3 registers, but only if they were previously locked.
522 */
523 if (v3_readw(V3_SYSTEM) & V3_SYSTEM_M_LOCK)
524 v3_writew(V3_SYSTEM, 0xa05f);
525
526 /*
527 * Setup window 0 - PCI non-prefetchable memory
528 * Local: 0x40000000 Bus: 0x00000000 Size: 256MB
529 */
530 v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
531 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
532 v3_writew(V3_LB_MAP0, v3_addr_to_lb_map(PCI_BUS_NONMEM_START) |
533 V3_LB_MAP_TYPE_MEM);
534
535 /*
536 * Setup window 1 - PCI prefetchable memory
537 * Local: 0x50000000 Bus: 0x10000000 Size: 256MB
538 */
539 v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) |
540 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
541 V3_LB_BASE_ENABLE);
542 v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) |
543 V3_LB_MAP_TYPE_MEM_MULTIPLE);
544
545 /*
546 * Setup window 2 - PCI IO
547 */
548 v3_writel(V3_LB_BASE2, v3_addr_to_lb_base2(PHYS_PCI_IO_BASE) |
549 V3_LB_BASE_ENABLE);
550 v3_writew(V3_LB_MAP2, v3_addr_to_lb_map2(0));
551
552 /*
553 * Disable PCI to host IO cycles
554 */
555 temp = v3_readw(V3_PCI_CFG) & ~V3_PCI_CFG_M_I2O_EN;
556 temp |= V3_PCI_CFG_M_IO_REG_DIS | V3_PCI_CFG_M_IO_DIS;
557 v3_writew(V3_PCI_CFG, temp);
558
559 printk(KERN_DEBUG "FIFO_CFG: %04x FIFO_PRIO: %04x\n",
560 v3_readw(V3_FIFO_CFG), v3_readw(V3_FIFO_PRIORITY));
561
562 /*
563 * Set the V3 FIFO such that writes have higher priority than
564 * reads, and local bus write causes local bus read fifo flush.
565 * Same for PCI.
566 */
567 v3_writew(V3_FIFO_PRIORITY, 0x0a0a);
568
569 /*
570 * Re-lock the system register.
571 */
572 temp = v3_readw(V3_SYSTEM) | V3_SYSTEM_M_LOCK;
573 v3_writew(V3_SYSTEM, temp);
574
575 /*
576 * Clear any error conditions, and enable write errors.
577 */
578 v3_writeb(V3_LB_ISTAT, 0);
579 v3_writew(V3_LB_CFG, v3_readw(V3_LB_CFG) | (1 << 10));
580 v3_writeb(V3_LB_IMASK, 0x28);
581 __raw_writel(3, SC_PCI);
582
583 /*
584 * Grab the PCI error interrupt.
585 */
586 ret = request_irq(IRQ_AP_V3INT, v3_irq, 0, "V3", NULL);
587 if (ret)
588 printk(KERN_ERR "PCI: unable to grab PCI error "
589 "interrupt: %d\n", ret);
590
591 spin_unlock_irqrestore(&v3_lock, flags);
592}
593
594void __init pci_v3_postinit(void)
595{
596 unsigned int pci_cmd;
597
598 pci_cmd = PCI_COMMAND_MEMORY |
599 PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
600
601 v3_writew(V3_PCI_CMD, pci_cmd);
602
603 v3_writeb(V3_LB_ISTAT, ~0x40);
604 v3_writeb(V3_LB_IMASK, 0x68);
605
606#if 0
607 ret = request_irq(IRQ_AP_LBUSTIMEOUT, lb_timeout, 0, "bus timeout", NULL);
608 if (ret)
609 printk(KERN_ERR "PCI: unable to grab local bus timeout "
610 "interrupt: %d\n", ret);
611#endif
863dab45
RK		 612
613 register_isa_ports(PHYS_PCI_MEM_BASE, PHYS_PCI_IO_BASE, 0);
1da177e4 614}
Linux kernel - Deliverables
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