Commit | Line | Data |
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285f5fa7 DW |
1 | /* |
2 | * iop13xx platform Initialization | |
3 | * Copyright (c) 2005-2006, Intel Corporation. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., 59 Temple | |
16 | * Place - Suite 330, Boston, MA 02111-1307 USA. | |
17 | * | |
18 | */ | |
19 | ||
b7f080cf | 20 | #include <linux/dma-mapping.h> |
285f5fa7 | 21 | #include <linux/serial_8250.h> |
fced80c7 | 22 | #include <linux/io.h> |
285f5fa7 DW |
23 | #ifdef CONFIG_MTD_PHYSMAP |
24 | #include <linux/mtd/physmap.h> | |
25 | #endif | |
26 | #include <asm/mach/map.h> | |
a09e64fb | 27 | #include <mach/hardware.h> |
285f5fa7 | 28 | #include <asm/irq.h> |
39a8d7d1 | 29 | #include <asm/hardware/iop_adma.h> |
285f5fa7 DW |
30 | |
31 | #define IOP13XX_UART_XTAL 33334000 | |
32 | #define IOP13XX_SETUP_DEBUG 0 | |
33 | #define PRINTK(x...) ((void)(IOP13XX_SETUP_DEBUG && printk(x))) | |
34 | ||
35 | /* Standard IO mapping for all IOP13XX based systems | |
36 | */ | |
37 | static struct map_desc iop13xx_std_desc[] __initdata = { | |
38 | { /* mem mapped registers */ | |
abf2ba15 | 39 | .virtual = (unsigned long)IOP13XX_PMMR_VIRT_MEM_BASE, |
285f5fa7 DW |
40 | .pfn = __phys_to_pfn(IOP13XX_PMMR_PHYS_MEM_BASE), |
41 | .length = IOP13XX_PMMR_SIZE, | |
42 | .type = MT_DEVICE, | |
285f5fa7 DW |
43 | }, |
44 | }; | |
45 | ||
46 | static struct resource iop13xx_uart0_resources[] = { | |
47 | [0] = { | |
48 | .start = IOP13XX_UART0_PHYS, | |
49 | .end = IOP13XX_UART0_PHYS + 0x3f, | |
50 | .flags = IORESOURCE_MEM, | |
51 | }, | |
52 | [1] = { | |
53 | .start = IRQ_IOP13XX_UART0, | |
54 | .end = IRQ_IOP13XX_UART0, | |
55 | .flags = IORESOURCE_IRQ | |
56 | } | |
57 | }; | |
58 | ||
59 | static struct resource iop13xx_uart1_resources[] = { | |
60 | [0] = { | |
61 | .start = IOP13XX_UART1_PHYS, | |
62 | .end = IOP13XX_UART1_PHYS + 0x3f, | |
63 | .flags = IORESOURCE_MEM, | |
64 | }, | |
65 | [1] = { | |
66 | .start = IRQ_IOP13XX_UART1, | |
67 | .end = IRQ_IOP13XX_UART1, | |
68 | .flags = IORESOURCE_IRQ | |
69 | } | |
70 | }; | |
71 | ||
72 | static struct plat_serial8250_port iop13xx_uart0_data[] = { | |
73 | { | |
abf2ba15 AB |
74 | .membase = IOP13XX_UART0_VIRT, |
75 | .mapbase = IOP13XX_UART0_PHYS, | |
285f5fa7 DW |
76 | .irq = IRQ_IOP13XX_UART0, |
77 | .uartclk = IOP13XX_UART_XTAL, | |
78 | .regshift = 2, | |
79 | .iotype = UPIO_MEM, | |
80 | .flags = UPF_SKIP_TEST, | |
81 | }, | |
82 | { }, | |
83 | }; | |
84 | ||
85 | static struct plat_serial8250_port iop13xx_uart1_data[] = { | |
86 | { | |
abf2ba15 AB |
87 | .membase = IOP13XX_UART1_VIRT, |
88 | .mapbase = IOP13XX_UART1_PHYS, | |
285f5fa7 DW |
89 | .irq = IRQ_IOP13XX_UART1, |
90 | .uartclk = IOP13XX_UART_XTAL, | |
91 | .regshift = 2, | |
92 | .iotype = UPIO_MEM, | |
93 | .flags = UPF_SKIP_TEST, | |
94 | }, | |
95 | { }, | |
96 | }; | |
97 | ||
98 | /* The ids are fixed up later in iop13xx_platform_init */ | |
99 | static struct platform_device iop13xx_uart0 = { | |
100 | .name = "serial8250", | |
101 | .id = 0, | |
102 | .dev.platform_data = iop13xx_uart0_data, | |
103 | .num_resources = 2, | |
104 | .resource = iop13xx_uart0_resources, | |
105 | }; | |
106 | ||
107 | static struct platform_device iop13xx_uart1 = { | |
108 | .name = "serial8250", | |
109 | .id = 0, | |
110 | .dev.platform_data = iop13xx_uart1_data, | |
111 | .num_resources = 2, | |
112 | .resource = iop13xx_uart1_resources | |
113 | }; | |
114 | ||
115 | static struct resource iop13xx_i2c_0_resources[] = { | |
116 | [0] = { | |
117 | .start = IOP13XX_I2C0_PHYS, | |
118 | .end = IOP13XX_I2C0_PHYS + 0x18, | |
119 | .flags = IORESOURCE_MEM, | |
120 | }, | |
121 | [1] = { | |
122 | .start = IRQ_IOP13XX_I2C_0, | |
123 | .end = IRQ_IOP13XX_I2C_0, | |
124 | .flags = IORESOURCE_IRQ | |
125 | } | |
126 | }; | |
127 | ||
128 | static struct resource iop13xx_i2c_1_resources[] = { | |
129 | [0] = { | |
130 | .start = IOP13XX_I2C1_PHYS, | |
131 | .end = IOP13XX_I2C1_PHYS + 0x18, | |
132 | .flags = IORESOURCE_MEM, | |
133 | }, | |
134 | [1] = { | |
135 | .start = IRQ_IOP13XX_I2C_1, | |
136 | .end = IRQ_IOP13XX_I2C_1, | |
137 | .flags = IORESOURCE_IRQ | |
138 | } | |
139 | }; | |
140 | ||
141 | static struct resource iop13xx_i2c_2_resources[] = { | |
142 | [0] = { | |
143 | .start = IOP13XX_I2C2_PHYS, | |
144 | .end = IOP13XX_I2C2_PHYS + 0x18, | |
145 | .flags = IORESOURCE_MEM, | |
146 | }, | |
147 | [1] = { | |
148 | .start = IRQ_IOP13XX_I2C_2, | |
149 | .end = IRQ_IOP13XX_I2C_2, | |
150 | .flags = IORESOURCE_IRQ | |
151 | } | |
152 | }; | |
153 | ||
154 | /* I2C controllers. The IOP13XX uses the same block as the IOP3xx, so | |
155 | * we just use the same device name. | |
156 | */ | |
157 | ||
158 | /* The ids are fixed up later in iop13xx_platform_init */ | |
159 | static struct platform_device iop13xx_i2c_0_controller = { | |
160 | .name = "IOP3xx-I2C", | |
161 | .id = 0, | |
162 | .num_resources = 2, | |
163 | .resource = iop13xx_i2c_0_resources | |
164 | }; | |
165 | ||
166 | static struct platform_device iop13xx_i2c_1_controller = { | |
167 | .name = "IOP3xx-I2C", | |
168 | .id = 0, | |
169 | .num_resources = 2, | |
170 | .resource = iop13xx_i2c_1_resources | |
171 | }; | |
172 | ||
173 | static struct platform_device iop13xx_i2c_2_controller = { | |
174 | .name = "IOP3xx-I2C", | |
175 | .id = 0, | |
176 | .num_resources = 2, | |
177 | .resource = iop13xx_i2c_2_resources | |
178 | }; | |
179 | ||
180 | #ifdef CONFIG_MTD_PHYSMAP | |
181 | /* PBI Flash Device | |
182 | */ | |
183 | static struct physmap_flash_data iq8134x_flash_data = { | |
184 | .width = 2, | |
185 | }; | |
186 | ||
187 | static struct resource iq8134x_flash_resource = { | |
188 | .start = IQ81340_FLASHBASE, | |
189 | .end = 0, | |
190 | .flags = IORESOURCE_MEM, | |
191 | }; | |
192 | ||
193 | static struct platform_device iq8134x_flash = { | |
194 | .name = "physmap-flash", | |
195 | .id = 0, | |
196 | .dev = { .platform_data = &iq8134x_flash_data, }, | |
197 | .num_resources = 1, | |
198 | .resource = &iq8134x_flash_resource, | |
199 | }; | |
200 | ||
201 | static unsigned long iq8134x_probe_flash_size(void) | |
202 | { | |
203 | uint8_t __iomem *flash_addr = ioremap(IQ81340_FLASHBASE, PAGE_SIZE); | |
204 | int i; | |
205 | char query[3]; | |
206 | unsigned long size = 0; | |
207 | int width = iq8134x_flash_data.width; | |
208 | ||
209 | if (flash_addr) { | |
210 | /* send CFI 'query' command */ | |
211 | writew(0x98, flash_addr); | |
212 | ||
213 | /* check for CFI compliance */ | |
214 | for (i = 0; i < 3 * width; i += width) | |
215 | query[i / width] = readb(flash_addr + (0x10 * width) + i); | |
216 | ||
217 | /* read the size */ | |
218 | if (memcmp(query, "QRY", 3) == 0) | |
219 | size = 1 << readb(flash_addr + (0x27 * width)); | |
220 | ||
221 | /* send CFI 'read array' command */ | |
222 | writew(0xff, flash_addr); | |
223 | ||
224 | iounmap(flash_addr); | |
225 | } | |
226 | ||
227 | return size; | |
228 | } | |
229 | #endif | |
230 | ||
39a8d7d1 DW |
231 | /* ADMA Channels */ |
232 | static struct resource iop13xx_adma_0_resources[] = { | |
233 | [0] = { | |
234 | .start = IOP13XX_ADMA_PHYS_BASE(0), | |
235 | .end = IOP13XX_ADMA_UPPER_PA(0), | |
236 | .flags = IORESOURCE_MEM, | |
237 | }, | |
238 | [1] = { | |
239 | .start = IRQ_IOP13XX_ADMA0_EOT, | |
240 | .end = IRQ_IOP13XX_ADMA0_EOT, | |
241 | .flags = IORESOURCE_IRQ | |
242 | }, | |
243 | [2] = { | |
244 | .start = IRQ_IOP13XX_ADMA0_EOC, | |
245 | .end = IRQ_IOP13XX_ADMA0_EOC, | |
246 | .flags = IORESOURCE_IRQ | |
247 | }, | |
248 | [3] = { | |
249 | .start = IRQ_IOP13XX_ADMA0_ERR, | |
250 | .end = IRQ_IOP13XX_ADMA0_ERR, | |
251 | .flags = IORESOURCE_IRQ | |
252 | } | |
253 | }; | |
254 | ||
255 | static struct resource iop13xx_adma_1_resources[] = { | |
256 | [0] = { | |
257 | .start = IOP13XX_ADMA_PHYS_BASE(1), | |
258 | .end = IOP13XX_ADMA_UPPER_PA(1), | |
259 | .flags = IORESOURCE_MEM, | |
260 | }, | |
261 | [1] = { | |
262 | .start = IRQ_IOP13XX_ADMA1_EOT, | |
263 | .end = IRQ_IOP13XX_ADMA1_EOT, | |
264 | .flags = IORESOURCE_IRQ | |
265 | }, | |
266 | [2] = { | |
267 | .start = IRQ_IOP13XX_ADMA1_EOC, | |
268 | .end = IRQ_IOP13XX_ADMA1_EOC, | |
269 | .flags = IORESOURCE_IRQ | |
270 | }, | |
271 | [3] = { | |
272 | .start = IRQ_IOP13XX_ADMA1_ERR, | |
273 | .end = IRQ_IOP13XX_ADMA1_ERR, | |
274 | .flags = IORESOURCE_IRQ | |
275 | } | |
276 | }; | |
277 | ||
278 | static struct resource iop13xx_adma_2_resources[] = { | |
279 | [0] = { | |
280 | .start = IOP13XX_ADMA_PHYS_BASE(2), | |
281 | .end = IOP13XX_ADMA_UPPER_PA(2), | |
282 | .flags = IORESOURCE_MEM, | |
283 | }, | |
284 | [1] = { | |
285 | .start = IRQ_IOP13XX_ADMA2_EOT, | |
286 | .end = IRQ_IOP13XX_ADMA2_EOT, | |
287 | .flags = IORESOURCE_IRQ | |
288 | }, | |
289 | [2] = { | |
290 | .start = IRQ_IOP13XX_ADMA2_EOC, | |
291 | .end = IRQ_IOP13XX_ADMA2_EOC, | |
292 | .flags = IORESOURCE_IRQ | |
293 | }, | |
294 | [3] = { | |
295 | .start = IRQ_IOP13XX_ADMA2_ERR, | |
296 | .end = IRQ_IOP13XX_ADMA2_ERR, | |
297 | .flags = IORESOURCE_IRQ | |
298 | } | |
299 | }; | |
300 | ||
6a35528a | 301 | static u64 iop13xx_adma_dmamask = DMA_BIT_MASK(64); |
39a8d7d1 DW |
302 | static struct iop_adma_platform_data iop13xx_adma_0_data = { |
303 | .hw_id = 0, | |
304 | .pool_size = PAGE_SIZE, | |
305 | }; | |
306 | ||
307 | static struct iop_adma_platform_data iop13xx_adma_1_data = { | |
308 | .hw_id = 1, | |
309 | .pool_size = PAGE_SIZE, | |
310 | }; | |
311 | ||
312 | static struct iop_adma_platform_data iop13xx_adma_2_data = { | |
313 | .hw_id = 2, | |
314 | .pool_size = PAGE_SIZE, | |
315 | }; | |
316 | ||
317 | /* The ids are fixed up later in iop13xx_platform_init */ | |
318 | static struct platform_device iop13xx_adma_0_channel = { | |
319 | .name = "iop-adma", | |
320 | .id = 0, | |
321 | .num_resources = 4, | |
322 | .resource = iop13xx_adma_0_resources, | |
323 | .dev = { | |
324 | .dma_mask = &iop13xx_adma_dmamask, | |
6a35528a | 325 | .coherent_dma_mask = DMA_BIT_MASK(64), |
39a8d7d1 DW |
326 | .platform_data = (void *) &iop13xx_adma_0_data, |
327 | }, | |
328 | }; | |
329 | ||
330 | static struct platform_device iop13xx_adma_1_channel = { | |
331 | .name = "iop-adma", | |
332 | .id = 0, | |
333 | .num_resources = 4, | |
334 | .resource = iop13xx_adma_1_resources, | |
335 | .dev = { | |
336 | .dma_mask = &iop13xx_adma_dmamask, | |
6a35528a | 337 | .coherent_dma_mask = DMA_BIT_MASK(64), |
39a8d7d1 DW |
338 | .platform_data = (void *) &iop13xx_adma_1_data, |
339 | }, | |
340 | }; | |
341 | ||
342 | static struct platform_device iop13xx_adma_2_channel = { | |
343 | .name = "iop-adma", | |
344 | .id = 0, | |
345 | .num_resources = 4, | |
346 | .resource = iop13xx_adma_2_resources, | |
347 | .dev = { | |
348 | .dma_mask = &iop13xx_adma_dmamask, | |
6a35528a | 349 | .coherent_dma_mask = DMA_BIT_MASK(64), |
39a8d7d1 DW |
350 | .platform_data = (void *) &iop13xx_adma_2_data, |
351 | }, | |
352 | }; | |
353 | ||
285f5fa7 DW |
354 | void __init iop13xx_map_io(void) |
355 | { | |
356 | /* Initialize the Static Page Table maps */ | |
357 | iotable_init(iop13xx_std_desc, ARRAY_SIZE(iop13xx_std_desc)); | |
358 | } | |
359 | ||
39a8d7d1 DW |
360 | static int init_uart; |
361 | static int init_i2c; | |
362 | static int init_adma; | |
285f5fa7 DW |
363 | |
364 | void __init iop13xx_platform_init(void) | |
365 | { | |
366 | int i; | |
39a8d7d1 | 367 | u32 uart_idx, i2c_idx, adma_idx, plat_idx; |
285f5fa7 DW |
368 | struct platform_device *iop13xx_devices[IQ81340_MAX_PLAT_DEVICES]; |
369 | ||
370 | /* set the bases so we can read the device id */ | |
371 | iop13xx_set_atu_mmr_bases(); | |
372 | ||
373 | memset(iop13xx_devices, 0, sizeof(iop13xx_devices)); | |
374 | ||
375 | if (init_uart == IOP13XX_INIT_UART_DEFAULT) { | |
376 | switch (iop13xx_dev_id()) { | |
fa543f00 | 377 | /* enable both uarts on iop341 */ |
285f5fa7 DW |
378 | case 0x3380: |
379 | case 0x3384: | |
380 | case 0x3388: | |
381 | case 0x338c: | |
285f5fa7 DW |
382 | init_uart |= IOP13XX_INIT_UART_0; |
383 | init_uart |= IOP13XX_INIT_UART_1; | |
384 | break; | |
385 | /* only enable uart 1 */ | |
386 | default: | |
387 | init_uart |= IOP13XX_INIT_UART_1; | |
388 | } | |
389 | } | |
390 | ||
391 | if (init_i2c == IOP13XX_INIT_I2C_DEFAULT) { | |
392 | switch (iop13xx_dev_id()) { | |
393 | /* enable all i2c units on iop341 and iop342 */ | |
394 | case 0x3380: | |
395 | case 0x3384: | |
396 | case 0x3388: | |
397 | case 0x338c: | |
398 | case 0x3382: | |
399 | case 0x3386: | |
400 | case 0x338a: | |
401 | case 0x338e: | |
402 | init_i2c |= IOP13XX_INIT_I2C_0; | |
403 | init_i2c |= IOP13XX_INIT_I2C_1; | |
404 | init_i2c |= IOP13XX_INIT_I2C_2; | |
405 | break; | |
406 | /* only enable i2c 1 and 2 */ | |
407 | default: | |
408 | init_i2c |= IOP13XX_INIT_I2C_1; | |
409 | init_i2c |= IOP13XX_INIT_I2C_2; | |
410 | } | |
411 | } | |
412 | ||
39a8d7d1 DW |
413 | if (init_adma == IOP13XX_INIT_ADMA_DEFAULT) { |
414 | init_adma |= IOP13XX_INIT_ADMA_0; | |
415 | init_adma |= IOP13XX_INIT_ADMA_1; | |
416 | init_adma |= IOP13XX_INIT_ADMA_2; | |
417 | } | |
418 | ||
285f5fa7 DW |
419 | plat_idx = 0; |
420 | uart_idx = 0; | |
421 | i2c_idx = 0; | |
422 | ||
423 | /* uart 1 (if enabled) is ttyS0 */ | |
424 | if (init_uart & IOP13XX_INIT_UART_1) { | |
425 | PRINTK("Adding uart1 to platform device list\n"); | |
426 | iop13xx_uart1.id = uart_idx++; | |
427 | iop13xx_devices[plat_idx++] = &iop13xx_uart1; | |
428 | } | |
429 | if (init_uart & IOP13XX_INIT_UART_0) { | |
430 | PRINTK("Adding uart0 to platform device list\n"); | |
431 | iop13xx_uart0.id = uart_idx++; | |
432 | iop13xx_devices[plat_idx++] = &iop13xx_uart0; | |
433 | } | |
434 | ||
435 | for(i = 0; i < IQ81340_NUM_I2C; i++) { | |
436 | if ((init_i2c & (1 << i)) && IOP13XX_SETUP_DEBUG) | |
437 | printk("Adding i2c%d to platform device list\n", i); | |
438 | switch(init_i2c & (1 << i)) { | |
439 | case IOP13XX_INIT_I2C_0: | |
440 | iop13xx_i2c_0_controller.id = i2c_idx++; | |
441 | iop13xx_devices[plat_idx++] = | |
442 | &iop13xx_i2c_0_controller; | |
443 | break; | |
444 | case IOP13XX_INIT_I2C_1: | |
445 | iop13xx_i2c_1_controller.id = i2c_idx++; | |
446 | iop13xx_devices[plat_idx++] = | |
447 | &iop13xx_i2c_1_controller; | |
448 | break; | |
449 | case IOP13XX_INIT_I2C_2: | |
450 | iop13xx_i2c_2_controller.id = i2c_idx++; | |
451 | iop13xx_devices[plat_idx++] = | |
452 | &iop13xx_i2c_2_controller; | |
453 | break; | |
454 | } | |
455 | } | |
456 | ||
39a8d7d1 DW |
457 | /* initialize adma channel ids and capabilities */ |
458 | adma_idx = 0; | |
459 | for (i = 0; i < IQ81340_NUM_ADMA; i++) { | |
460 | struct iop_adma_platform_data *plat_data; | |
461 | if ((init_adma & (1 << i)) && IOP13XX_SETUP_DEBUG) | |
462 | printk(KERN_INFO | |
463 | "Adding adma%d to platform device list\n", i); | |
464 | switch (init_adma & (1 << i)) { | |
465 | case IOP13XX_INIT_ADMA_0: | |
466 | iop13xx_adma_0_channel.id = adma_idx++; | |
467 | iop13xx_devices[plat_idx++] = &iop13xx_adma_0_channel; | |
468 | plat_data = &iop13xx_adma_0_data; | |
469 | dma_cap_set(DMA_MEMCPY, plat_data->cap_mask); | |
470 | dma_cap_set(DMA_XOR, plat_data->cap_mask); | |
099f53cb | 471 | dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask); |
39a8d7d1 DW |
472 | dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask); |
473 | break; | |
474 | case IOP13XX_INIT_ADMA_1: | |
475 | iop13xx_adma_1_channel.id = adma_idx++; | |
476 | iop13xx_devices[plat_idx++] = &iop13xx_adma_1_channel; | |
477 | plat_data = &iop13xx_adma_1_data; | |
478 | dma_cap_set(DMA_MEMCPY, plat_data->cap_mask); | |
479 | dma_cap_set(DMA_XOR, plat_data->cap_mask); | |
099f53cb | 480 | dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask); |
39a8d7d1 DW |
481 | dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask); |
482 | break; | |
483 | case IOP13XX_INIT_ADMA_2: | |
484 | iop13xx_adma_2_channel.id = adma_idx++; | |
485 | iop13xx_devices[plat_idx++] = &iop13xx_adma_2_channel; | |
486 | plat_data = &iop13xx_adma_2_data; | |
487 | dma_cap_set(DMA_MEMCPY, plat_data->cap_mask); | |
488 | dma_cap_set(DMA_XOR, plat_data->cap_mask); | |
099f53cb | 489 | dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask); |
39a8d7d1 | 490 | dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask); |
b2f46fd8 | 491 | dma_cap_set(DMA_PQ, plat_data->cap_mask); |
099f53cb | 492 | dma_cap_set(DMA_PQ_VAL, plat_data->cap_mask); |
39a8d7d1 DW |
493 | break; |
494 | } | |
495 | } | |
496 | ||
285f5fa7 DW |
497 | #ifdef CONFIG_MTD_PHYSMAP |
498 | iq8134x_flash_resource.end = iq8134x_flash_resource.start + | |
ab9d90db | 499 | iq8134x_probe_flash_size() - 1; |
285f5fa7 DW |
500 | if (iq8134x_flash_resource.end > iq8134x_flash_resource.start) |
501 | iop13xx_devices[plat_idx++] = &iq8134x_flash; | |
502 | else | |
8e86f427 | 503 | printk(KERN_ERR "%s: Failed to probe flash size\n", __func__); |
285f5fa7 DW |
504 | #endif |
505 | ||
506 | platform_add_devices(iop13xx_devices, plat_idx); | |
507 | } | |
508 | ||
509 | static int __init iop13xx_init_uart_setup(char *str) | |
510 | { | |
511 | if (str) { | |
512 | while (*str != '\0') { | |
513 | switch(*str) { | |
514 | case '0': | |
515 | init_uart |= IOP13XX_INIT_UART_0; | |
516 | break; | |
517 | case '1': | |
518 | init_uart |= IOP13XX_INIT_UART_1; | |
519 | break; | |
520 | case ',': | |
521 | case '=': | |
522 | break; | |
523 | default: | |
524 | PRINTK("\"iop13xx_init_uart\" malformed" | |
525 | " at character: \'%c\'", *str); | |
526 | *(str + 1) = '\0'; | |
527 | init_uart = IOP13XX_INIT_UART_DEFAULT; | |
528 | } | |
529 | str++; | |
530 | } | |
531 | } | |
532 | return 1; | |
533 | } | |
534 | ||
535 | static int __init iop13xx_init_i2c_setup(char *str) | |
536 | { | |
537 | if (str) { | |
538 | while (*str != '\0') { | |
539 | switch(*str) { | |
540 | case '0': | |
541 | init_i2c |= IOP13XX_INIT_I2C_0; | |
542 | break; | |
543 | case '1': | |
544 | init_i2c |= IOP13XX_INIT_I2C_1; | |
545 | break; | |
546 | case '2': | |
547 | init_i2c |= IOP13XX_INIT_I2C_2; | |
548 | break; | |
549 | case ',': | |
550 | case '=': | |
551 | break; | |
552 | default: | |
553 | PRINTK("\"iop13xx_init_i2c\" malformed" | |
554 | " at character: \'%c\'", *str); | |
555 | *(str + 1) = '\0'; | |
556 | init_i2c = IOP13XX_INIT_I2C_DEFAULT; | |
557 | } | |
558 | str++; | |
559 | } | |
560 | } | |
561 | return 1; | |
562 | } | |
563 | ||
39a8d7d1 DW |
564 | static int __init iop13xx_init_adma_setup(char *str) |
565 | { | |
566 | if (str) { | |
567 | while (*str != '\0') { | |
568 | switch (*str) { | |
569 | case '0': | |
570 | init_adma |= IOP13XX_INIT_ADMA_0; | |
571 | break; | |
572 | case '1': | |
573 | init_adma |= IOP13XX_INIT_ADMA_1; | |
574 | break; | |
575 | case '2': | |
576 | init_adma |= IOP13XX_INIT_ADMA_2; | |
577 | break; | |
578 | case ',': | |
579 | case '=': | |
580 | break; | |
581 | default: | |
582 | PRINTK("\"iop13xx_init_adma\" malformed" | |
583 | " at character: \'%c\'", *str); | |
584 | *(str + 1) = '\0'; | |
585 | init_adma = IOP13XX_INIT_ADMA_DEFAULT; | |
586 | } | |
587 | str++; | |
588 | } | |
589 | } | |
590 | return 1; | |
591 | } | |
592 | ||
593 | __setup("iop13xx_init_adma", iop13xx_init_adma_setup); | |
285f5fa7 DW |
594 | __setup("iop13xx_init_uart", iop13xx_init_uart_setup); |
595 | __setup("iop13xx_init_i2c", iop13xx_init_i2c_setup); | |
00aa78ee | 596 | |
7b6d864b | 597 | void iop13xx_restart(enum reboot_mode mode, const char *cmd) |
00aa78ee RK |
598 | { |
599 | /* | |
600 | * Reset the internal bus (warning both cores are reset) | |
601 | */ | |
602 | write_wdtcr(IOP_WDTCR_EN_ARM); | |
603 | write_wdtcr(IOP_WDTCR_EN); | |
604 | write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET); | |
605 | write_wdtcr(0x1000); | |
606 | } |