Commit | Line | Data |
---|---|---|
285f5fa7 DW |
1 | /* |
2 | * iop13xx platform Initialization | |
3 | * Copyright (c) 2005-2006, Intel Corporation. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., 59 Temple | |
16 | * Place - Suite 330, Boston, MA 02111-1307 USA. | |
17 | * | |
18 | */ | |
19 | ||
b7f080cf | 20 | #include <linux/dma-mapping.h> |
285f5fa7 | 21 | #include <linux/serial_8250.h> |
fced80c7 | 22 | #include <linux/io.h> |
285f5fa7 DW |
23 | #ifdef CONFIG_MTD_PHYSMAP |
24 | #include <linux/mtd/physmap.h> | |
25 | #endif | |
26 | #include <asm/mach/map.h> | |
a09e64fb | 27 | #include <mach/hardware.h> |
285f5fa7 | 28 | #include <asm/irq.h> |
39a8d7d1 | 29 | #include <asm/hardware/iop_adma.h> |
285f5fa7 DW |
30 | |
31 | #define IOP13XX_UART_XTAL 33334000 | |
32 | #define IOP13XX_SETUP_DEBUG 0 | |
33 | #define PRINTK(x...) ((void)(IOP13XX_SETUP_DEBUG && printk(x))) | |
34 | ||
35 | /* Standard IO mapping for all IOP13XX based systems | |
36 | */ | |
37 | static struct map_desc iop13xx_std_desc[] __initdata = { | |
38 | { /* mem mapped registers */ | |
39 | .virtual = IOP13XX_PMMR_VIRT_MEM_BASE, | |
40 | .pfn = __phys_to_pfn(IOP13XX_PMMR_PHYS_MEM_BASE), | |
41 | .length = IOP13XX_PMMR_SIZE, | |
42 | .type = MT_DEVICE, | |
43 | }, { /* PCIE IO space */ | |
44 | .virtual = IOP13XX_PCIE_LOWER_IO_VA, | |
45 | .pfn = __phys_to_pfn(IOP13XX_PCIE_LOWER_IO_PA), | |
46 | .length = IOP13XX_PCIX_IO_WINDOW_SIZE, | |
47 | .type = MT_DEVICE, | |
48 | }, { /* PCIX IO space */ | |
49 | .virtual = IOP13XX_PCIX_LOWER_IO_VA, | |
50 | .pfn = __phys_to_pfn(IOP13XX_PCIX_LOWER_IO_PA), | |
51 | .length = IOP13XX_PCIX_IO_WINDOW_SIZE, | |
52 | .type = MT_DEVICE, | |
53 | }, | |
54 | }; | |
55 | ||
56 | static struct resource iop13xx_uart0_resources[] = { | |
57 | [0] = { | |
58 | .start = IOP13XX_UART0_PHYS, | |
59 | .end = IOP13XX_UART0_PHYS + 0x3f, | |
60 | .flags = IORESOURCE_MEM, | |
61 | }, | |
62 | [1] = { | |
63 | .start = IRQ_IOP13XX_UART0, | |
64 | .end = IRQ_IOP13XX_UART0, | |
65 | .flags = IORESOURCE_IRQ | |
66 | } | |
67 | }; | |
68 | ||
69 | static struct resource iop13xx_uart1_resources[] = { | |
70 | [0] = { | |
71 | .start = IOP13XX_UART1_PHYS, | |
72 | .end = IOP13XX_UART1_PHYS + 0x3f, | |
73 | .flags = IORESOURCE_MEM, | |
74 | }, | |
75 | [1] = { | |
76 | .start = IRQ_IOP13XX_UART1, | |
77 | .end = IRQ_IOP13XX_UART1, | |
78 | .flags = IORESOURCE_IRQ | |
79 | } | |
80 | }; | |
81 | ||
82 | static struct plat_serial8250_port iop13xx_uart0_data[] = { | |
83 | { | |
84 | .membase = (char*)(IOP13XX_UART0_VIRT), | |
85 | .mapbase = (IOP13XX_UART0_PHYS), | |
86 | .irq = IRQ_IOP13XX_UART0, | |
87 | .uartclk = IOP13XX_UART_XTAL, | |
88 | .regshift = 2, | |
89 | .iotype = UPIO_MEM, | |
90 | .flags = UPF_SKIP_TEST, | |
91 | }, | |
92 | { }, | |
93 | }; | |
94 | ||
95 | static struct plat_serial8250_port iop13xx_uart1_data[] = { | |
96 | { | |
97 | .membase = (char*)(IOP13XX_UART1_VIRT), | |
98 | .mapbase = (IOP13XX_UART1_PHYS), | |
99 | .irq = IRQ_IOP13XX_UART1, | |
100 | .uartclk = IOP13XX_UART_XTAL, | |
101 | .regshift = 2, | |
102 | .iotype = UPIO_MEM, | |
103 | .flags = UPF_SKIP_TEST, | |
104 | }, | |
105 | { }, | |
106 | }; | |
107 | ||
108 | /* The ids are fixed up later in iop13xx_platform_init */ | |
109 | static struct platform_device iop13xx_uart0 = { | |
110 | .name = "serial8250", | |
111 | .id = 0, | |
112 | .dev.platform_data = iop13xx_uart0_data, | |
113 | .num_resources = 2, | |
114 | .resource = iop13xx_uart0_resources, | |
115 | }; | |
116 | ||
117 | static struct platform_device iop13xx_uart1 = { | |
118 | .name = "serial8250", | |
119 | .id = 0, | |
120 | .dev.platform_data = iop13xx_uart1_data, | |
121 | .num_resources = 2, | |
122 | .resource = iop13xx_uart1_resources | |
123 | }; | |
124 | ||
125 | static struct resource iop13xx_i2c_0_resources[] = { | |
126 | [0] = { | |
127 | .start = IOP13XX_I2C0_PHYS, | |
128 | .end = IOP13XX_I2C0_PHYS + 0x18, | |
129 | .flags = IORESOURCE_MEM, | |
130 | }, | |
131 | [1] = { | |
132 | .start = IRQ_IOP13XX_I2C_0, | |
133 | .end = IRQ_IOP13XX_I2C_0, | |
134 | .flags = IORESOURCE_IRQ | |
135 | } | |
136 | }; | |
137 | ||
138 | static struct resource iop13xx_i2c_1_resources[] = { | |
139 | [0] = { | |
140 | .start = IOP13XX_I2C1_PHYS, | |
141 | .end = IOP13XX_I2C1_PHYS + 0x18, | |
142 | .flags = IORESOURCE_MEM, | |
143 | }, | |
144 | [1] = { | |
145 | .start = IRQ_IOP13XX_I2C_1, | |
146 | .end = IRQ_IOP13XX_I2C_1, | |
147 | .flags = IORESOURCE_IRQ | |
148 | } | |
149 | }; | |
150 | ||
151 | static struct resource iop13xx_i2c_2_resources[] = { | |
152 | [0] = { | |
153 | .start = IOP13XX_I2C2_PHYS, | |
154 | .end = IOP13XX_I2C2_PHYS + 0x18, | |
155 | .flags = IORESOURCE_MEM, | |
156 | }, | |
157 | [1] = { | |
158 | .start = IRQ_IOP13XX_I2C_2, | |
159 | .end = IRQ_IOP13XX_I2C_2, | |
160 | .flags = IORESOURCE_IRQ | |
161 | } | |
162 | }; | |
163 | ||
164 | /* I2C controllers. The IOP13XX uses the same block as the IOP3xx, so | |
165 | * we just use the same device name. | |
166 | */ | |
167 | ||
168 | /* The ids are fixed up later in iop13xx_platform_init */ | |
169 | static struct platform_device iop13xx_i2c_0_controller = { | |
170 | .name = "IOP3xx-I2C", | |
171 | .id = 0, | |
172 | .num_resources = 2, | |
173 | .resource = iop13xx_i2c_0_resources | |
174 | }; | |
175 | ||
176 | static struct platform_device iop13xx_i2c_1_controller = { | |
177 | .name = "IOP3xx-I2C", | |
178 | .id = 0, | |
179 | .num_resources = 2, | |
180 | .resource = iop13xx_i2c_1_resources | |
181 | }; | |
182 | ||
183 | static struct platform_device iop13xx_i2c_2_controller = { | |
184 | .name = "IOP3xx-I2C", | |
185 | .id = 0, | |
186 | .num_resources = 2, | |
187 | .resource = iop13xx_i2c_2_resources | |
188 | }; | |
189 | ||
190 | #ifdef CONFIG_MTD_PHYSMAP | |
191 | /* PBI Flash Device | |
192 | */ | |
193 | static struct physmap_flash_data iq8134x_flash_data = { | |
194 | .width = 2, | |
195 | }; | |
196 | ||
197 | static struct resource iq8134x_flash_resource = { | |
198 | .start = IQ81340_FLASHBASE, | |
199 | .end = 0, | |
200 | .flags = IORESOURCE_MEM, | |
201 | }; | |
202 | ||
203 | static struct platform_device iq8134x_flash = { | |
204 | .name = "physmap-flash", | |
205 | .id = 0, | |
206 | .dev = { .platform_data = &iq8134x_flash_data, }, | |
207 | .num_resources = 1, | |
208 | .resource = &iq8134x_flash_resource, | |
209 | }; | |
210 | ||
211 | static unsigned long iq8134x_probe_flash_size(void) | |
212 | { | |
213 | uint8_t __iomem *flash_addr = ioremap(IQ81340_FLASHBASE, PAGE_SIZE); | |
214 | int i; | |
215 | char query[3]; | |
216 | unsigned long size = 0; | |
217 | int width = iq8134x_flash_data.width; | |
218 | ||
219 | if (flash_addr) { | |
220 | /* send CFI 'query' command */ | |
221 | writew(0x98, flash_addr); | |
222 | ||
223 | /* check for CFI compliance */ | |
224 | for (i = 0; i < 3 * width; i += width) | |
225 | query[i / width] = readb(flash_addr + (0x10 * width) + i); | |
226 | ||
227 | /* read the size */ | |
228 | if (memcmp(query, "QRY", 3) == 0) | |
229 | size = 1 << readb(flash_addr + (0x27 * width)); | |
230 | ||
231 | /* send CFI 'read array' command */ | |
232 | writew(0xff, flash_addr); | |
233 | ||
234 | iounmap(flash_addr); | |
235 | } | |
236 | ||
237 | return size; | |
238 | } | |
239 | #endif | |
240 | ||
39a8d7d1 DW |
241 | /* ADMA Channels */ |
242 | static struct resource iop13xx_adma_0_resources[] = { | |
243 | [0] = { | |
244 | .start = IOP13XX_ADMA_PHYS_BASE(0), | |
245 | .end = IOP13XX_ADMA_UPPER_PA(0), | |
246 | .flags = IORESOURCE_MEM, | |
247 | }, | |
248 | [1] = { | |
249 | .start = IRQ_IOP13XX_ADMA0_EOT, | |
250 | .end = IRQ_IOP13XX_ADMA0_EOT, | |
251 | .flags = IORESOURCE_IRQ | |
252 | }, | |
253 | [2] = { | |
254 | .start = IRQ_IOP13XX_ADMA0_EOC, | |
255 | .end = IRQ_IOP13XX_ADMA0_EOC, | |
256 | .flags = IORESOURCE_IRQ | |
257 | }, | |
258 | [3] = { | |
259 | .start = IRQ_IOP13XX_ADMA0_ERR, | |
260 | .end = IRQ_IOP13XX_ADMA0_ERR, | |
261 | .flags = IORESOURCE_IRQ | |
262 | } | |
263 | }; | |
264 | ||
265 | static struct resource iop13xx_adma_1_resources[] = { | |
266 | [0] = { | |
267 | .start = IOP13XX_ADMA_PHYS_BASE(1), | |
268 | .end = IOP13XX_ADMA_UPPER_PA(1), | |
269 | .flags = IORESOURCE_MEM, | |
270 | }, | |
271 | [1] = { | |
272 | .start = IRQ_IOP13XX_ADMA1_EOT, | |
273 | .end = IRQ_IOP13XX_ADMA1_EOT, | |
274 | .flags = IORESOURCE_IRQ | |
275 | }, | |
276 | [2] = { | |
277 | .start = IRQ_IOP13XX_ADMA1_EOC, | |
278 | .end = IRQ_IOP13XX_ADMA1_EOC, | |
279 | .flags = IORESOURCE_IRQ | |
280 | }, | |
281 | [3] = { | |
282 | .start = IRQ_IOP13XX_ADMA1_ERR, | |
283 | .end = IRQ_IOP13XX_ADMA1_ERR, | |
284 | .flags = IORESOURCE_IRQ | |
285 | } | |
286 | }; | |
287 | ||
288 | static struct resource iop13xx_adma_2_resources[] = { | |
289 | [0] = { | |
290 | .start = IOP13XX_ADMA_PHYS_BASE(2), | |
291 | .end = IOP13XX_ADMA_UPPER_PA(2), | |
292 | .flags = IORESOURCE_MEM, | |
293 | }, | |
294 | [1] = { | |
295 | .start = IRQ_IOP13XX_ADMA2_EOT, | |
296 | .end = IRQ_IOP13XX_ADMA2_EOT, | |
297 | .flags = IORESOURCE_IRQ | |
298 | }, | |
299 | [2] = { | |
300 | .start = IRQ_IOP13XX_ADMA2_EOC, | |
301 | .end = IRQ_IOP13XX_ADMA2_EOC, | |
302 | .flags = IORESOURCE_IRQ | |
303 | }, | |
304 | [3] = { | |
305 | .start = IRQ_IOP13XX_ADMA2_ERR, | |
306 | .end = IRQ_IOP13XX_ADMA2_ERR, | |
307 | .flags = IORESOURCE_IRQ | |
308 | } | |
309 | }; | |
310 | ||
6a35528a | 311 | static u64 iop13xx_adma_dmamask = DMA_BIT_MASK(64); |
39a8d7d1 DW |
312 | static struct iop_adma_platform_data iop13xx_adma_0_data = { |
313 | .hw_id = 0, | |
314 | .pool_size = PAGE_SIZE, | |
315 | }; | |
316 | ||
317 | static struct iop_adma_platform_data iop13xx_adma_1_data = { | |
318 | .hw_id = 1, | |
319 | .pool_size = PAGE_SIZE, | |
320 | }; | |
321 | ||
322 | static struct iop_adma_platform_data iop13xx_adma_2_data = { | |
323 | .hw_id = 2, | |
324 | .pool_size = PAGE_SIZE, | |
325 | }; | |
326 | ||
327 | /* The ids are fixed up later in iop13xx_platform_init */ | |
328 | static struct platform_device iop13xx_adma_0_channel = { | |
329 | .name = "iop-adma", | |
330 | .id = 0, | |
331 | .num_resources = 4, | |
332 | .resource = iop13xx_adma_0_resources, | |
333 | .dev = { | |
334 | .dma_mask = &iop13xx_adma_dmamask, | |
6a35528a | 335 | .coherent_dma_mask = DMA_BIT_MASK(64), |
39a8d7d1 DW |
336 | .platform_data = (void *) &iop13xx_adma_0_data, |
337 | }, | |
338 | }; | |
339 | ||
340 | static struct platform_device iop13xx_adma_1_channel = { | |
341 | .name = "iop-adma", | |
342 | .id = 0, | |
343 | .num_resources = 4, | |
344 | .resource = iop13xx_adma_1_resources, | |
345 | .dev = { | |
346 | .dma_mask = &iop13xx_adma_dmamask, | |
6a35528a | 347 | .coherent_dma_mask = DMA_BIT_MASK(64), |
39a8d7d1 DW |
348 | .platform_data = (void *) &iop13xx_adma_1_data, |
349 | }, | |
350 | }; | |
351 | ||
352 | static struct platform_device iop13xx_adma_2_channel = { | |
353 | .name = "iop-adma", | |
354 | .id = 0, | |
355 | .num_resources = 4, | |
356 | .resource = iop13xx_adma_2_resources, | |
357 | .dev = { | |
358 | .dma_mask = &iop13xx_adma_dmamask, | |
6a35528a | 359 | .coherent_dma_mask = DMA_BIT_MASK(64), |
39a8d7d1 DW |
360 | .platform_data = (void *) &iop13xx_adma_2_data, |
361 | }, | |
362 | }; | |
363 | ||
285f5fa7 DW |
364 | void __init iop13xx_map_io(void) |
365 | { | |
366 | /* Initialize the Static Page Table maps */ | |
367 | iotable_init(iop13xx_std_desc, ARRAY_SIZE(iop13xx_std_desc)); | |
368 | } | |
369 | ||
39a8d7d1 DW |
370 | static int init_uart; |
371 | static int init_i2c; | |
372 | static int init_adma; | |
285f5fa7 DW |
373 | |
374 | void __init iop13xx_platform_init(void) | |
375 | { | |
376 | int i; | |
39a8d7d1 | 377 | u32 uart_idx, i2c_idx, adma_idx, plat_idx; |
285f5fa7 DW |
378 | struct platform_device *iop13xx_devices[IQ81340_MAX_PLAT_DEVICES]; |
379 | ||
380 | /* set the bases so we can read the device id */ | |
381 | iop13xx_set_atu_mmr_bases(); | |
382 | ||
383 | memset(iop13xx_devices, 0, sizeof(iop13xx_devices)); | |
384 | ||
385 | if (init_uart == IOP13XX_INIT_UART_DEFAULT) { | |
386 | switch (iop13xx_dev_id()) { | |
fa543f00 | 387 | /* enable both uarts on iop341 */ |
285f5fa7 DW |
388 | case 0x3380: |
389 | case 0x3384: | |
390 | case 0x3388: | |
391 | case 0x338c: | |
285f5fa7 DW |
392 | init_uart |= IOP13XX_INIT_UART_0; |
393 | init_uart |= IOP13XX_INIT_UART_1; | |
394 | break; | |
395 | /* only enable uart 1 */ | |
396 | default: | |
397 | init_uart |= IOP13XX_INIT_UART_1; | |
398 | } | |
399 | } | |
400 | ||
401 | if (init_i2c == IOP13XX_INIT_I2C_DEFAULT) { | |
402 | switch (iop13xx_dev_id()) { | |
403 | /* enable all i2c units on iop341 and iop342 */ | |
404 | case 0x3380: | |
405 | case 0x3384: | |
406 | case 0x3388: | |
407 | case 0x338c: | |
408 | case 0x3382: | |
409 | case 0x3386: | |
410 | case 0x338a: | |
411 | case 0x338e: | |
412 | init_i2c |= IOP13XX_INIT_I2C_0; | |
413 | init_i2c |= IOP13XX_INIT_I2C_1; | |
414 | init_i2c |= IOP13XX_INIT_I2C_2; | |
415 | break; | |
416 | /* only enable i2c 1 and 2 */ | |
417 | default: | |
418 | init_i2c |= IOP13XX_INIT_I2C_1; | |
419 | init_i2c |= IOP13XX_INIT_I2C_2; | |
420 | } | |
421 | } | |
422 | ||
39a8d7d1 DW |
423 | if (init_adma == IOP13XX_INIT_ADMA_DEFAULT) { |
424 | init_adma |= IOP13XX_INIT_ADMA_0; | |
425 | init_adma |= IOP13XX_INIT_ADMA_1; | |
426 | init_adma |= IOP13XX_INIT_ADMA_2; | |
427 | } | |
428 | ||
285f5fa7 DW |
429 | plat_idx = 0; |
430 | uart_idx = 0; | |
431 | i2c_idx = 0; | |
432 | ||
433 | /* uart 1 (if enabled) is ttyS0 */ | |
434 | if (init_uart & IOP13XX_INIT_UART_1) { | |
435 | PRINTK("Adding uart1 to platform device list\n"); | |
436 | iop13xx_uart1.id = uart_idx++; | |
437 | iop13xx_devices[plat_idx++] = &iop13xx_uart1; | |
438 | } | |
439 | if (init_uart & IOP13XX_INIT_UART_0) { | |
440 | PRINTK("Adding uart0 to platform device list\n"); | |
441 | iop13xx_uart0.id = uart_idx++; | |
442 | iop13xx_devices[plat_idx++] = &iop13xx_uart0; | |
443 | } | |
444 | ||
445 | for(i = 0; i < IQ81340_NUM_I2C; i++) { | |
446 | if ((init_i2c & (1 << i)) && IOP13XX_SETUP_DEBUG) | |
447 | printk("Adding i2c%d to platform device list\n", i); | |
448 | switch(init_i2c & (1 << i)) { | |
449 | case IOP13XX_INIT_I2C_0: | |
450 | iop13xx_i2c_0_controller.id = i2c_idx++; | |
451 | iop13xx_devices[plat_idx++] = | |
452 | &iop13xx_i2c_0_controller; | |
453 | break; | |
454 | case IOP13XX_INIT_I2C_1: | |
455 | iop13xx_i2c_1_controller.id = i2c_idx++; | |
456 | iop13xx_devices[plat_idx++] = | |
457 | &iop13xx_i2c_1_controller; | |
458 | break; | |
459 | case IOP13XX_INIT_I2C_2: | |
460 | iop13xx_i2c_2_controller.id = i2c_idx++; | |
461 | iop13xx_devices[plat_idx++] = | |
462 | &iop13xx_i2c_2_controller; | |
463 | break; | |
464 | } | |
465 | } | |
466 | ||
39a8d7d1 DW |
467 | /* initialize adma channel ids and capabilities */ |
468 | adma_idx = 0; | |
469 | for (i = 0; i < IQ81340_NUM_ADMA; i++) { | |
470 | struct iop_adma_platform_data *plat_data; | |
471 | if ((init_adma & (1 << i)) && IOP13XX_SETUP_DEBUG) | |
472 | printk(KERN_INFO | |
473 | "Adding adma%d to platform device list\n", i); | |
474 | switch (init_adma & (1 << i)) { | |
475 | case IOP13XX_INIT_ADMA_0: | |
476 | iop13xx_adma_0_channel.id = adma_idx++; | |
477 | iop13xx_devices[plat_idx++] = &iop13xx_adma_0_channel; | |
478 | plat_data = &iop13xx_adma_0_data; | |
479 | dma_cap_set(DMA_MEMCPY, plat_data->cap_mask); | |
480 | dma_cap_set(DMA_XOR, plat_data->cap_mask); | |
099f53cb | 481 | dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask); |
39a8d7d1 | 482 | dma_cap_set(DMA_MEMSET, plat_data->cap_mask); |
39a8d7d1 DW |
483 | dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask); |
484 | break; | |
485 | case IOP13XX_INIT_ADMA_1: | |
486 | iop13xx_adma_1_channel.id = adma_idx++; | |
487 | iop13xx_devices[plat_idx++] = &iop13xx_adma_1_channel; | |
488 | plat_data = &iop13xx_adma_1_data; | |
489 | dma_cap_set(DMA_MEMCPY, plat_data->cap_mask); | |
490 | dma_cap_set(DMA_XOR, plat_data->cap_mask); | |
099f53cb | 491 | dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask); |
39a8d7d1 | 492 | dma_cap_set(DMA_MEMSET, plat_data->cap_mask); |
39a8d7d1 DW |
493 | dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask); |
494 | break; | |
495 | case IOP13XX_INIT_ADMA_2: | |
496 | iop13xx_adma_2_channel.id = adma_idx++; | |
497 | iop13xx_devices[plat_idx++] = &iop13xx_adma_2_channel; | |
498 | plat_data = &iop13xx_adma_2_data; | |
499 | dma_cap_set(DMA_MEMCPY, plat_data->cap_mask); | |
500 | dma_cap_set(DMA_XOR, plat_data->cap_mask); | |
099f53cb | 501 | dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask); |
39a8d7d1 | 502 | dma_cap_set(DMA_MEMSET, plat_data->cap_mask); |
39a8d7d1 | 503 | dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask); |
b2f46fd8 | 504 | dma_cap_set(DMA_PQ, plat_data->cap_mask); |
099f53cb | 505 | dma_cap_set(DMA_PQ_VAL, plat_data->cap_mask); |
39a8d7d1 DW |
506 | break; |
507 | } | |
508 | } | |
509 | ||
285f5fa7 DW |
510 | #ifdef CONFIG_MTD_PHYSMAP |
511 | iq8134x_flash_resource.end = iq8134x_flash_resource.start + | |
ab9d90db | 512 | iq8134x_probe_flash_size() - 1; |
285f5fa7 DW |
513 | if (iq8134x_flash_resource.end > iq8134x_flash_resource.start) |
514 | iop13xx_devices[plat_idx++] = &iq8134x_flash; | |
515 | else | |
8e86f427 | 516 | printk(KERN_ERR "%s: Failed to probe flash size\n", __func__); |
285f5fa7 DW |
517 | #endif |
518 | ||
519 | platform_add_devices(iop13xx_devices, plat_idx); | |
520 | } | |
521 | ||
522 | static int __init iop13xx_init_uart_setup(char *str) | |
523 | { | |
524 | if (str) { | |
525 | while (*str != '\0') { | |
526 | switch(*str) { | |
527 | case '0': | |
528 | init_uart |= IOP13XX_INIT_UART_0; | |
529 | break; | |
530 | case '1': | |
531 | init_uart |= IOP13XX_INIT_UART_1; | |
532 | break; | |
533 | case ',': | |
534 | case '=': | |
535 | break; | |
536 | default: | |
537 | PRINTK("\"iop13xx_init_uart\" malformed" | |
538 | " at character: \'%c\'", *str); | |
539 | *(str + 1) = '\0'; | |
540 | init_uart = IOP13XX_INIT_UART_DEFAULT; | |
541 | } | |
542 | str++; | |
543 | } | |
544 | } | |
545 | return 1; | |
546 | } | |
547 | ||
548 | static int __init iop13xx_init_i2c_setup(char *str) | |
549 | { | |
550 | if (str) { | |
551 | while (*str != '\0') { | |
552 | switch(*str) { | |
553 | case '0': | |
554 | init_i2c |= IOP13XX_INIT_I2C_0; | |
555 | break; | |
556 | case '1': | |
557 | init_i2c |= IOP13XX_INIT_I2C_1; | |
558 | break; | |
559 | case '2': | |
560 | init_i2c |= IOP13XX_INIT_I2C_2; | |
561 | break; | |
562 | case ',': | |
563 | case '=': | |
564 | break; | |
565 | default: | |
566 | PRINTK("\"iop13xx_init_i2c\" malformed" | |
567 | " at character: \'%c\'", *str); | |
568 | *(str + 1) = '\0'; | |
569 | init_i2c = IOP13XX_INIT_I2C_DEFAULT; | |
570 | } | |
571 | str++; | |
572 | } | |
573 | } | |
574 | return 1; | |
575 | } | |
576 | ||
39a8d7d1 DW |
577 | static int __init iop13xx_init_adma_setup(char *str) |
578 | { | |
579 | if (str) { | |
580 | while (*str != '\0') { | |
581 | switch (*str) { | |
582 | case '0': | |
583 | init_adma |= IOP13XX_INIT_ADMA_0; | |
584 | break; | |
585 | case '1': | |
586 | init_adma |= IOP13XX_INIT_ADMA_1; | |
587 | break; | |
588 | case '2': | |
589 | init_adma |= IOP13XX_INIT_ADMA_2; | |
590 | break; | |
591 | case ',': | |
592 | case '=': | |
593 | break; | |
594 | default: | |
595 | PRINTK("\"iop13xx_init_adma\" malformed" | |
596 | " at character: \'%c\'", *str); | |
597 | *(str + 1) = '\0'; | |
598 | init_adma = IOP13XX_INIT_ADMA_DEFAULT; | |
599 | } | |
600 | str++; | |
601 | } | |
602 | } | |
603 | return 1; | |
604 | } | |
605 | ||
606 | __setup("iop13xx_init_adma", iop13xx_init_adma_setup); | |
285f5fa7 DW |
607 | __setup("iop13xx_init_uart", iop13xx_init_uart_setup); |
608 | __setup("iop13xx_init_i2c", iop13xx_init_i2c_setup); | |
00aa78ee RK |
609 | |
610 | void iop13xx_restart(char mode, const char *cmd) | |
611 | { | |
612 | /* | |
613 | * Reset the internal bus (warning both cores are reset) | |
614 | */ | |
615 | write_wdtcr(IOP_WDTCR_EN_ARM); | |
616 | write_wdtcr(IOP_WDTCR_EN); | |
617 | write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET); | |
618 | write_wdtcr(0x1000); | |
619 | } |