[deliverable/linux.git] / arch / arm / mach-iop32x / iq31244.c

/*
 * arch/arm/mach-iop32x/iq31244.c
 *
 * Board support code for the Intel EP80219 and IQ31244 platforms.
 *
 * Author: Rory Bolt <rorybolt@pacbell.net>
 * Copyright (C) 2002 Rory Bolt
 * Copyright 2003 (c) MontaVista, Software, Inc.
 * Copyright (C) 2004 Intel Corp.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 */

#include <linux/mm.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/pm.h>
#include <linux/string.h>
#include <linux/serial_core.h>
#include <linux/serial_8250.h>
#include <linux/mtd/physmap.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <asm/cputype.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/pci.h>
#include <asm/mach/time.h>
#include <asm/mach-types.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <mach/time.h>
#include "gpio-iop32x.h"

/*
 * Until March of 2007 iq31244 platforms and ep80219 platforms shared the
 * same machine id, and the processor type was used to select board type.
 * However this assumption breaks for an iq80219 board which is an iop219
 * processor on an iq31244 board.  The force_ep80219 flag has been added
 * for old boot loaders using the iq31244 machine id for an ep80219 platform.
 */
static int force_ep80219;

static int is_80219(void)
{
	return !!((read_cpuid_id() & 0xffffffe0) == 0x69052e20);
}

static int is_ep80219(void)
{
	if (machine_is_ep80219() || force_ep80219)
		return 1;
	else
		return 0;
}


/*
 * EP80219/IQ31244 timer tick configuration.
 */
static void __init iq31244_timer_init(void)
{
	if (is_ep80219()) {
		/* 33.333 MHz crystal.  */
		iop_init_time(200000000);
	} else {
		/* 33.000 MHz crystal.  */
		iop_init_time(198000000);
	}
}


/*
 * IQ31244 I/O.
 */
static struct map_desc iq31244_io_desc[] __initdata = {
	{	/* on-board devices */
		.virtual	= IQ31244_UART,
		.pfn		= __phys_to_pfn(IQ31244_UART),
		.length		= 0x00100000,
		.type		= MT_DEVICE,
	},
};

void __init iq31244_map_io(void)
{
	iop3xx_map_io();
	iotable_init(iq31244_io_desc, ARRAY_SIZE(iq31244_io_desc));
}


/*
 * EP80219/IQ31244 PCI.
 */
static int __init
ep80219_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
	int irq;

	if (slot == 0) {
		/* CFlash */
		irq = IRQ_IOP32X_XINT1;
	} else if (slot == 1) {
		/* 82551 Pro 100 */
		irq = IRQ_IOP32X_XINT0;
	} else if (slot == 2) {
		/* PCI-X Slot */
		irq = IRQ_IOP32X_XINT3;
	} else if (slot == 3) {
		/* SATA */
		irq = IRQ_IOP32X_XINT2;
	} else {
		printk(KERN_ERR "ep80219_pci_map_irq() called for unknown "
			"device PCI:%d:%d:%d\n", dev->bus->number,
			PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
		irq = -1;
	}

	return irq;
}

static struct hw_pci ep80219_pci __initdata = {
	.nr_controllers = 1,
	.ops		= &iop3xx_ops,
	.setup		= iop3xx_pci_setup,
	.preinit	= iop3xx_pci_preinit,
	.map_irq	= ep80219_pci_map_irq,
};

static int __init
iq31244_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
	int irq;

	if (slot == 0) {
		/* CFlash */
		irq = IRQ_IOP32X_XINT1;
	} else if (slot == 1) {
		/* SATA */
		irq = IRQ_IOP32X_XINT2;
	} else if (slot == 2) {
		/* PCI-X Slot */
		irq = IRQ_IOP32X_XINT3;
	} else if (slot == 3) {
		/* 82546 GigE */
		irq = IRQ_IOP32X_XINT0;
	} else {
		printk(KERN_ERR "iq31244_pci_map_irq called for unknown "
			"device PCI:%d:%d:%d\n", dev->bus->number,
			PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
		irq = -1;
	}

	return irq;
}

static struct hw_pci iq31244_pci __initdata = {
	.nr_controllers = 1,
	.ops		= &iop3xx_ops,
	.setup		= iop3xx_pci_setup,
	.preinit	= iop3xx_pci_preinit,
	.map_irq	= iq31244_pci_map_irq,
};

static int __init iq31244_pci_init(void)
{
	if (is_ep80219())
		pci_common_init(&ep80219_pci);
	else if (machine_is_iq31244()) {
		if (is_80219()) {
			printk("note: iq31244 board type has been selected\n");
			printk("note: to select ep80219 operation:\n");
			printk("\t1/ specify \"force_ep80219\" on the kernel"
				" command line\n");
			printk("\t2/ update boot loader to pass"
				" the ep80219 id: %d\n", MACH_TYPE_EP80219);
		}
		pci_common_init(&iq31244_pci);
	}

	return 0;
}

subsys_initcall(iq31244_pci_init);


/*
 * IQ31244 machine initialisation.
 */
static struct physmap_flash_data iq31244_flash_data = {
	.width		= 2,
};

static struct resource iq31244_flash_resource = {
	.start		= 0xf0000000,
	.end		= 0xf07fffff,
	.flags		= IORESOURCE_MEM,
};

static struct platform_device iq31244_flash_device = {
	.name		= "physmap-flash",
	.id		= 0,
	.dev		= {
		.platform_data	= &iq31244_flash_data,
	},
	.num_resources	= 1,
	.resource	= &iq31244_flash_resource,
};

static struct plat_serial8250_port iq31244_serial_port[] = {
	{
		.mapbase	= IQ31244_UART,
		.membase	= (char *)IQ31244_UART,
		.irq		= IRQ_IOP32X_XINT1,
		.flags		= UPF_SKIP_TEST,
		.iotype		= UPIO_MEM,
		.regshift	= 0,
		.uartclk	= 1843200,
	},
	{ },
};

static struct resource iq31244_uart_resource = {
	.start		= IQ31244_UART,
	.end		= IQ31244_UART + 7,
	.flags		= IORESOURCE_MEM,
};

static struct platform_device iq31244_serial_device = {
	.name		= "serial8250",
	.id		= PLAT8250_DEV_PLATFORM,
	.dev		= {
		.platform_data		= iq31244_serial_port,
	},
	.num_resources	= 1,
	.resource	= &iq31244_uart_resource,
};

/*
 * This function will send a SHUTDOWN_COMPLETE message to the PIC
 * controller over I2C.  We are not using the i2c subsystem since
 * we are going to power off and it may be removed
 */
void ep80219_power_off(void)
{
	/*
	 * Send the Address byte w/ the start condition
	 */
	*IOP3XX_IDBR1 = 0x60;
	*IOP3XX_ICR1 = 0xE9;
	mdelay(1);

	/*
	 * Send the START_MSG byte w/ no start or stop condition
	 */
	*IOP3XX_IDBR1 = 0x0F;
	*IOP3XX_ICR1 = 0xE8;
	mdelay(1);

	/*
	 * Send the SHUTDOWN_COMPLETE Message ID byte w/ no start or
	 * stop condition
	 */
	*IOP3XX_IDBR1 = 0x03;
	*IOP3XX_ICR1 = 0xE8;
	mdelay(1);

	/*
	 * Send an ignored byte w/ stop condition
	 */
	*IOP3XX_IDBR1 = 0x00;
	*IOP3XX_ICR1 = 0xEA;

	while (1)
		;
}

static void __init iq31244_init_machine(void)
{
	register_iop32x_gpio();
	platform_device_register(&iop3xx_i2c0_device);
	platform_device_register(&iop3xx_i2c1_device);
	platform_device_register(&iq31244_flash_device);
	platform_device_register(&iq31244_serial_device);
	platform_device_register(&iop3xx_dma_0_channel);
	platform_device_register(&iop3xx_dma_1_channel);

	if (is_ep80219())
		pm_power_off = ep80219_power_off;

	if (!is_80219())
		platform_device_register(&iop3xx_aau_channel);
}

static int __init force_ep80219_setup(char *str)
{
	force_ep80219 = 1;
	return 1;
}

__setup("force_ep80219", force_ep80219_setup);

MACHINE_START(IQ31244, "Intel IQ31244")
	/* Maintainer: Intel Corp. */
	.atag_offset	= 0x100,
	.map_io		= iq31244_map_io,
	.init_irq	= iop32x_init_irq,
	.init_time	= iq31244_timer_init,
	.init_machine	= iq31244_init_machine,
	.restart	= iop3xx_restart,
MACHINE_END

/* There should have been an ep80219 machine identifier from the beginning.
 * Boot roms older than March 2007 do not know the ep80219 machine id.  Pass
 * "force_ep80219" on the kernel command line, otherwise iq31244 operation
 * will be selected.
 */
MACHINE_START(EP80219, "Intel EP80219")
	/* Maintainer: Intel Corp. */
	.atag_offset	= 0x100,
	.map_io		= iq31244_map_io,
	.init_irq	= iop32x_init_irq,
	.init_time	= iq31244_timer_init,
	.init_machine	= iq31244_init_machine,
	.restart	= iop3xx_restart,
MACHINE_END
Commit	Line	Data
c680b77e LB	1	/*
	2	* arch/arm/mach-iop32x/iq31244.c
	3	*
	4	* Board support code for the Intel EP80219 and IQ31244 platforms.
	5	*
	6	* Author: Rory Bolt <rorybolt@pacbell.net>
	7	* Copyright (C) 2002 Rory Bolt
	8	* Copyright 2003 (c) MontaVista, Software, Inc.
	9	* Copyright (C) 2004 Intel Corp.
	10	*
	11	* This program is free software; you can redistribute it and/or modify it
	12	* under the terms of the GNU General Public License as published by the
	13	* Free Software Foundation; either version 2 of the License, or (at your
	14	* option) any later version.
	15	*/
	16
	17	#include <linux/mm.h>
	18	#include <linux/init.h>
	19	#include <linux/delay.h>
	20	#include <linux/kernel.h>
	21	#include <linux/pci.h>
	22	#include <linux/pm.h>
	23	#include <linux/string.h>
c680b77e LB	24	#include <linux/serial_core.h>
	25	#include <linux/serial_8250.h>
	26	#include <linux/mtd/physmap.h>
	27	#include <linux/platform_device.h>
fced80c7	28	#include <linux/io.h>
a09e64fb	29	#include <mach/hardware.h>
0ba8b9b2	30	#include <asm/cputype.h>
c680b77e LB	31	#include <asm/irq.h>
	32	#include <asm/mach/arch.h>
	33	#include <asm/mach/map.h>
	34	#include <asm/mach/pci.h>
	35	#include <asm/mach/time.h>
	36	#include <asm/mach-types.h>
	37	#include <asm/page.h>
	38	#include <asm/pgtable.h>
a09e64fb	39	#include <mach/time.h>
7b85b867	40	#include "gpio-iop32x.h"
c680b77e LB	41
c680b77e LB	42	/*
094f1275 DW	43	* Until March of 2007 iq31244 platforms and ep80219 platforms shared the
	44	* same machine id, and the processor type was used to select board type.
	45	* However this assumption breaks for an iq80219 board which is an iop219
	46	* processor on an iq31244 board. The force_ep80219 flag has been added
	47	* for old boot loaders using the iq31244 machine id for an ep80219 platform.
c680b77e	48	*/
094f1275 DW	49	static int force_ep80219;
094f1275 DW	50
c680b77e LB	51	static int is_80219(void)
c680b77e LB	52	{
0ba8b9b2	53	return !!((read_cpuid_id() & 0xffffffe0) == 0x69052e20);
c680b77e LB	54	}
c680b77e LB	55
094f1275 DW	56	static int is_ep80219(void)
	57	{
	58	if (machine_is_ep80219() \|\| force_ep80219)
	59	return 1;
	60	else
	61	return 0;
	62	}
	63
c680b77e LB	64
	65	/*
	66	* EP80219/IQ31244 timer tick configuration.
	67	*/
	68	static void __init iq31244_timer_init(void)
	69	{
094f1275	70	if (is_ep80219()) {
c680b77e	71	/* 33.333 MHz crystal. */
3668b45d	72	iop_init_time(200000000);
c680b77e LB	73	} else {
c680b77e LB	74	/* 33.000 MHz crystal. */
3668b45d	75	iop_init_time(198000000);
c680b77e LB	76	}
	77	}
	78
c680b77e LB	79
	80	/*
	81	* IQ31244 I/O.
	82	*/
	83	static struct map_desc iq31244_io_desc[] __initdata = {
	84	{ /* on-board devices */
	85	.virtual = IQ31244_UART,
	86	.pfn = __phys_to_pfn(IQ31244_UART),
	87	.length = 0x00100000,
	88	.type = MT_DEVICE,
	89	},
	90	};
	91
	92	void __init iq31244_map_io(void)
	93	{
	94	iop3xx_map_io();
	95	iotable_init(iq31244_io_desc, ARRAY_SIZE(iq31244_io_desc));
	96	}
	97
	98
	99	/*
	100	* EP80219/IQ31244 PCI.
	101	*/
d73d8011	102	static int __init
d5341942	103	ep80219_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
c680b77e LB	104	{
	105	int irq;
	106
	107	if (slot == 0) {
	108	/* CFlash */
c852ac80	109	irq = IRQ_IOP32X_XINT1;
c680b77e LB	110	} else if (slot == 1) {
c680b77e LB	111	/* 82551 Pro 100 */
c852ac80	112	irq = IRQ_IOP32X_XINT0;
c680b77e LB	113	} else if (slot == 2) {
c680b77e LB	114	/* PCI-X Slot */
c852ac80	115	irq = IRQ_IOP32X_XINT3;
c680b77e LB	116	} else if (slot == 3) {
c680b77e LB	117	/* SATA */
c852ac80	118	irq = IRQ_IOP32X_XINT2;
c680b77e LB	119	} else {
	120	printk(KERN_ERR "ep80219_pci_map_irq() called for unknown "
	121	"device PCI:%d:%d:%d\n", dev->bus->number,
	122	PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
	123	irq = -1;
	124	}
	125
	126	return irq;
	127	}
	128
	129	static struct hw_pci ep80219_pci __initdata = {
c680b77e	130	.nr_controllers = 1,
c23bfc38	131	.ops = &iop3xx_ops,
c680b77e LB	132	.setup = iop3xx_pci_setup,
c680b77e LB	133	.preinit = iop3xx_pci_preinit,
c680b77e LB	134	.map_irq = ep80219_pci_map_irq,
	135	};
	136
d73d8011	137	static int __init
d5341942	138	iq31244_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
c680b77e LB	139	{
	140	int irq;
	141
	142	if (slot == 0) {
	143	/* CFlash */
c852ac80	144	irq = IRQ_IOP32X_XINT1;
c680b77e LB	145	} else if (slot == 1) {
c680b77e LB	146	/* SATA */
c852ac80	147	irq = IRQ_IOP32X_XINT2;
c680b77e LB	148	} else if (slot == 2) {
c680b77e LB	149	/* PCI-X Slot */
c852ac80	150	irq = IRQ_IOP32X_XINT3;
c680b77e LB	151	} else if (slot == 3) {
c680b77e LB	152	/* 82546 GigE */
c852ac80	153	irq = IRQ_IOP32X_XINT0;
c680b77e	154	} else {
c852ac80	155	printk(KERN_ERR "iq31244_pci_map_irq called for unknown "
c680b77e LB	156	"device PCI:%d:%d:%d\n", dev->bus->number,
	157	PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
	158	irq = -1;
	159	}
	160
	161	return irq;
	162	}
	163
	164	static struct hw_pci iq31244_pci __initdata = {
c680b77e	165	.nr_controllers = 1,
c23bfc38	166	.ops = &iop3xx_ops,
c680b77e LB	167	.setup = iop3xx_pci_setup,
c680b77e LB	168	.preinit = iop3xx_pci_preinit,
c680b77e LB	169	.map_irq = iq31244_pci_map_irq,
	170	};
	171
	172	static int __init iq31244_pci_init(void)
	173	{
c34002c1 DW	174	if (is_ep80219())
	175	pci_common_init(&ep80219_pci);
	176	else if (machine_is_iq31244()) {
c680b77e	177	if (is_80219()) {
094f1275 DW	178	printk("note: iq31244 board type has been selected\n");
	179	printk("note: to select ep80219 operation:\n");
	180	printk("\t1/ specify \"force_ep80219\" on the kernel"
	181	" command line\n");
	182	printk("\t2/ update boot loader to pass"
	183	" the ep80219 id: %d\n", MACH_TYPE_EP80219);
c680b77e	184	}
c34002c1	185	pci_common_init(&iq31244_pci);
c680b77e LB	186	}
	187
	188	return 0;
	189	}
	190
	191	subsys_initcall(iq31244_pci_init);
	192
	193
	194	/*
	195	* IQ31244 machine initialisation.
	196	*/
	197	static struct physmap_flash_data iq31244_flash_data = {
	198	.width = 2,
	199	};
	200
	201	static struct resource iq31244_flash_resource = {
	202	.start = 0xf0000000,
	203	.end = 0xf07fffff,
	204	.flags = IORESOURCE_MEM,
	205	};
	206
	207	static struct platform_device iq31244_flash_device = {
	208	.name = "physmap-flash",
	209	.id = 0,
	210	.dev = {
	211	.platform_data = &iq31244_flash_data,
	212	},
	213	.num_resources = 1,
	214	.resource = &iq31244_flash_resource,
	215	};
	216
	217	static struct plat_serial8250_port iq31244_serial_port[] = {
	218	{
	219	.mapbase = IQ31244_UART,
	220	.membase = (char *)IQ31244_UART,
c852ac80	221	.irq = IRQ_IOP32X_XINT1,
c680b77e LB	222	.flags = UPF_SKIP_TEST,
	223	.iotype = UPIO_MEM,
	224	.regshift = 0,
	225	.uartclk = 1843200,
	226	},
	227	{ },
	228	};
	229
	230	static struct resource iq31244_uart_resource = {
	231	.start = IQ31244_UART,
	232	.end = IQ31244_UART + 7,
	233	.flags = IORESOURCE_MEM,
	234	};
	235
	236	static struct platform_device iq31244_serial_device = {
	237	.name = "serial8250",
	238	.id = PLAT8250_DEV_PLATFORM,
	239	.dev = {
	240	.platform_data = iq31244_serial_port,
	241	},
	242	.num_resources = 1,
	243	.resource = &iq31244_uart_resource,
	244	};
	245
	246	/*
	247	* This function will send a SHUTDOWN_COMPLETE message to the PIC
	248	* controller over I2C. We are not using the i2c subsystem since
	249	* we are going to power off and it may be removed
	250	*/
	251	void ep80219_power_off(void)
	252	{
	253	/*
	254	* Send the Address byte w/ the start condition
	255	*/
	256	*IOP3XX_IDBR1 = 0x60;
	257	*IOP3XX_ICR1 = 0xE9;
	258	mdelay(1);
	259
	260	/*
	261	* Send the START_MSG byte w/ no start or stop condition
	262	*/
	263	*IOP3XX_IDBR1 = 0x0F;
	264	*IOP3XX_ICR1 = 0xE8;
	265	mdelay(1);
	266
	267	/*
	268	* Send the SHUTDOWN_COMPLETE Message ID byte w/ no start or
	269	* stop condition
	270	*/
	271	*IOP3XX_IDBR1 = 0x03;
	272	*IOP3XX_ICR1 = 0xE8;
	273	mdelay(1);
	274
	275	/*
	276	* Send an ignored byte w/ stop condition
	277	*/
	278	*IOP3XX_IDBR1 = 0x00;
	279	*IOP3XX_ICR1 = 0xEA;
	280
	281	while (1)
	282	;
	283	}
	284
	285	static void __init iq31244_init_machine(void)
286	{
7b85b867	287	register_iop32x_gpio();
c680b77e LB	288	platform_device_register(&iop3xx_i2c0_device);
	289	platform_device_register(&iop3xx_i2c1_device);
	290	platform_device_register(&iq31244_flash_device);
	291	platform_device_register(&iq31244_serial_device);
2492c845 DW	292	platform_device_register(&iop3xx_dma_0_channel);
2492c845 DW	293	platform_device_register(&iop3xx_dma_1_channel);
c680b77e	294
094f1275	295	if (is_ep80219())
c680b77e	296	pm_power_off = ep80219_power_off;
2492c845 DW	297
	298	if (!is_80219())
	299	platform_device_register(&iop3xx_aau_channel);
c680b77e LB	300	}
c680b77e LB	301
094f1275 DW	302	static int __init force_ep80219_setup(char *str)
	303	{
	304	force_ep80219 = 1;
	305	return 1;
	306	}
	307
	308	__setup("force_ep80219", force_ep80219_setup);
	309
c680b77e LB	310	MACHINE_START(IQ31244, "Intel IQ31244")
c680b77e LB	311	/* Maintainer: Intel Corp. */
1896746d	312	.atag_offset = 0x100,
c680b77e	313	.map_io = iq31244_map_io,
c852ac80	314	.init_irq = iop32x_init_irq,
6bb27d73	315	.init_time = iq31244_timer_init,
c680b77e	316	.init_machine = iq31244_init_machine,
bec92b1e	317	.restart = iop3xx_restart,
c680b77e	318	MACHINE_END
094f1275 DW	319
	320	/* There should have been an ep80219 machine identifier from the beginning.
	321	* Boot roms older than March 2007 do not know the ep80219 machine id. Pass
	322	* "force_ep80219" on the kernel command line, otherwise iq31244 operation
	323	* will be selected.
	324	*/
	325	MACHINE_START(EP80219, "Intel EP80219")
	326	/* Maintainer: Intel Corp. */
1896746d	327	.atag_offset = 0x100,
094f1275 DW	328	.map_io = iq31244_map_io,
094f1275 DW	329	.init_irq = iop32x_init_irq,
6bb27d73	330	.init_time = iq31244_timer_init,
094f1275	331	.init_machine = iq31244_init_machine,
bec92b1e	332	.restart = iop3xx_restart,
094f1275	333	MACHINE_END