[deliverable/linux.git] / arch / arm / mach-iop32x / iq80321.c

/*
 * arch/arm/mach-iop32x/iq80321.c
 *
 * Board support code for the Intel IQ80321 platform.
 *
 * Author: Rory Bolt <rorybolt@pacbell.net>
 * Copyright (C) 2002 Rory Bolt
 * Copyright (C) 2004 Intel Corp.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 */

#include <linux/mm.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/string.h>
#include <linux/serial_core.h>
#include <linux/serial_8250.h>
#include <linux/mtd/physmap.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/pci.h>
#include <asm/mach/time.h>
#include <asm/mach-types.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <mach/time.h>
#include "gpio-iop32x.h"

/*
 * IQ80321 timer tick configuration.
 */
static void __init iq80321_timer_init(void)
{
	/* 33.333 MHz crystal.  */
	iop_init_time(200000000);
}


/*
 * IQ80321 I/O.
 */
static struct map_desc iq80321_io_desc[] __initdata = {
 	{	/* on-board devices */
		.virtual	= IQ80321_UART,
		.pfn		= __phys_to_pfn(IQ80321_UART),
		.length		= 0x00100000,
		.type		= MT_DEVICE,
	},
};

void __init iq80321_map_io(void)
{
	iop3xx_map_io();
	iotable_init(iq80321_io_desc, ARRAY_SIZE(iq80321_io_desc));
}


/*
 * IQ80321 PCI.
 */
static int __init
iq80321_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
	int irq;

	if ((slot == 2 || slot == 6) && pin == 1) {
		/* PCI-X Slot INTA */
		irq = IRQ_IOP32X_XINT2;
	} else if ((slot == 2 || slot == 6) && pin == 2) {
		/* PCI-X Slot INTA */
		irq = IRQ_IOP32X_XINT3;
	} else if ((slot == 2 || slot == 6) && pin == 3) {
		/* PCI-X Slot INTA */
		irq = IRQ_IOP32X_XINT0;
	} else if ((slot == 2 || slot == 6) && pin == 4) {
		/* PCI-X Slot INTA */
		irq = IRQ_IOP32X_XINT1;
	} else if (slot == 4 || slot == 8) {
		/* Gig-E */
		irq = IRQ_IOP32X_XINT0;
	} else {
		printk(KERN_ERR "iq80321_pci_map_irq() called for unknown "
			"device PCI:%d:%d:%d\n", dev->bus->number,
			PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
		irq = -1;
	}

	return irq;
}

static struct hw_pci iq80321_pci __initdata = {
	.nr_controllers = 1,
	.ops		= &iop3xx_ops,
	.setup		= iop3xx_pci_setup,
	.preinit	= iop3xx_pci_preinit_cond,
	.map_irq	= iq80321_pci_map_irq,
};

static int __init iq80321_pci_init(void)
{
	if ((iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) &&
		machine_is_iq80321())
		pci_common_init(&iq80321_pci);

	return 0;
}

subsys_initcall(iq80321_pci_init);


/*
 * IQ80321 machine initialisation.
 */
static struct physmap_flash_data iq80321_flash_data = {
	.width		= 1,
};

static struct resource iq80321_flash_resource = {
	.start		= 0xf0000000,
	.end		= 0xf07fffff,
	.flags		= IORESOURCE_MEM,
};

static struct platform_device iq80321_flash_device = {
	.name		= "physmap-flash",
	.id		= 0,
	.dev		= {
		.platform_data	= &iq80321_flash_data,
	},
	.num_resources	= 1,
	.resource	= &iq80321_flash_resource,
};

static struct plat_serial8250_port iq80321_serial_port[] = {
	{
		.mapbase	= IQ80321_UART,
		.membase	= (char *)IQ80321_UART,
		.irq		= IRQ_IOP32X_XINT1,
		.flags		= UPF_SKIP_TEST,
		.iotype		= UPIO_MEM,
		.regshift	= 0,
		.uartclk	= 1843200,
	},
	{ },
};

static struct resource iq80321_uart_resource = {
	.start		= IQ80321_UART,
	.end		= IQ80321_UART + 7,
	.flags		= IORESOURCE_MEM,
};

static struct platform_device iq80321_serial_device = {
	.name		= "serial8250",
	.id		= PLAT8250_DEV_PLATFORM,
	.dev		= {
		.platform_data		= iq80321_serial_port,
	},
	.num_resources	= 1,
	.resource	= &iq80321_uart_resource,
};

static void __init iq80321_init_machine(void)
{
	register_iop32x_gpio();
	platform_device_register(&iop3xx_i2c0_device);
	platform_device_register(&iop3xx_i2c1_device);
	platform_device_register(&iq80321_flash_device);
	platform_device_register(&iq80321_serial_device);
	platform_device_register(&iop3xx_dma_0_channel);
	platform_device_register(&iop3xx_dma_1_channel);
	platform_device_register(&iop3xx_aau_channel);
}

MACHINE_START(IQ80321, "Intel IQ80321")
	/* Maintainer: Intel Corp. */
	.atag_offset	= 0x100,
	.map_io		= iq80321_map_io,
	.init_irq	= iop32x_init_irq,
	.init_time	= iq80321_timer_init,
	.init_machine	= iq80321_init_machine,
	.restart	= iop3xx_restart,
MACHINE_END
Commit	Line	Data
c680b77e LB	1	/*
	2	* arch/arm/mach-iop32x/iq80321.c
	3	*
	4	* Board support code for the Intel IQ80321 platform.
	5	*
	6	* Author: Rory Bolt <rorybolt@pacbell.net>
	7	* Copyright (C) 2002 Rory Bolt
	8	* Copyright (C) 2004 Intel Corp.
	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License as published by the
	12	* Free Software Foundation; either version 2 of the License, or (at your
	13	* option) any later version.
	14	*/
	15
	16	#include <linux/mm.h>
	17	#include <linux/init.h>
	18	#include <linux/kernel.h>
	19	#include <linux/pci.h>
	20	#include <linux/string.h>
c680b77e LB	21	#include <linux/serial_core.h>
	22	#include <linux/serial_8250.h>
	23	#include <linux/mtd/physmap.h>
	24	#include <linux/platform_device.h>
fced80c7	25	#include <linux/io.h>
a09e64fb	26	#include <mach/hardware.h>
c680b77e LB	27	#include <asm/irq.h>
	28	#include <asm/mach/arch.h>
	29	#include <asm/mach/map.h>
	30	#include <asm/mach/pci.h>
	31	#include <asm/mach/time.h>
	32	#include <asm/mach-types.h>
	33	#include <asm/page.h>
	34	#include <asm/pgtable.h>
a09e64fb	35	#include <mach/time.h>
7b85b867	36	#include "gpio-iop32x.h"
c680b77e LB	37
	38	/*
	39	* IQ80321 timer tick configuration.
	40	*/
	41	static void __init iq80321_timer_init(void)
	42	{
	43	/* 33.333 MHz crystal. */
3668b45d	44	iop_init_time(200000000);
c680b77e LB	45	}
c680b77e LB	46
c680b77e LB	47
	48	/*
	49	* IQ80321 I/O.
	50	*/
	51	static struct map_desc iq80321_io_desc[] __initdata = {
	52	{ /* on-board devices */
	53	.virtual = IQ80321_UART,
	54	.pfn = __phys_to_pfn(IQ80321_UART),
	55	.length = 0x00100000,
	56	.type = MT_DEVICE,
	57	},
	58	};
	59
	60	void __init iq80321_map_io(void)
	61	{
	62	iop3xx_map_io();
	63	iotable_init(iq80321_io_desc, ARRAY_SIZE(iq80321_io_desc));
	64	}
	65
	66
	67	/*
	68	* IQ80321 PCI.
	69	*/
d73d8011	70	static int __init
d5341942	71	iq80321_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
c680b77e LB	72	{
	73	int irq;
	74
	75	if ((slot == 2 \|\| slot == 6) && pin == 1) {
	76	/* PCI-X Slot INTA */
c852ac80	77	irq = IRQ_IOP32X_XINT2;
c680b77e LB	78	} else if ((slot == 2 \|\| slot == 6) && pin == 2) {
c680b77e LB	79	/* PCI-X Slot INTA */
c852ac80	80	irq = IRQ_IOP32X_XINT3;
c680b77e LB	81	} else if ((slot == 2 \|\| slot == 6) && pin == 3) {
c680b77e LB	82	/* PCI-X Slot INTA */
c852ac80	83	irq = IRQ_IOP32X_XINT0;
c680b77e LB	84	} else if ((slot == 2 \|\| slot == 6) && pin == 4) {
c680b77e LB	85	/* PCI-X Slot INTA */
c852ac80	86	irq = IRQ_IOP32X_XINT1;
c680b77e LB	87	} else if (slot == 4 \|\| slot == 8) {
c680b77e LB	88	/* Gig-E */
c852ac80	89	irq = IRQ_IOP32X_XINT0;
c680b77e LB	90	} else {
	91	printk(KERN_ERR "iq80321_pci_map_irq() called for unknown "
	92	"device PCI:%d:%d:%d\n", dev->bus->number,
	93	PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
	94	irq = -1;
	95	}
	96
	97	return irq;
	98	}
	99
	100	static struct hw_pci iq80321_pci __initdata = {
c680b77e	101	.nr_controllers = 1,
c23bfc38	102	.ops = &iop3xx_ops,
c680b77e	103	.setup = iop3xx_pci_setup,
c34002c1	104	.preinit = iop3xx_pci_preinit_cond,
c680b77e LB	105	.map_irq = iq80321_pci_map_irq,
	106	};
	107
	108	static int __init iq80321_pci_init(void)
	109	{
e90ddd81 DW	110	if ((iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) &&
e90ddd81 DW	111	machine_is_iq80321())
c680b77e LB	112	pci_common_init(&iq80321_pci);
	113
	114	return 0;
	115	}
	116
	117	subsys_initcall(iq80321_pci_init);
	118
	119
	120	/*
	121	* IQ80321 machine initialisation.
	122	*/
	123	static struct physmap_flash_data iq80321_flash_data = {
	124	.width = 1,
	125	};
	126
	127	static struct resource iq80321_flash_resource = {
	128	.start = 0xf0000000,
	129	.end = 0xf07fffff,
	130	.flags = IORESOURCE_MEM,
	131	};
	132
	133	static struct platform_device iq80321_flash_device = {
	134	.name = "physmap-flash",
	135	.id = 0,
	136	.dev = {
	137	.platform_data = &iq80321_flash_data,
	138	},
	139	.num_resources = 1,
	140	.resource = &iq80321_flash_resource,
	141	};
	142
	143	static struct plat_serial8250_port iq80321_serial_port[] = {
	144	{
	145	.mapbase = IQ80321_UART,
	146	.membase = (char *)IQ80321_UART,
c852ac80	147	.irq = IRQ_IOP32X_XINT1,
c680b77e LB	148	.flags = UPF_SKIP_TEST,
	149	.iotype = UPIO_MEM,
	150	.regshift = 0,
	151	.uartclk = 1843200,
	152	},
	153	{ },
	154	};
	155
	156	static struct resource iq80321_uart_resource = {
	157	.start = IQ80321_UART,
	158	.end = IQ80321_UART + 7,
	159	.flags = IORESOURCE_MEM,
	160	};
	161
	162	static struct platform_device iq80321_serial_device = {
	163	.name = "serial8250",
	164	.id = PLAT8250_DEV_PLATFORM,
	165	.dev = {
	166	.platform_data = iq80321_serial_port,
	167	},
	168	.num_resources = 1,
	169	.resource = &iq80321_uart_resource,
	170	};
	171
	172	static void __init iq80321_init_machine(void)
	173	{
7b85b867	174	register_iop32x_gpio();
c680b77e LB	175	platform_device_register(&iop3xx_i2c0_device);
	176	platform_device_register(&iop3xx_i2c1_device);
	177	platform_device_register(&iq80321_flash_device);
	178	platform_device_register(&iq80321_serial_device);
2492c845 DW	179	platform_device_register(&iop3xx_dma_0_channel);
	180	platform_device_register(&iop3xx_dma_1_channel);
	181	platform_device_register(&iop3xx_aau_channel);
c680b77e LB	182	}
	183
	184	MACHINE_START(IQ80321, "Intel IQ80321")
	185	/* Maintainer: Intel Corp. */
1896746d	186	.atag_offset = 0x100,
c680b77e	187	.map_io = iq80321_map_io,
c852ac80	188	.init_irq = iop32x_init_irq,
6bb27d73	189	.init_time = iq80321_timer_init,
c680b77e	190	.init_machine = iq80321_init_machine,
bec92b1e	191	.restart = iop3xx_restart,
c680b77e	192	MACHINE_END