Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
3f7e5815 | 2 | * linux/arch/arm/mach-iop32x/setup.c |
1da177e4 LT |
3 | * |
4 | * Author: Nicolas Pitre <nico@cam.org> | |
5 | * Copyright (C) 2001 MontaVista Software, Inc. | |
6 | * Copyright (C) 2004 Intel Corporation. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | */ | |
13 | #include <linux/mm.h> | |
14 | #include <linux/init.h> | |
1da177e4 LT |
15 | #include <linux/major.h> |
16 | #include <linux/fs.h> | |
d052d1be | 17 | #include <linux/platform_device.h> |
1da177e4 LT |
18 | #include <linux/serial.h> |
19 | #include <linux/tty.h> | |
20 | #include <linux/serial_core.h> | |
21 | ||
22 | #include <asm/io.h> | |
23 | #include <asm/pgtable.h> | |
24 | #include <asm/page.h> | |
25 | #include <asm/mach/map.h> | |
26 | #include <asm/setup.h> | |
27 | #include <asm/system.h> | |
28 | #include <asm/memory.h> | |
29 | #include <asm/hardware.h> | |
30 | #include <asm/mach-types.h> | |
31 | #include <asm/mach/arch.h> | |
32 | ||
33 | #define IOP321_UART_XTAL 1843200 | |
34 | ||
35 | /* | |
36 | * Standard IO mapping for all IOP321 based systems | |
37 | */ | |
38 | static struct map_desc iop321_std_desc[] __initdata = { | |
4835e64a DS |
39 | { /* mem mapped registers */ |
40 | .virtual = IOP321_VIRT_MEM_BASE, | |
41 | .pfn = __phys_to_pfn(IOP321_PHYS_MEM_BASE), | |
42 | .length = 0x00002000, | |
43 | .type = MT_DEVICE | |
44 | }, { /* PCI IO space */ | |
45 | .virtual = IOP321_PCI_LOWER_IO_VA, | |
46 | .pfn = __phys_to_pfn(IOP321_PCI_LOWER_IO_PA), | |
47 | .length = IOP321_PCI_IO_WINDOW_SIZE, | |
48 | .type = MT_DEVICE | |
49 | } | |
1da177e4 LT |
50 | }; |
51 | ||
52 | #ifdef CONFIG_ARCH_IQ80321 | |
53 | #define UARTBASE IQ80321_UART | |
54 | #define IRQ_UART IRQ_IQ80321_UART | |
55 | #endif | |
56 | ||
57 | #ifdef CONFIG_ARCH_IQ31244 | |
58 | #define UARTBASE IQ31244_UART | |
59 | #define IRQ_UART IRQ_IQ31244_UART | |
60 | #endif | |
61 | ||
62 | static struct uart_port iop321_serial_ports[] = { | |
63 | { | |
64 | .membase = (char*)(UARTBASE), | |
65 | .mapbase = (UARTBASE), | |
66 | .irq = IRQ_UART, | |
67 | .flags = UPF_SKIP_TEST, | |
68 | .iotype = UPIO_MEM, | |
69 | .regshift = 0, | |
70 | .uartclk = IOP321_UART_XTAL, | |
71 | .line = 0, | |
72 | .type = PORT_16550A, | |
73 | .fifosize = 16 | |
74 | } | |
75 | }; | |
76 | ||
77 | static struct resource iop32x_i2c_0_resources[] = { | |
78 | [0] = { | |
79 | .start = 0xfffff680, | |
80 | .end = 0xfffff698, | |
81 | .flags = IORESOURCE_MEM, | |
82 | }, | |
83 | [1] = { | |
84 | .start = IRQ_IOP321_I2C_0, | |
85 | .end = IRQ_IOP321_I2C_0, | |
86 | .flags = IORESOURCE_IRQ | |
87 | } | |
88 | }; | |
89 | ||
90 | static struct resource iop32x_i2c_1_resources[] = { | |
91 | [0] = { | |
92 | .start = 0xfffff6a0, | |
93 | .end = 0xfffff6b8, | |
94 | .flags = IORESOURCE_MEM, | |
95 | }, | |
96 | [1] = { | |
97 | .start = IRQ_IOP321_I2C_1, | |
98 | .end = IRQ_IOP321_I2C_1, | |
99 | .flags = IORESOURCE_IRQ | |
100 | } | |
101 | }; | |
102 | ||
103 | static struct platform_device iop32x_i2c_0_controller = { | |
104 | .name = "IOP3xx-I2C", | |
105 | .id = 0, | |
106 | .num_resources = 2, | |
107 | .resource = iop32x_i2c_0_resources | |
108 | }; | |
109 | ||
110 | static struct platform_device iop32x_i2c_1_controller = { | |
111 | .name = "IOP3xx-I2C", | |
112 | .id = 1, | |
113 | .num_resources = 2, | |
114 | .resource = iop32x_i2c_1_resources | |
115 | }; | |
116 | ||
117 | static struct platform_device *iop32x_devices[] __initdata = { | |
118 | &iop32x_i2c_0_controller, | |
119 | &iop32x_i2c_1_controller | |
120 | }; | |
121 | ||
122 | void __init iop32x_init(void) | |
123 | { | |
124 | if(iop_is_321()) | |
125 | { | |
126 | platform_add_devices(iop32x_devices, | |
127 | ARRAY_SIZE(iop32x_devices)); | |
128 | } | |
129 | } | |
130 | ||
131 | void __init iop321_map_io(void) | |
132 | { | |
133 | iotable_init(iop321_std_desc, ARRAY_SIZE(iop321_std_desc)); | |
134 | early_serial_setup(&iop321_serial_ports[0]); | |
135 | } | |
136 | ||
137 | #ifdef CONFIG_ARCH_IQ80321 | |
138 | extern void iq80321_map_io(void); | |
139 | extern struct sys_timer iop321_timer; | |
140 | extern void iop321_init_time(void); | |
141 | #endif | |
142 | ||
143 | #ifdef CONFIG_ARCH_IQ31244 | |
144 | extern void iq31244_map_io(void); | |
145 | extern struct sys_timer iop321_timer; | |
146 | extern void iop321_init_time(void); | |
147 | #endif | |
148 | ||
149 | #if defined(CONFIG_ARCH_IQ80321) | |
150 | MACHINE_START(IQ80321, "Intel IQ80321") | |
e9dea0c6 | 151 | /* Maintainer: Intel Corporation */ |
e9dea0c6 RK |
152 | .phys_io = IQ80321_UART, |
153 | .io_pg_offst = ((IQ80321_UART) >> 18) & 0xfffc, | |
154 | .map_io = iq80321_map_io, | |
155 | .init_irq = iop321_init_irq, | |
1da177e4 | 156 | .timer = &iop321_timer, |
e9dea0c6 RK |
157 | .boot_params = 0xa0000100, |
158 | .init_machine = iop32x_init, | |
1da177e4 LT |
159 | MACHINE_END |
160 | #elif defined(CONFIG_ARCH_IQ31244) | |
161 | MACHINE_START(IQ31244, "Intel IQ31244") | |
e9dea0c6 | 162 | /* Maintainer: Intel Corp. */ |
e9dea0c6 RK |
163 | .phys_io = IQ31244_UART, |
164 | .io_pg_offst = ((IQ31244_UART) >> 18) & 0xfffc, | |
165 | .map_io = iq31244_map_io, | |
166 | .init_irq = iop321_init_irq, | |
1da177e4 | 167 | .timer = &iop321_timer, |
e9dea0c6 RK |
168 | .boot_params = 0xa0000100, |
169 | .init_machine = iop32x_init, | |
1da177e4 LT |
170 | MACHINE_END |
171 | #else | |
172 | #error No machine descriptor defined for this IOP3XX implementation | |
173 | #endif |