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1da177e4 | 1 | /* |
3f7e5815 | 2 | * linux/arch/arm/mach-iop32x/setup.c |
1da177e4 LT |
3 | * |
4 | * Author: Nicolas Pitre <nico@cam.org> | |
5 | * Copyright (C) 2001 MontaVista Software, Inc. | |
6 | * Copyright (C) 2004 Intel Corporation. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | */ | |
13 | #include <linux/mm.h> | |
14 | #include <linux/init.h> | |
1da177e4 LT |
15 | #include <linux/major.h> |
16 | #include <linux/fs.h> | |
d052d1be | 17 | #include <linux/platform_device.h> |
1da177e4 LT |
18 | #include <linux/serial.h> |
19 | #include <linux/tty.h> | |
20 | #include <linux/serial_core.h> | |
21 | ||
22 | #include <asm/io.h> | |
23 | #include <asm/pgtable.h> | |
24 | #include <asm/page.h> | |
25 | #include <asm/mach/map.h> | |
26 | #include <asm/setup.h> | |
27 | #include <asm/system.h> | |
28 | #include <asm/memory.h> | |
29 | #include <asm/hardware.h> | |
30 | #include <asm/mach-types.h> | |
31 | #include <asm/mach/arch.h> | |
863753a8 | 32 | #include <asm/mach/time.h> |
e25d64f1 | 33 | #include <asm/hardware/iop3xx.h> |
1da177e4 LT |
34 | |
35 | #define IOP321_UART_XTAL 1843200 | |
36 | ||
1da177e4 LT |
37 | #ifdef CONFIG_ARCH_IQ80321 |
38 | #define UARTBASE IQ80321_UART | |
39 | #define IRQ_UART IRQ_IQ80321_UART | |
40 | #endif | |
41 | ||
42 | #ifdef CONFIG_ARCH_IQ31244 | |
43 | #define UARTBASE IQ31244_UART | |
44 | #define IRQ_UART IRQ_IQ31244_UART | |
45 | #endif | |
46 | ||
47 | static struct uart_port iop321_serial_ports[] = { | |
48 | { | |
49 | .membase = (char*)(UARTBASE), | |
50 | .mapbase = (UARTBASE), | |
51 | .irq = IRQ_UART, | |
52 | .flags = UPF_SKIP_TEST, | |
53 | .iotype = UPIO_MEM, | |
54 | .regshift = 0, | |
55 | .uartclk = IOP321_UART_XTAL, | |
56 | .line = 0, | |
57 | .type = PORT_16550A, | |
58 | .fifosize = 16 | |
59 | } | |
60 | }; | |
61 | ||
1da177e4 LT |
62 | void __init iop32x_init(void) |
63 | { | |
e25d64f1 LB |
64 | platform_device_register(&iop3xx_i2c0_device); |
65 | platform_device_register(&iop3xx_i2c1_device); | |
1da177e4 LT |
66 | early_serial_setup(&iop321_serial_ports[0]); |
67 | } | |
68 | ||
69 | #ifdef CONFIG_ARCH_IQ80321 | |
70 | extern void iq80321_map_io(void); | |
1da177e4 LT |
71 | #endif |
72 | ||
73 | #ifdef CONFIG_ARCH_IQ31244 | |
74 | extern void iq31244_map_io(void); | |
1da177e4 LT |
75 | #endif |
76 | ||
863753a8 LB |
77 | static void __init iop3xx_timer_init(void) |
78 | { | |
79 | iop3xx_init_time(IOP321_TICK_RATE); | |
80 | } | |
81 | ||
82 | struct sys_timer iop321_timer = { | |
83 | .init = iop3xx_timer_init, | |
84 | .offset = iop3xx_gettimeoffset, | |
85 | }; | |
86 | ||
1da177e4 LT |
87 | #if defined(CONFIG_ARCH_IQ80321) |
88 | MACHINE_START(IQ80321, "Intel IQ80321") | |
e9dea0c6 | 89 | /* Maintainer: Intel Corporation */ |
e9dea0c6 RK |
90 | .phys_io = IQ80321_UART, |
91 | .io_pg_offst = ((IQ80321_UART) >> 18) & 0xfffc, | |
92 | .map_io = iq80321_map_io, | |
93 | .init_irq = iop321_init_irq, | |
1da177e4 | 94 | .timer = &iop321_timer, |
e9dea0c6 RK |
95 | .boot_params = 0xa0000100, |
96 | .init_machine = iop32x_init, | |
1da177e4 LT |
97 | MACHINE_END |
98 | #elif defined(CONFIG_ARCH_IQ31244) | |
99 | MACHINE_START(IQ31244, "Intel IQ31244") | |
e9dea0c6 | 100 | /* Maintainer: Intel Corp. */ |
e9dea0c6 RK |
101 | .phys_io = IQ31244_UART, |
102 | .io_pg_offst = ((IQ31244_UART) >> 18) & 0xfffc, | |
103 | .map_io = iq31244_map_io, | |
104 | .init_irq = iop321_init_irq, | |
1da177e4 | 105 | .timer = &iop321_timer, |
e9dea0c6 RK |
106 | .boot_params = 0xa0000100, |
107 | .init_machine = iop32x_init, | |
1da177e4 LT |
108 | MACHINE_END |
109 | #else | |
110 | #error No machine descriptor defined for this IOP3XX implementation | |
111 | #endif |