projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /* |
| 2 | * linux/arch/arm/mach-iop3xx/iop321-irq.c | |
| 3 | * | |
| 4 | * Generic IOP321 IRQ handling functionality | |
| 5 | * | |
| 6 | * Author: Rory Bolt <rorybolt@pacbell.net> | |
| 7 | * Copyright (C) 2002 Rory Bolt | |
| 8 | * | |
| 9 | * This program is free software; you can redistribute it and/or modify | |
| 10 | * it under the terms of the GNU General Public License version 2 as | |
| 11 | * published by the Free Software Foundation. | |
| 12 | * | |
| 13 | * Added IOP3XX chipset and IQ80321 board masking code. | |
| 14 | * | |
| 15 | */ | |
| 16 | #include <linux/init.h> | |
| 17 | #include <linux/interrupt.h> | |
| 18 | #include <linux/list.h> | |
| 19 | ||
| 20 | #include <asm/mach/irq.h> | |
| 21 | #include <asm/irq.h> | |
| 22 | #include <asm/hardware.h> | |
| 23 | ||
| 24 | #include <asm/mach-types.h> | |
| 25 | ||
| 26 | static u32 iop321_mask /* = 0 */; | |
| 27 | ||
| 28 | static inline void intctl_write(u32 val) | |
| 29 | { | |
| 30 | asm volatile("mcr p6,0,%0,c0,c0,0"::"r" (val)); | |
| 31 | } | |
| 32 | ||
| 33 | static inline void intstr_write(u32 val) | |
| 34 | { | |
| 35 | asm volatile("mcr p6,0,%0,c4,c0,0"::"r" (val)); | |
| 36 | } | |
| 37 | ||
| 38 | static void | |
| 39 | iop321_irq_mask (unsigned int irq) | |
| 40 | { | |
| 41 | ||
| 42 | iop321_mask &= ~(1 << (irq - IOP321_IRQ_OFS)); | |
| 43 | ||
| 44 | intctl_write(iop321_mask); | |
| 45 | } | |
| 46 | ||
| 47 | static void | |
| 48 | iop321_irq_unmask (unsigned int irq) | |
| 49 | { | |
| 50 | iop321_mask |= (1 << (irq - IOP321_IRQ_OFS)); | |
| 51 | ||
| 52 | intctl_write(iop321_mask); | |
| 53 | } | |
| 54 | ||
| 55 | struct irqchip ext_chip = { | |
| 56 | .ack = iop321_irq_mask, | |
| 57 | .mask = iop321_irq_mask, | |
| 58 | .unmask = iop321_irq_unmask, | |
| 59 | }; | |
| 60 | ||
| 61 | void __init iop321_init_irq(void) | |
| 62 | { | |
| 63 | unsigned int i, tmp; | |
| 64 | ||
| 65 | /* Enable access to coprocessor 6 for dealing with IRQs. | |
| 66 | * From RMK: | |
| 67 | * Basically, the Intel documentation here is poor. It appears that | |
| 68 | * you need to set the bit to be able to access the coprocessor from | |
| 69 | * SVC mode. Whether that allows access from user space or not is | |
| 70 | * unclear. | |
| 71 | */ | |
| 72 | asm volatile ( | |
| 73 | "mrc p15, 0, %0, c15, c1, 0\n\t" | |
| 74 | "orr %0, %0, %1\n\t" | |
| 75 | "mcr p15, 0, %0, c15, c1, 0\n\t" | |
| 76 | /* The action is delayed, so we have to do this: */ | |
| 77 | "mrc p15, 0, %0, c15, c1, 0\n\t" | |
| 78 | "mov %0, %0\n\t" | |
| 79 | "sub pc, pc, #4" | |
| 80 | : "=r" (tmp) : "i" (1 << 6) ); | |
| 81 | ||
| 82 | intctl_write(0); // disable all interrupts | |
| 83 | intstr_write(0); // treat all as IRQ | |
| 84 | if(machine_is_iq80321() || | |
| 85 | machine_is_iq31244()) // all interrupts are inputs to chip | |
| 86 | *IOP321_PCIIRSR = 0x0f; | |
| 87 | ||
| 88 | for(i = IOP321_IRQ_OFS; i < NR_IOP321_IRQS; i++) | |
| 89 | { | |
| 90 | set_irq_chip(i, &ext_chip); | |
| 91 | set_irq_handler(i, do_level_IRQ); | |
| 92 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); | |
| 93 | ||
| 94 | } | |
| 95 | } | |
| 96 |