[ARM] 4033/1: Add separate Avila board setup code
[deliverable/linux.git] / arch / arm / mach-ixp4xx / Kconfig
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1if ARCH_IXP4XX
2
3config ARCH_SUPPORTS_BIG_ENDIAN
4 bool
5 default y
6
7menu "Intel IXP4xx Implementation Options"
8
9comment "IXP4xx Platforms"
10
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11config MACH_NSLU2
12 bool
e7fcdb79 13 prompt "Linksys NSLU2"
76bbb002 14 select PCI
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15 help
16 Say 'Y' here if you want your kernel to support Linksys's
17 NSLU2 NAS device. For more information on this platform,
18 see http://www.nslu2-linux.org
19
0f185971 20config MACH_AVILA
1da177e4 21 bool "Avila"
76bbb002 22 select PCI
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23 help
24 Say 'Y' here if you want your kernel to support the Gateworks
25 Avila Network Platform. For more information on this platform,
26 see <file:Documentation/arm/IXP4xx>.
27
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28config MACH_LOFT
29 bool "Loft"
30 depends on MACH_AVILA
31 help
32 Say 'Y' here if you want your kernel to support the Giant
33 Shoulder Inc Loft board (a minor variation on the standard
34 Gateworks Avila Network Platform).
35
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36config ARCH_ADI_COYOTE
37 bool "Coyote"
76bbb002 38 select PCI
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39 help
40 Say 'Y' here if you want your kernel to support the ADI
41 Engineering Coyote Gateway Reference Platform. For more
42 information on this platform, see <file:Documentation/arm/IXP4xx>.
43
44config ARCH_IXDP425
45 bool "IXDP425"
46 help
47 Say 'Y' here if you want your kernel to support Intel's
48 IXDP425 Development Platform (Also known as Richfield).
49 For more information on this platform, see <file:Documentation/arm/IXP4xx>.
50
51config MACH_IXDPG425
52 bool "IXDPG425"
53 help
54 Say 'Y' here if you want your kernel to support Intel's
55 IXDPG425 Development Platform (Also known as Montajade).
56 For more information on this platform, see <file:Documentation/arm/IXP4xx>.
57
58config MACH_IXDP465
59 bool "IXDP465"
60 help
61 Say 'Y' here if you want your kernel to support Intel's
62 IXDP465 Development Platform (Also known as BMP).
7aa52f51 63 For more information on this platform, see <file:Documentation/arm/IXP4xx>.
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64
65
66#
67# IXCDP1100 is the exact same HW as IXDP425, but with a different machine
68# number from the bootloader due to marketing monkeys, so we just enable it
69# by default if IXDP425 is enabled.
70#
71config ARCH_IXCDP1100
72 bool
73 depends on ARCH_IXDP425
74 default y
75
76config ARCH_PRPMC1100
77 bool "PrPMC1100"
78 help
79 Say 'Y' here if you want your kernel to support the Motorola
80 PrPCM1100 Processor Mezanine Module. For more information on
81 this platform, see <file:Documentation/arm/IXP4xx>.
82
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83config MACH_NAS100D
84 bool
85 prompt "NAS100D"
76bbb002 86 select PCI
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87 help
88 Say 'Y' here if you want your kernel to support Iomega's
89 NAS 100d device. For more information on this platform,
90 see http://www.nslu2-linux.org/wiki/NAS100d/HomePage
91
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92#
93# Avila and IXDP share the same source for now. Will change in future
94#
95config ARCH_IXDP4XX
96 bool
0f185971 97 depends on ARCH_IXDP425 || MACH_IXDP465
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98 default y
99
100#
101# Certain registers and IRQs are only enabled if supporting IXP465 CPUs
102#
103config CPU_IXP46X
104 bool
105 depends on MACH_IXDP465
106 default y
107
108config MACH_GTWX5715
109 bool "Gemtek WX5715 (Linksys WRV54G)"
110 depends on ARCH_IXP4XX
76bbb002 111 select PCI
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112 help
113 This board is currently inside the Linksys WRV54G Gateways.
114
115 IXP425 - 266mhz
116 32mb SDRAM
117 8mb Flash
118 miniPCI slot 0 does not have a card connector soldered to the board
119 miniPCI slot 1 has an ISL3880 802.11g card (Prism54)
120 npe0 is connected to a Kendin KS8995M Switch (4 ports)
121 npe1 is the "wan" port
122 "Console" UART is available on J11 as console
123 "High Speed" UART is n/c (as far as I can tell)
124 20 Pin ARM/Xscale JTAG interface on J2
125
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126comment "IXP4xx Options"
127
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128config DMABOUNCE
129 bool
130 default y
131 depends on PCI
132
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133config IXP4XX_INDIRECT_PCI
134 bool "Use indirect PCI memory access"
76bbb002 135 depends on PCI
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136 help
137 IXP4xx provides two methods of accessing PCI memory space:
138
139 1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB).
140 To access PCI via this space, we simply ioremap() the BAR
141 into the kernel and we can use the standard read[bwl]/write[bwl]
142 macros. This is the preferred method due to speed but it
143 limits the system to just 64MB of PCI memory. This can be
3cb2fccc 144 problematic if using video cards and other memory-heavy devices.
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145
146 2) If > 64MB of memory space is required, the IXP4xx can be
147 configured to use indirect registers to access PCI This allows
148 for up to 128MB (0x48000000 to 0x4fffffff) of memory on the bus.
c41045a4 149 The disadvantage of this is that every PCI access requires
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150 three local register accesses plus a spinlock, but in some
151 cases the performance hit is acceptable. In addition, you cannot
152 mmap() PCI devices in this case due to the indirect nature
153 of the PCI window.
154
155 By default, the direct method is used. Choose this option if you
156 need to use the indirect method instead. If you don't know
157 what you need, leave this option unselected.
158
159endmenu
160
161endif
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