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1da177e4 LT |
1 | if ARCH_IXP4XX |
2 | ||
3 | config ARCH_SUPPORTS_BIG_ENDIAN | |
4 | bool | |
5 | default y | |
6 | ||
7 | menu "Intel IXP4xx Implementation Options" | |
8 | ||
9 | comment "IXP4xx Platforms" | |
10 | ||
a7918f39 AZ |
11 | config MACH_NSLU2 |
12 | bool | |
e7fcdb79 | 13 | prompt "Linksys NSLU2" |
76bbb002 | 14 | select PCI |
a7918f39 AZ |
15 | help |
16 | Say 'Y' here if you want your kernel to support Linksys's | |
17 | NSLU2 NAS device. For more information on this platform, | |
18 | see http://www.nslu2-linux.org | |
19 | ||
1da177e4 LT |
20 | config ARCH_AVILA |
21 | bool "Avila" | |
76bbb002 | 22 | select PCI |
1da177e4 LT |
23 | help |
24 | Say 'Y' here if you want your kernel to support the Gateworks | |
25 | Avila Network Platform. For more information on this platform, | |
26 | see <file:Documentation/arm/IXP4xx>. | |
27 | ||
28 | config ARCH_ADI_COYOTE | |
29 | bool "Coyote" | |
76bbb002 | 30 | select PCI |
1da177e4 LT |
31 | help |
32 | Say 'Y' here if you want your kernel to support the ADI | |
33 | Engineering Coyote Gateway Reference Platform. For more | |
34 | information on this platform, see <file:Documentation/arm/IXP4xx>. | |
35 | ||
36 | config ARCH_IXDP425 | |
37 | bool "IXDP425" | |
38 | help | |
39 | Say 'Y' here if you want your kernel to support Intel's | |
40 | IXDP425 Development Platform (Also known as Richfield). | |
41 | For more information on this platform, see <file:Documentation/arm/IXP4xx>. | |
42 | ||
43 | config MACH_IXDPG425 | |
44 | bool "IXDPG425" | |
45 | help | |
46 | Say 'Y' here if you want your kernel to support Intel's | |
47 | IXDPG425 Development Platform (Also known as Montajade). | |
48 | For more information on this platform, see <file:Documentation/arm/IXP4xx>. | |
49 | ||
50 | config MACH_IXDP465 | |
51 | bool "IXDP465" | |
52 | help | |
53 | Say 'Y' here if you want your kernel to support Intel's | |
54 | IXDP465 Development Platform (Also known as BMP). | |
7aa52f51 | 55 | For more information on this platform, see <file:Documentation/arm/IXP4xx>. |
1da177e4 LT |
56 | |
57 | ||
58 | # | |
59 | # IXCDP1100 is the exact same HW as IXDP425, but with a different machine | |
60 | # number from the bootloader due to marketing monkeys, so we just enable it | |
61 | # by default if IXDP425 is enabled. | |
62 | # | |
63 | config ARCH_IXCDP1100 | |
64 | bool | |
65 | depends on ARCH_IXDP425 | |
66 | default y | |
67 | ||
68 | config ARCH_PRPMC1100 | |
69 | bool "PrPMC1100" | |
70 | help | |
71 | Say 'Y' here if you want your kernel to support the Motorola | |
72 | PrPCM1100 Processor Mezanine Module. For more information on | |
73 | this platform, see <file:Documentation/arm/IXP4xx>. | |
74 | ||
3145d8a6 RW |
75 | config MACH_NAS100D |
76 | bool | |
77 | prompt "NAS100D" | |
76bbb002 | 78 | select PCI |
3145d8a6 RW |
79 | help |
80 | Say 'Y' here if you want your kernel to support Iomega's | |
81 | NAS 100d device. For more information on this platform, | |
82 | see http://www.nslu2-linux.org/wiki/NAS100d/HomePage | |
83 | ||
1da177e4 LT |
84 | # |
85 | # Avila and IXDP share the same source for now. Will change in future | |
86 | # | |
87 | config ARCH_IXDP4XX | |
88 | bool | |
89 | depends on ARCH_IXDP425 || ARCH_AVILA || MACH_IXDP465 | |
90 | default y | |
91 | ||
92 | # | |
93 | # Certain registers and IRQs are only enabled if supporting IXP465 CPUs | |
94 | # | |
95 | config CPU_IXP46X | |
96 | bool | |
97 | depends on MACH_IXDP465 | |
98 | default y | |
99 | ||
100 | config MACH_GTWX5715 | |
101 | bool "Gemtek WX5715 (Linksys WRV54G)" | |
102 | depends on ARCH_IXP4XX | |
76bbb002 | 103 | select PCI |
1da177e4 LT |
104 | help |
105 | This board is currently inside the Linksys WRV54G Gateways. | |
106 | ||
107 | IXP425 - 266mhz | |
108 | 32mb SDRAM | |
109 | 8mb Flash | |
110 | miniPCI slot 0 does not have a card connector soldered to the board | |
111 | miniPCI slot 1 has an ISL3880 802.11g card (Prism54) | |
112 | npe0 is connected to a Kendin KS8995M Switch (4 ports) | |
113 | npe1 is the "wan" port | |
114 | "Console" UART is available on J11 as console | |
115 | "High Speed" UART is n/c (as far as I can tell) | |
116 | 20 Pin ARM/Xscale JTAG interface on J2 | |
117 | ||
1da177e4 LT |
118 | comment "IXP4xx Options" |
119 | ||
76bbb002 DS |
120 | config DMABOUNCE |
121 | bool | |
122 | default y | |
123 | depends on PCI | |
124 | ||
1da177e4 LT |
125 | config IXP4XX_INDIRECT_PCI |
126 | bool "Use indirect PCI memory access" | |
76bbb002 | 127 | depends on PCI |
1da177e4 LT |
128 | help |
129 | IXP4xx provides two methods of accessing PCI memory space: | |
130 | ||
131 | 1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB). | |
132 | To access PCI via this space, we simply ioremap() the BAR | |
133 | into the kernel and we can use the standard read[bwl]/write[bwl] | |
134 | macros. This is the preferred method due to speed but it | |
135 | limits the system to just 64MB of PCI memory. This can be | |
3cb2fccc | 136 | problematic if using video cards and other memory-heavy devices. |
1da177e4 LT |
137 | |
138 | 2) If > 64MB of memory space is required, the IXP4xx can be | |
139 | configured to use indirect registers to access PCI This allows | |
140 | for up to 128MB (0x48000000 to 0x4fffffff) of memory on the bus. | |
c41045a4 | 141 | The disadvantage of this is that every PCI access requires |
1da177e4 LT |
142 | three local register accesses plus a spinlock, but in some |
143 | cases the performance hit is acceptable. In addition, you cannot | |
144 | mmap() PCI devices in this case due to the indirect nature | |
145 | of the PCI window. | |
146 | ||
147 | By default, the direct method is used. Choose this option if you | |
148 | need to use the indirect method instead. If you don't know | |
149 | what you need, leave this option unselected. | |
150 | ||
151 | endmenu | |
152 | ||
153 | endif |