Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * arch/arm/mach-ixp4xx/common-pci.c | |
3 | * | |
4 | * IXP4XX PCI routines for all platforms | |
5 | * | |
6 | * Maintainer: Deepak Saxena <dsaxena@plexity.net> | |
7 | * | |
8 | * Copyright (C) 2002 Intel Corporation. | |
9 | * Copyright (C) 2003 Greg Ungerer <gerg@snapgear.com> | |
10 | * Copyright (C) 2003-2004 MontaVista Software, Inc. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | * | |
16 | */ | |
17 | ||
18 | #include <linux/sched.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/pci.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/mm.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/ioport.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/device.h> | |
28 | #include <asm/dma-mapping.h> | |
29 | ||
30 | #include <asm/io.h> | |
31 | #include <asm/irq.h> | |
32 | #include <asm/sizes.h> | |
33 | #include <asm/system.h> | |
34 | #include <asm/mach/pci.h> | |
35 | #include <asm/hardware.h> | |
36 | ||
37 | ||
38 | /* | |
39 | * IXP4xx PCI read function is dependent on whether we are | |
40 | * running A0 or B0 (AppleGate) silicon. | |
41 | */ | |
42 | int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data); | |
43 | ||
44 | /* | |
45 | * Base address for PCI regsiter region | |
46 | */ | |
47 | unsigned long ixp4xx_pci_reg_base = 0; | |
48 | ||
49 | /* | |
50 | * PCI cfg an I/O routines are done by programming a | |
51 | * command/byte enable register, and then read/writing | |
52 | * the data from a data regsiter. We need to ensure | |
53 | * these transactions are atomic or we will end up | |
54 | * with corrupt data on the bus or in a driver. | |
55 | */ | |
56 | static DEFINE_SPINLOCK(ixp4xx_pci_lock); | |
57 | ||
58 | /* | |
59 | * Read from PCI config space | |
60 | */ | |
61 | static void crp_read(u32 ad_cbe, u32 *data) | |
62 | { | |
63 | unsigned long flags; | |
64 | spin_lock_irqsave(&ixp4xx_pci_lock, flags); | |
65 | *PCI_CRP_AD_CBE = ad_cbe; | |
66 | *data = *PCI_CRP_RDATA; | |
67 | spin_unlock_irqrestore(&ixp4xx_pci_lock, flags); | |
68 | } | |
69 | ||
70 | /* | |
71 | * Write to PCI config space | |
72 | */ | |
73 | static void crp_write(u32 ad_cbe, u32 data) | |
74 | { | |
75 | unsigned long flags; | |
76 | spin_lock_irqsave(&ixp4xx_pci_lock, flags); | |
77 | *PCI_CRP_AD_CBE = CRP_AD_CBE_WRITE | ad_cbe; | |
78 | *PCI_CRP_WDATA = data; | |
79 | spin_unlock_irqrestore(&ixp4xx_pci_lock, flags); | |
80 | } | |
81 | ||
82 | static inline int check_master_abort(void) | |
83 | { | |
84 | /* check Master Abort bit after access */ | |
85 | unsigned long isr = *PCI_ISR; | |
86 | ||
87 | if (isr & PCI_ISR_PFE) { | |
88 | /* make sure the Master Abort bit is reset */ | |
89 | *PCI_ISR = PCI_ISR_PFE; | |
90 | pr_debug("%s failed\n", __FUNCTION__); | |
91 | return 1; | |
92 | } | |
93 | ||
94 | return 0; | |
95 | } | |
96 | ||
97 | int ixp4xx_pci_read_errata(u32 addr, u32 cmd, u32* data) | |
98 | { | |
99 | unsigned long flags; | |
100 | int retval = 0; | |
101 | int i; | |
102 | ||
103 | spin_lock_irqsave(&ixp4xx_pci_lock, flags); | |
104 | ||
105 | *PCI_NP_AD = addr; | |
106 | ||
107 | /* | |
108 | * PCI workaround - only works if NP PCI space reads have | |
109 | * no side effects!!! Read 8 times. last one will be good. | |
110 | */ | |
111 | for (i = 0; i < 8; i++) { | |
112 | *PCI_NP_CBE = cmd; | |
113 | *data = *PCI_NP_RDATA; | |
114 | *data = *PCI_NP_RDATA; | |
115 | } | |
116 | ||
117 | if(check_master_abort()) | |
118 | retval = 1; | |
119 | ||
120 | spin_unlock_irqrestore(&ixp4xx_pci_lock, flags); | |
121 | return retval; | |
122 | } | |
123 | ||
124 | int ixp4xx_pci_read_no_errata(u32 addr, u32 cmd, u32* data) | |
125 | { | |
126 | unsigned long flags; | |
127 | int retval = 0; | |
128 | ||
129 | spin_lock_irqsave(&ixp4xx_pci_lock, flags); | |
130 | ||
131 | *PCI_NP_AD = addr; | |
132 | ||
133 | /* set up and execute the read */ | |
134 | *PCI_NP_CBE = cmd; | |
135 | ||
136 | /* the result of the read is now in NP_RDATA */ | |
137 | *data = *PCI_NP_RDATA; | |
138 | ||
139 | if(check_master_abort()) | |
140 | retval = 1; | |
141 | ||
142 | spin_unlock_irqrestore(&ixp4xx_pci_lock, flags); | |
143 | return retval; | |
144 | } | |
145 | ||
146 | int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data) | |
147 | { | |
148 | unsigned long flags; | |
149 | int retval = 0; | |
150 | ||
151 | spin_lock_irqsave(&ixp4xx_pci_lock, flags); | |
152 | ||
153 | *PCI_NP_AD = addr; | |
154 | ||
155 | /* set up the write */ | |
156 | *PCI_NP_CBE = cmd; | |
157 | ||
158 | /* execute the write by writing to NP_WDATA */ | |
159 | *PCI_NP_WDATA = data; | |
160 | ||
161 | if(check_master_abort()) | |
162 | retval = 1; | |
163 | ||
164 | spin_unlock_irqrestore(&ixp4xx_pci_lock, flags); | |
165 | return retval; | |
166 | } | |
167 | ||
168 | static u32 ixp4xx_config_addr(u8 bus_num, u16 devfn, int where) | |
169 | { | |
170 | u32 addr; | |
171 | if (!bus_num) { | |
172 | /* type 0 */ | |
173 | addr = BIT(32-PCI_SLOT(devfn)) | ((PCI_FUNC(devfn)) << 8) | | |
174 | (where & ~3); | |
175 | } else { | |
176 | /* type 1 */ | |
177 | addr = (bus_num << 16) | ((PCI_SLOT(devfn)) << 11) | | |
178 | ((PCI_FUNC(devfn)) << 8) | (where & ~3) | 1; | |
179 | } | |
180 | return addr; | |
181 | } | |
182 | ||
183 | /* | |
184 | * Mask table, bits to mask for quantity of size 1, 2 or 4 bytes. | |
185 | * 0 and 3 are not valid indexes... | |
186 | */ | |
187 | static u32 bytemask[] = { | |
188 | /*0*/ 0, | |
189 | /*1*/ 0xff, | |
190 | /*2*/ 0xffff, | |
191 | /*3*/ 0, | |
192 | /*4*/ 0xffffffff, | |
193 | }; | |
194 | ||
195 | static u32 local_byte_lane_enable_bits(u32 n, int size) | |
196 | { | |
197 | if (size == 1) | |
198 | return (0xf & ~BIT(n)) << CRP_AD_CBE_BESL; | |
199 | if (size == 2) | |
200 | return (0xf & ~(BIT(n) | BIT(n+1))) << CRP_AD_CBE_BESL; | |
201 | if (size == 4) | |
202 | return 0; | |
203 | return 0xffffffff; | |
204 | } | |
205 | ||
206 | static int local_read_config(int where, int size, u32 *value) | |
207 | { | |
208 | u32 n, data; | |
209 | pr_debug("local_read_config from %d size %d\n", where, size); | |
210 | n = where % 4; | |
211 | crp_read(where & ~3, &data); | |
212 | *value = (data >> (8*n)) & bytemask[size]; | |
213 | pr_debug("local_read_config read %#x\n", *value); | |
214 | return PCIBIOS_SUCCESSFUL; | |
215 | } | |
216 | ||
217 | static int local_write_config(int where, int size, u32 value) | |
218 | { | |
219 | u32 n, byte_enables, data; | |
220 | pr_debug("local_write_config %#x to %d size %d\n", value, where, size); | |
221 | n = where % 4; | |
222 | byte_enables = local_byte_lane_enable_bits(n, size); | |
223 | if (byte_enables == 0xffffffff) | |
224 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
225 | data = value << (8*n); | |
226 | crp_write((where & ~3) | byte_enables, data); | |
227 | return PCIBIOS_SUCCESSFUL; | |
228 | } | |
229 | ||
230 | static u32 byte_lane_enable_bits(u32 n, int size) | |
231 | { | |
232 | if (size == 1) | |
233 | return (0xf & ~BIT(n)) << 4; | |
234 | if (size == 2) | |
235 | return (0xf & ~(BIT(n) | BIT(n+1))) << 4; | |
236 | if (size == 4) | |
237 | return 0; | |
238 | return 0xffffffff; | |
239 | } | |
240 | ||
241 | static int ixp4xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value) | |
242 | { | |
243 | u32 n, byte_enables, addr, data; | |
244 | u8 bus_num = bus->number; | |
245 | ||
246 | pr_debug("read_config from %d size %d dev %d:%d:%d\n", where, size, | |
247 | bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn)); | |
248 | ||
249 | *value = 0xffffffff; | |
250 | n = where % 4; | |
251 | byte_enables = byte_lane_enable_bits(n, size); | |
252 | if (byte_enables == 0xffffffff) | |
253 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
254 | ||
255 | addr = ixp4xx_config_addr(bus_num, devfn, where); | |
256 | if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_CONFIGREAD, &data)) | |
257 | return PCIBIOS_DEVICE_NOT_FOUND; | |
258 | ||
259 | *value = (data >> (8*n)) & bytemask[size]; | |
260 | pr_debug("read_config_byte read %#x\n", *value); | |
261 | return PCIBIOS_SUCCESSFUL; | |
262 | } | |
263 | ||
264 | static int ixp4xx_pci_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value) | |
265 | { | |
266 | u32 n, byte_enables, addr, data; | |
267 | u8 bus_num = bus->number; | |
268 | ||
269 | pr_debug("write_config_byte %#x to %d size %d dev %d:%d:%d\n", value, where, | |
270 | size, bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn)); | |
271 | ||
272 | n = where % 4; | |
273 | byte_enables = byte_lane_enable_bits(n, size); | |
274 | if (byte_enables == 0xffffffff) | |
275 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
276 | ||
277 | addr = ixp4xx_config_addr(bus_num, devfn, where); | |
278 | data = value << (8*n); | |
279 | if (ixp4xx_pci_write(addr, byte_enables | NP_CMD_CONFIGWRITE, data)) | |
280 | return PCIBIOS_DEVICE_NOT_FOUND; | |
281 | ||
282 | return PCIBIOS_SUCCESSFUL; | |
283 | } | |
284 | ||
285 | struct pci_ops ixp4xx_ops = { | |
286 | .read = ixp4xx_pci_read_config, | |
287 | .write = ixp4xx_pci_write_config, | |
288 | }; | |
289 | ||
290 | /* | |
291 | * PCI abort handler | |
292 | */ | |
293 | static int abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs) | |
294 | { | |
295 | u32 isr, status; | |
296 | ||
297 | isr = *PCI_ISR; | |
298 | local_read_config(PCI_STATUS, 2, &status); | |
299 | pr_debug("PCI: abort_handler addr = %#lx, isr = %#x, " | |
300 | "status = %#x\n", addr, isr, status); | |
301 | ||
302 | /* make sure the Master Abort bit is reset */ | |
303 | *PCI_ISR = PCI_ISR_PFE; | |
304 | status |= PCI_STATUS_REC_MASTER_ABORT; | |
305 | local_write_config(PCI_STATUS, 2, status); | |
306 | ||
307 | /* | |
308 | * If it was an imprecise abort, then we need to correct the | |
309 | * return address to be _after_ the instruction. | |
310 | */ | |
311 | if (fsr & (1 << 10)) | |
312 | regs->ARM_pc += 4; | |
313 | ||
314 | return 0; | |
315 | } | |
316 | ||
317 | ||
318 | /* | |
319 | * Setup DMA mask to 64MB on PCI devices. Ignore all other devices. | |
320 | */ | |
321 | static int ixp4xx_pci_platform_notify(struct device *dev) | |
322 | { | |
323 | if(dev->bus == &pci_bus_type) { | |
324 | *dev->dma_mask = SZ_64M - 1; | |
325 | dev->coherent_dma_mask = SZ_64M - 1; | |
326 | dmabounce_register_dev(dev, 2048, 4096); | |
327 | } | |
328 | return 0; | |
329 | } | |
330 | ||
331 | static int ixp4xx_pci_platform_notify_remove(struct device *dev) | |
332 | { | |
333 | if(dev->bus == &pci_bus_type) { | |
334 | dmabounce_unregister_dev(dev); | |
335 | } | |
336 | return 0; | |
337 | } | |
338 | ||
339 | int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size) | |
340 | { | |
341 | return (dev->bus == &pci_bus_type ) && ((dma_addr + size) >= SZ_64M); | |
342 | } | |
343 | ||
313cbb55 RW |
344 | /* |
345 | * Only first 64MB of memory can be accessed via PCI. | |
346 | * We use GFP_DMA to allocate safe buffers to do map/unmap. | |
347 | * This is really ugly and we need a better way of specifying | |
348 | * DMA-capable regions of memory. | |
349 | */ | |
350 | void __init ixp4xx_adjust_zones(int node, unsigned long *zone_size, | |
351 | unsigned long *zhole_size) | |
352 | { | |
353 | unsigned int sz = SZ_64M >> PAGE_SHIFT; | |
354 | ||
355 | /* | |
356 | * Only adjust if > 64M on current system | |
357 | */ | |
358 | if (node || (zone_size[0] <= sz)) | |
359 | return; | |
360 | ||
361 | zone_size[1] = zone_size[0] - sz; | |
362 | zone_size[0] = sz; | |
363 | zhole_size[1] = zhole_size[0]; | |
364 | zhole_size[0] = 0; | |
365 | } | |
366 | ||
1da177e4 LT |
367 | void __init ixp4xx_pci_preinit(void) |
368 | { | |
369 | unsigned long processor_id; | |
370 | ||
371 | asm("mrc p15, 0, %0, cr0, cr0, 0;" : "=r"(processor_id) :); | |
372 | ||
373 | /* | |
374 | * Determine which PCI read method to use. | |
375 | * Rev 0 IXP425 requires workaround. | |
376 | */ | |
377 | if (!(processor_id & 0xf) && !cpu_is_ixp46x()) { | |
378 | printk("PCI: IXP42x A0 silicon detected - " | |
379 | "PCI Non-Prefetch Workaround Enabled\n"); | |
380 | ixp4xx_pci_read = ixp4xx_pci_read_errata; | |
381 | } else | |
382 | ixp4xx_pci_read = ixp4xx_pci_read_no_errata; | |
383 | ||
384 | ||
385 | /* hook in our fault handler for PCI errors */ | |
386 | hook_fault_code(16+6, abort_handler, SIGBUS, "imprecise external abort"); | |
387 | ||
388 | pr_debug("setup PCI-AHB(inbound) and AHB-PCI(outbound) address mappings\n"); | |
389 | ||
390 | /* | |
391 | * We use identity AHB->PCI address translation | |
392 | * in the 0x48000000 to 0x4bffffff address space | |
393 | */ | |
394 | *PCI_PCIMEMBASE = 0x48494A4B; | |
395 | ||
396 | /* | |
397 | * We also use identity PCI->AHB address translation | |
398 | * in 4 16MB BARs that begin at the physical memory start | |
399 | */ | |
400 | *PCI_AHBMEMBASE = (PHYS_OFFSET & 0xFF000000) + | |
401 | ((PHYS_OFFSET & 0xFF000000) >> 8) + | |
402 | ((PHYS_OFFSET & 0xFF000000) >> 16) + | |
403 | ((PHYS_OFFSET & 0xFF000000) >> 24) + | |
404 | 0x00010203; | |
405 | ||
406 | if (*PCI_CSR & PCI_CSR_HOST) { | |
407 | printk("PCI: IXP4xx is host\n"); | |
408 | ||
409 | pr_debug("setup BARs in controller\n"); | |
410 | ||
411 | /* | |
412 | * We configure the PCI inbound memory windows to be | |
413 | * 1:1 mapped to SDRAM | |
414 | */ | |
415 | local_write_config(PCI_BASE_ADDRESS_0, 4, PHYS_OFFSET + 0x00000000); | |
416 | local_write_config(PCI_BASE_ADDRESS_1, 4, PHYS_OFFSET + 0x01000000); | |
417 | local_write_config(PCI_BASE_ADDRESS_2, 4, PHYS_OFFSET + 0x02000000); | |
418 | local_write_config(PCI_BASE_ADDRESS_3, 4, PHYS_OFFSET + 0x03000000); | |
419 | ||
420 | /* | |
421 | * Enable CSR window at 0xff000000. | |
422 | */ | |
423 | local_write_config(PCI_BASE_ADDRESS_4, 4, 0xff000008); | |
424 | ||
425 | /* | |
426 | * Enable the IO window to be way up high, at 0xfffffc00 | |
427 | */ | |
428 | local_write_config(PCI_BASE_ADDRESS_5, 4, 0xfffffc01); | |
429 | } else { | |
430 | printk("PCI: IXP4xx is target - No bus scan performed\n"); | |
431 | } | |
432 | ||
433 | printk("PCI: IXP4xx Using %s access for memory space\n", | |
434 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | |
435 | "direct" | |
436 | #else | |
437 | "indirect" | |
438 | #endif | |
439 | ); | |
440 | ||
441 | pr_debug("clear error bits in ISR\n"); | |
442 | *PCI_ISR = PCI_ISR_PSE | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE; | |
443 | ||
444 | /* | |
445 | * Set Initialize Complete in PCI Control Register: allow IXP4XX to | |
446 | * respond to PCI configuration cycles. Specify that the AHB bus is | |
447 | * operating in big endian mode. Set up byte lane swapping between | |
448 | * little-endian PCI and the big-endian AHB bus | |
449 | */ | |
450 | #ifdef __ARMEB__ | |
451 | *PCI_CSR = PCI_CSR_IC | PCI_CSR_ABE | PCI_CSR_PDS | PCI_CSR_ADS; | |
452 | #else | |
84613387 | 453 | *PCI_CSR = PCI_CSR_IC | PCI_CSR_ABE; |
1da177e4 LT |
454 | #endif |
455 | ||
456 | pr_debug("DONE\n"); | |
457 | } | |
458 | ||
459 | int ixp4xx_setup(int nr, struct pci_sys_data *sys) | |
460 | { | |
461 | struct resource *res; | |
462 | ||
463 | if (nr >= 1) | |
464 | return 0; | |
465 | ||
d2a02b93 | 466 | res = kzalloc(sizeof(*res) * 2, GFP_KERNEL); |
1da177e4 LT |
467 | if (res == NULL) { |
468 | /* | |
469 | * If we're out of memory this early, something is wrong, | |
470 | * so we might as well catch it here. | |
471 | */ | |
472 | panic("PCI: unable to allocate resources?\n"); | |
473 | } | |
1da177e4 LT |
474 | |
475 | local_write_config(PCI_COMMAND, 2, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); | |
476 | ||
477 | res[0].name = "PCI I/O Space"; | |
450008b5 DS |
478 | res[0].start = 0x00000000; |
479 | res[0].end = 0x0000ffff; | |
1da177e4 LT |
480 | res[0].flags = IORESOURCE_IO; |
481 | ||
482 | res[1].name = "PCI Memory Space"; | |
483 | res[1].start = 0x48000000; | |
484 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | |
485 | res[1].end = 0x4bffffff; | |
486 | #else | |
487 | res[1].end = 0x4fffffff; | |
488 | #endif | |
489 | res[1].flags = IORESOURCE_MEM; | |
490 | ||
491 | request_resource(&ioport_resource, &res[0]); | |
492 | request_resource(&iomem_resource, &res[1]); | |
493 | ||
494 | sys->resource[0] = &res[0]; | |
495 | sys->resource[1] = &res[1]; | |
496 | sys->resource[2] = NULL; | |
497 | ||
498 | platform_notify = ixp4xx_pci_platform_notify; | |
499 | platform_notify_remove = ixp4xx_pci_platform_notify_remove; | |
500 | ||
501 | return 1; | |
502 | } | |
503 | ||
504 | struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys) | |
505 | { | |
506 | return pci_scan_bus(sys->busnr, &ixp4xx_ops, sys); | |
507 | } | |
508 | ||
509 | /* | |
510 | * We override these so we properly do dmabounce otherwise drivers | |
511 | * are able to set the dma_mask to 0xffffffff and we can no longer | |
512 | * trap bounces. :( | |
513 | * | |
514 | * We just return true on everyhing except for < 64MB in which case | |
515 | * we will fail miseralby and die since we can't handle that case. | |
516 | */ | |
517 | int | |
518 | pci_set_dma_mask(struct pci_dev *dev, u64 mask) | |
519 | { | |
520 | if (mask >= SZ_64M - 1 ) | |
521 | return 0; | |
522 | ||
523 | return -EIO; | |
524 | } | |
525 | ||
1da177e4 LT |
526 | int |
527 | pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) | |
528 | { | |
529 | if (mask >= SZ_64M - 1 ) | |
530 | return 0; | |
531 | ||
532 | return -EIO; | |
533 | } | |
534 | ||
1da177e4 LT |
535 | EXPORT_SYMBOL(ixp4xx_pci_read); |
536 | EXPORT_SYMBOL(ixp4xx_pci_write); | |
537 |