ixp4xx: Declare MODULE_FIRMWARE usage
[deliverable/linux.git] / arch / arm / mach-ixp4xx / common.c
CommitLineData
1da177e4
LT
1/*
2 * arch/arm/mach-ixp4xx/common.c
3 *
4 * Generic code shared across all IXP4XX platforms
5 *
6 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
7 *
8 * Copyright 2002 (c) Intel Corporation
9 * Copyright 2003-2004 (c) MontaVista, Software, Inc.
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15
1da177e4
LT
16#include <linux/kernel.h>
17#include <linux/mm.h>
18#include <linux/init.h>
19#include <linux/serial.h>
1da177e4 20#include <linux/tty.h>
d052d1be 21#include <linux/platform_device.h>
1da177e4 22#include <linux/serial_core.h>
1da177e4
LT
23#include <linux/interrupt.h>
24#include <linux/bitops.h>
25#include <linux/time.h>
26#include <linux/timex.h>
84904d0e 27#include <linux/clocksource.h>
e32f1502 28#include <linux/clockchips.h>
fced80c7 29#include <linux/io.h>
dc28094b 30#include <linux/export.h>
9dde0ae3 31#include <linux/gpio.h>
1da177e4 32
a09e64fb
RK
33#include <mach/udc.h>
34#include <mach/hardware.h>
f449588c 35#include <mach/io.h>
1da177e4 36#include <asm/uaccess.h>
1da177e4
LT
37#include <asm/pgtable.h>
38#include <asm/page.h>
39#include <asm/irq.h>
5b0d495c 40#include <asm/sched_clock.h>
86dfe446 41#include <asm/system_misc.h>
1da177e4
LT
42
43#include <asm/mach/map.h>
44#include <asm/mach/irq.h>
45#include <asm/mach/time.h>
46
ceb69a89
MP
47static void __init ixp4xx_clocksource_init(void);
48static void __init ixp4xx_clockevent_init(void);
e32f1502 49static struct clock_event_device clockevent_ixp4xx;
f9a8ca1c 50
1da177e4
LT
51/*************************************************************************
52 * IXP4xx chipset I/O mapping
53 *************************************************************************/
54static struct map_desc ixp4xx_io_desc[] __initdata = {
55 { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
13ec32f4 56 .virtual = (unsigned long)IXP4XX_PERIPHERAL_BASE_VIRT,
87fe04bd 57 .pfn = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS),
1da177e4
LT
58 .length = IXP4XX_PERIPHERAL_REGION_SIZE,
59 .type = MT_DEVICE
60 }, { /* Expansion Bus Config Registers */
13ec32f4 61 .virtual = (unsigned long)IXP4XX_EXP_CFG_BASE_VIRT,
87fe04bd 62 .pfn = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS),
1da177e4
LT
63 .length = IXP4XX_EXP_CFG_REGION_SIZE,
64 .type = MT_DEVICE
65 }, { /* PCI Registers */
13ec32f4 66 .virtual = (unsigned long)IXP4XX_PCI_CFG_BASE_VIRT,
87fe04bd 67 .pfn = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
1da177e4
LT
68 .length = IXP4XX_PCI_CFG_REGION_SIZE,
69 .type = MT_DEVICE
5932ae3f
DS
70 },
71#ifdef CONFIG_DEBUG_LL
72 { /* Debug UART mapping */
13ec32f4 73 .virtual = (unsigned long)IXP4XX_DEBUG_UART_BASE_VIRT,
87fe04bd 74 .pfn = __phys_to_pfn(IXP4XX_DEBUG_UART_BASE_PHYS),
5932ae3f
DS
75 .length = IXP4XX_DEBUG_UART_REGION_SIZE,
76 .type = MT_DEVICE
1da177e4 77 }
5932ae3f 78#endif
1da177e4
LT
79};
80
81void __init ixp4xx_map_io(void)
82{
83 iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc));
84}
85
86
87/*************************************************************************
88 * IXP4xx chipset IRQ handling
89 *
90 * TODO: GPIO IRQs should be marked invalid until the user of the IRQ
91 * (be it PCI or something else) configures that GPIO line
92 * as an IRQ.
93 **************************************************************************/
bdf82b59
DS
94enum ixp4xx_irq_type {
95 IXP4XX_IRQ_LEVEL, IXP4XX_IRQ_EDGE
96};
97
984d115b
KH
98/* Each bit represents an IRQ: 1: edge-triggered, 0: level triggered */
99static unsigned long long ixp4xx_irq_edge = 0;
bdf82b59
DS
100
101/*
102 * IRQ -> GPIO mapping table
103 */
6cc1b658 104static signed char irq2gpio[32] = {
bdf82b59
DS
105 -1, -1, -1, -1, -1, -1, 0, 1,
106 -1, -1, -1, -1, -1, -1, -1, -1,
107 -1, -1, -1, 2, 3, 4, 5, 6,
108 7, 8, 9, 10, 11, 12, -1, -1,
109};
110
9dde0ae3 111static int ixp4xx_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
25735d10
MS
112{
113 int irq;
114
115 for (irq = 0; irq < 32; irq++) {
116 if (irq2gpio[irq] == gpio)
117 return irq;
118 }
119 return -EINVAL;
120}
25735d10 121
efec194f 122int irq_to_gpio(unsigned int irq)
25735d10
MS
123{
124 int gpio = (irq < 32) ? irq2gpio[irq] : -EINVAL;
125
126 if (gpio == -1)
127 return -EINVAL;
128
129 return gpio;
130}
131EXPORT_SYMBOL(irq_to_gpio);
132
ee04087a 133static int ixp4xx_set_irq_type(struct irq_data *d, unsigned int type)
bdf82b59 134{
ee04087a 135 int line = irq2gpio[d->irq];
bdf82b59
DS
136 u32 int_style;
137 enum ixp4xx_irq_type irq_type;
138 volatile u32 *int_reg;
139
140 /*
141 * Only for GPIO IRQs
142 */
143 if (line < 0)
144 return -EINVAL;
145