Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * arch/arm/mach-ixp4xx/common.c | |
3 | * | |
4 | * Generic code shared across all IXP4XX platforms | |
5 | * | |
6 | * Maintainer: Deepak Saxena <dsaxena@plexity.net> | |
7 | * | |
8 | * Copyright 2002 (c) Intel Corporation | |
9 | * Copyright 2003-2004 (c) MontaVista, Software, Inc. | |
10 | * | |
11 | * This file is licensed under the terms of the GNU General Public | |
12 | * License version 2. This program is licensed "as is" without any | |
13 | * warranty of any kind, whether express or implied. | |
14 | */ | |
15 | ||
1da177e4 LT |
16 | #include <linux/kernel.h> |
17 | #include <linux/mm.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/serial.h> | |
20 | #include <linux/sched.h> | |
21 | #include <linux/tty.h> | |
d052d1be | 22 | #include <linux/platform_device.h> |
1da177e4 | 23 | #include <linux/serial_core.h> |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/bitops.h> | |
26 | #include <linux/time.h> | |
27 | #include <linux/timex.h> | |
84904d0e | 28 | #include <linux/clocksource.h> |
e32f1502 | 29 | #include <linux/clockchips.h> |
fced80c7 | 30 | #include <linux/io.h> |
1da177e4 | 31 | |
a09e64fb RK |
32 | #include <mach/udc.h> |
33 | #include <mach/hardware.h> | |
1da177e4 | 34 | #include <asm/uaccess.h> |
1da177e4 LT |
35 | #include <asm/pgtable.h> |
36 | #include <asm/page.h> | |
37 | #include <asm/irq.h> | |
38 | ||
39 | #include <asm/mach/map.h> | |
40 | #include <asm/mach/irq.h> | |
41 | #include <asm/mach/time.h> | |
42 | ||
ceb69a89 MP |
43 | static void __init ixp4xx_clocksource_init(void); |
44 | static void __init ixp4xx_clockevent_init(void); | |
e32f1502 | 45 | static struct clock_event_device clockevent_ixp4xx; |
f9a8ca1c | 46 | |
1da177e4 LT |
47 | /************************************************************************* |
48 | * IXP4xx chipset I/O mapping | |
49 | *************************************************************************/ | |
50 | static struct map_desc ixp4xx_io_desc[] __initdata = { | |
51 | { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */ | |
52 | .virtual = IXP4XX_PERIPHERAL_BASE_VIRT, | |
87fe04bd | 53 | .pfn = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS), |
1da177e4 LT |
54 | .length = IXP4XX_PERIPHERAL_REGION_SIZE, |
55 | .type = MT_DEVICE | |
56 | }, { /* Expansion Bus Config Registers */ | |
57 | .virtual = IXP4XX_EXP_CFG_BASE_VIRT, | |
87fe04bd | 58 | .pfn = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS), |
1da177e4 LT |
59 | .length = IXP4XX_EXP_CFG_REGION_SIZE, |
60 | .type = MT_DEVICE | |
61 | }, { /* PCI Registers */ | |
62 | .virtual = IXP4XX_PCI_CFG_BASE_VIRT, | |
87fe04bd | 63 | .pfn = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS), |
1da177e4 LT |
64 | .length = IXP4XX_PCI_CFG_REGION_SIZE, |
65 | .type = MT_DEVICE | |
5932ae3f DS |
66 | }, |
67 | #ifdef CONFIG_DEBUG_LL | |
68 | { /* Debug UART mapping */ | |
69 | .virtual = IXP4XX_DEBUG_UART_BASE_VIRT, | |
87fe04bd | 70 | .pfn = __phys_to_pfn(IXP4XX_DEBUG_UART_BASE_PHYS), |
5932ae3f DS |
71 | .length = IXP4XX_DEBUG_UART_REGION_SIZE, |
72 | .type = MT_DEVICE | |
1da177e4 | 73 | } |
5932ae3f | 74 | #endif |
1da177e4 LT |
75 | }; |
76 | ||
77 | void __init ixp4xx_map_io(void) | |
78 | { | |
79 | iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc)); | |
80 | } | |
81 | ||
82 | ||
83 | /************************************************************************* | |
84 | * IXP4xx chipset IRQ handling | |
85 | * | |
86 | * TODO: GPIO IRQs should be marked invalid until the user of the IRQ | |
87 | * (be it PCI or something else) configures that GPIO line | |
88 | * as an IRQ. | |
89 | **************************************************************************/ | |
bdf82b59 DS |
90 | enum ixp4xx_irq_type { |
91 | IXP4XX_IRQ_LEVEL, IXP4XX_IRQ_EDGE | |
92 | }; | |
93 | ||
984d115b KH |
94 | /* Each bit represents an IRQ: 1: edge-triggered, 0: level triggered */ |
95 | static unsigned long long ixp4xx_irq_edge = 0; | |
bdf82b59 DS |
96 | |
97 | /* | |
98 | * IRQ -> GPIO mapping table | |
99 | */ | |
6cc1b658 | 100 | static signed char irq2gpio[32] = { |
bdf82b59 DS |
101 | -1, -1, -1, -1, -1, -1, 0, 1, |
102 | -1, -1, -1, -1, -1, -1, -1, -1, | |
103 | -1, -1, -1, 2, 3, 4, 5, 6, | |
104 | 7, 8, 9, 10, 11, 12, -1, -1, | |
105 | }; | |
106 | ||
25735d10 MS |
107 | int gpio_to_irq(int gpio) |
108 | { | |
109 | int irq; | |
110 | ||
111 | for (irq = 0; irq < 32; irq++) { | |
112 | if (irq2gpio[irq] == gpio) | |
113 | return irq; | |
114 | } | |
115 | return -EINVAL; | |
116 | } | |
117 | EXPORT_SYMBOL(gpio_to_irq); | |
118 | ||
efec194f | 119 | int irq_to_gpio(unsigned int irq) |
25735d10 MS |
120 | { |
121 | int gpio = (irq < 32) ? irq2gpio[irq] : -EINVAL; | |
122 | ||
123 | if (gpio == -1) | |
124 | return -EINVAL; | |
125 | ||
126 | return gpio; | |
127 | } | |
128 | EXPORT_SYMBOL(irq_to_gpio); | |
129 | ||
bdf82b59 DS |
130 | static int ixp4xx_set_irq_type(unsigned int irq, unsigned int type) |
131 | { | |
132 | int line = irq2gpio[irq]; | |
133 | u32 int_style; | |
134 | enum ixp4xx_irq_type irq_type; | |
135 | volatile u32 *int_reg; | |
136 | ||
137 | /* | |
138 | * Only for GPIO IRQs | |
139 | */ | |
140 | if (line < 0) | |
141 | return -EINVAL; | |
142 |