Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * arch/arm/mach-ixp4xx/common.c | |
3 | * | |
4 | * Generic code shared across all IXP4XX platforms | |
5 | * | |
6 | * Maintainer: Deepak Saxena <dsaxena@plexity.net> | |
7 | * | |
8 | * Copyright 2002 (c) Intel Corporation | |
9 | * Copyright 2003-2004 (c) MontaVista, Software, Inc. | |
10 | * | |
11 | * This file is licensed under the terms of the GNU General Public | |
12 | * License version 2. This program is licensed "as is" without any | |
13 | * warranty of any kind, whether express or implied. | |
14 | */ | |
15 | ||
1da177e4 LT |
16 | #include <linux/kernel.h> |
17 | #include <linux/mm.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/serial.h> | |
1da177e4 | 20 | #include <linux/tty.h> |
d052d1be | 21 | #include <linux/platform_device.h> |
1da177e4 | 22 | #include <linux/serial_core.h> |
1da177e4 LT |
23 | #include <linux/interrupt.h> |
24 | #include <linux/bitops.h> | |
25 | #include <linux/time.h> | |
26 | #include <linux/timex.h> | |
84904d0e | 27 | #include <linux/clocksource.h> |
e32f1502 | 28 | #include <linux/clockchips.h> |
fced80c7 | 29 | #include <linux/io.h> |
dc28094b | 30 | #include <linux/export.h> |
9dde0ae3 | 31 | #include <linux/gpio.h> |
f7b861b7 | 32 | #include <linux/cpu.h> |
38ff87f7 | 33 | #include <linux/sched_clock.h> |
1da177e4 | 34 | |
a09e64fb RK |
35 | #include <mach/udc.h> |
36 | #include <mach/hardware.h> | |
f449588c | 37 | #include <mach/io.h> |
1da177e4 | 38 | #include <asm/uaccess.h> |
1da177e4 LT |
39 | #include <asm/pgtable.h> |
40 | #include <asm/page.h> | |
41 | #include <asm/irq.h> | |
86dfe446 | 42 | #include <asm/system_misc.h> |
1da177e4 LT |
43 | |
44 | #include <asm/mach/map.h> | |
45 | #include <asm/mach/irq.h> | |
46 | #include <asm/mach/time.h> | |
47 | ||
ceb69a89 MP |
48 | static void __init ixp4xx_clocksource_init(void); |
49 | static void __init ixp4xx_clockevent_init(void); | |
e32f1502 | 50 | static struct clock_event_device clockevent_ixp4xx; |
f9a8ca1c | 51 | |
1da177e4 LT |
52 | /************************************************************************* |
53 | * IXP4xx chipset I/O mapping | |
54 | *************************************************************************/ | |
55 | static struct map_desc ixp4xx_io_desc[] __initdata = { | |
56 | { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */ | |
13ec32f4 | 57 | .virtual = (unsigned long)IXP4XX_PERIPHERAL_BASE_VIRT, |
87fe04bd | 58 | .pfn = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS), |
1da177e4 LT |
59 | .length = IXP4XX_PERIPHERAL_REGION_SIZE, |
60 | .type = MT_DEVICE | |
61 | }, { /* Expansion Bus Config Registers */ | |
13ec32f4 | 62 | .virtual = (unsigned long)IXP4XX_EXP_CFG_BASE_VIRT, |
87fe04bd | 63 | .pfn = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS), |
1da177e4 LT |
64 | .length = IXP4XX_EXP_CFG_REGION_SIZE, |
65 | .type = MT_DEVICE | |
66 | }, { /* PCI Registers */ | |
13ec32f4 | 67 | .virtual = (unsigned long)IXP4XX_PCI_CFG_BASE_VIRT, |
87fe04bd | 68 | .pfn = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS), |
1da177e4 LT |
69 | .length = IXP4XX_PCI_CFG_REGION_SIZE, |
70 | .type = MT_DEVICE | |
f0cdb153 KH |
71 | }, { /* Queue Manager */ |
72 | .virtual = (unsigned long)IXP4XX_QMGR_BASE_VIRT, | |
73 | .pfn = __phys_to_pfn(IXP4XX_QMGR_BASE_PHYS), | |
74 | .length = IXP4XX_QMGR_REGION_SIZE, | |
75 | .type = MT_DEVICE | |
5932ae3f | 76 | }, |
1da177e4 LT |
77 | }; |
78 | ||
79 | void __init ixp4xx_map_io(void) | |
80 | { | |
81 | iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc)); | |
82 | } | |
83 | ||
84 | ||
85 | /************************************************************************* | |
86 | * IXP4xx chipset IRQ handling | |
87 | * | |
88 | * TODO: GPIO IRQs should be marked invalid until the user of the IRQ | |
89 | * (be it PCI or something else) configures that GPIO line | |
90 | * as an IRQ. | |
91 | **************************************************************************/ | |
bdf82b59 DS |
92 | enum ixp4xx_irq_type { |
93 | IXP4XX_IRQ_LEVEL, IXP4XX_IRQ_EDGE | |
94 | }; | |
95 | ||
984d115b KH |
96 | /* Each bit represents an IRQ: 1: edge-triggered, 0: level triggered */ |
97 | static unsigned long long ixp4xx_irq_edge = 0; | |
bdf82b59 DS |
98 | |
99 | /* | |
100 | * IRQ -> GPIO mapping table | |
101 | */ | |
6cc1b658 | 102 | static signed char irq2gpio[32] = { |
bdf82b59 DS |
103 | -1, -1, -1, -1, -1, -1, 0, 1, |
104 | -1, -1, -1, -1, -1, -1, -1, -1, | |
105 | -1, -1, -1, 2, 3, 4, 5, 6, | |
106 | 7, 8, 9, 10, 11, 12, -1, -1, | |
107 | }; | |
108 | ||
9dde0ae3 | 109 | static int ixp4xx_gpio_to_irq(struct gpio_chip *chip, unsigned gpio) |
25735d10 MS |
110 | { |
111 | int irq; | |
112 | ||
113 | for (irq = 0; irq < 32; irq++) { | |
114 | if (irq2gpio[irq] == gpio) | |
115 | return irq; | |
116 | } | |
117 | return -EINVAL; | |
118 | } | |
25735d10 | 119 | |
ee04087a | 120 | static int ixp4xx_set_irq_type(struct irq_data *d, unsigned int type) |
bdf82b59 | 121 | { |
ee04087a | 122 | int line = irq2gpio[d->irq]; |
bdf82b59 DS |
123 | u32 int_style; |
124 | enum ixp4xx_irq_type irq_type; | |
125 | volatile u32 *int_reg; | |
126 | ||
127 | /* | |
128 | * Only for GPIO IRQs | |
129 | */ | |
130 | if (line < 0) | |
131 | return -EINVAL; | |
132 |