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1da177e4 LT |
1 | /* |
2 | * arch/arm/mach-ixp4xx/common.c | |
3 | * | |
4 | * Generic code shared across all IXP4XX platforms | |
5 | * | |
6 | * Maintainer: Deepak Saxena <dsaxena@plexity.net> | |
7 | * | |
8 | * Copyright 2002 (c) Intel Corporation | |
9 | * Copyright 2003-2004 (c) MontaVista, Software, Inc. | |
10 | * | |
11 | * This file is licensed under the terms of the GNU General Public | |
12 | * License version 2. This program is licensed "as is" without any | |
13 | * warranty of any kind, whether express or implied. | |
14 | */ | |
15 | ||
16 | #include <linux/config.h> | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/mm.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/serial.h> | |
21 | #include <linux/sched.h> | |
22 | #include <linux/tty.h> | |
23 | #include <linux/serial_core.h> | |
24 | #include <linux/bootmem.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/bitops.h> | |
27 | #include <linux/time.h> | |
28 | #include <linux/timex.h> | |
29 | ||
30 | #include <asm/hardware.h> | |
31 | #include <asm/uaccess.h> | |
32 | #include <asm/io.h> | |
33 | #include <asm/pgtable.h> | |
34 | #include <asm/page.h> | |
35 | #include <asm/irq.h> | |
36 | ||
37 | #include <asm/mach/map.h> | |
38 | #include <asm/mach/irq.h> | |
39 | #include <asm/mach/time.h> | |
40 | ||
1da177e4 LT |
41 | /************************************************************************* |
42 | * IXP4xx chipset I/O mapping | |
43 | *************************************************************************/ | |
44 | static struct map_desc ixp4xx_io_desc[] __initdata = { | |
45 | { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */ | |
46 | .virtual = IXP4XX_PERIPHERAL_BASE_VIRT, | |
47 | .physical = IXP4XX_PERIPHERAL_BASE_PHYS, | |
48 | .length = IXP4XX_PERIPHERAL_REGION_SIZE, | |
49 | .type = MT_DEVICE | |
50 | }, { /* Expansion Bus Config Registers */ | |
51 | .virtual = IXP4XX_EXP_CFG_BASE_VIRT, | |
52 | .physical = IXP4XX_EXP_CFG_BASE_PHYS, | |
53 | .length = IXP4XX_EXP_CFG_REGION_SIZE, | |
54 | .type = MT_DEVICE | |
55 | }, { /* PCI Registers */ | |
56 | .virtual = IXP4XX_PCI_CFG_BASE_VIRT, | |
57 | .physical = IXP4XX_PCI_CFG_BASE_PHYS, | |
58 | .length = IXP4XX_PCI_CFG_REGION_SIZE, | |
59 | .type = MT_DEVICE | |
5932ae3f DS |
60 | }, |
61 | #ifdef CONFIG_DEBUG_LL | |
62 | { /* Debug UART mapping */ | |
63 | .virtual = IXP4XX_DEBUG_UART_BASE_VIRT, | |
64 | .physical = IXP4XX_DEBUG_UART_BASE_PHYS, | |
65 | .length = IXP4XX_DEBUG_UART_REGION_SIZE, | |
66 | .type = MT_DEVICE | |
1da177e4 | 67 | } |
5932ae3f | 68 | #endif |
1da177e4 LT |
69 | }; |
70 | ||
71 | void __init ixp4xx_map_io(void) | |
72 | { | |
73 | iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc)); | |
74 | } | |
75 | ||
76 | ||
77 | /************************************************************************* | |
78 | * IXP4xx chipset IRQ handling | |
79 | * | |
80 | * TODO: GPIO IRQs should be marked invalid until the user of the IRQ | |
81 | * (be it PCI or something else) configures that GPIO line | |
82 | * as an IRQ. | |
83 | **************************************************************************/ | |
bdf82b59 DS |
84 | enum ixp4xx_irq_type { |
85 | IXP4XX_IRQ_LEVEL, IXP4XX_IRQ_EDGE | |
86 | }; | |
87 | ||
88 | static void ixp4xx_config_irq(unsigned irq, enum ixp4xx_irq_type type); | |
89 | ||
90 | /* | |
91 | * IRQ -> GPIO mapping table | |
92 | */ | |
93 | static int irq2gpio[32] = { | |
94 | -1, -1, -1, -1, -1, -1, 0, 1, | |
95 | -1, -1, -1, -1, -1, -1, -1, -1, | |
96 | -1, -1, -1, 2, 3, 4, 5, 6, | |
97 | 7, 8, 9, 10, 11, 12, -1, -1, | |
98 | }; | |
99 | ||
100 | static int ixp4xx_set_irq_type(unsigned int irq, unsigned int type) | |
101 | { | |
102 | int line = irq2gpio[irq]; | |
103 | u32 int_style; | |
104 | enum ixp4xx_irq_type irq_type; | |
105 | volatile u32 *int_reg; | |
106 | ||
107 | /* | |
108 | * Only for GPIO IRQs | |
109 | */ | |
110 | if (line < 0) | |
111 | return -EINVAL; | |
112 | ||
113 | if (type & IRQT_BOTHEDGE) { | |
114 | int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL; | |
115 | irq_type = IXP4XX_IRQ_EDGE; | |
116 | } else if (type & IRQT_RISING) { | |
117 | int_style = IXP4XX_GPIO_STYLE_RISING_EDGE; | |
118 | irq_type = IXP4XX_IRQ_EDGE; | |
119 | } else if (type & IRQT_FALLING) { | |
120 | int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE; | |
121 | irq_type = IXP4XX_IRQ_EDGE; | |
122 | } else if (type & IRQT_HIGH) { | |
123 | int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH; | |
124 | irq_type = IXP4XX_IRQ_LEVEL; | |
125 | } else if (type & IRQT_LOW) { | |
126 | int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW; | |
127 | irq_type = IXP4XX_IRQ_LEVEL; | |
6132f9e1 DV |
128 | } else |
129 | return -EINVAL; | |
bdf82b59 DS |
130 | |
131 | ixp4xx_config_irq(irq, irq_type); | |
132 | ||
133 | if (line >= 8) { /* pins 8-15 */ | |
134 | line -= 8; | |
135 | int_reg = IXP4XX_GPIO_GPIT2R; | |
136 | } else { /* pins 0-7 */ | |
137 | int_reg = IXP4XX_GPIO_GPIT1R; | |
138 | } | |
139 | ||
140 | /* Clear the style for the appropriate pin */ | |
141 | *int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR << | |
142 | (line * IXP4XX_GPIO_STYLE_SIZE)); | |
143 | ||
144 | /* Set the new style */ | |
145 | *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE)); | |
6132f9e1 DV |
146 | |
147 | return 0; | |
bdf82b59 DS |
148 | } |
149 | ||
1da177e4 LT |
150 | static void ixp4xx_irq_mask(unsigned int irq) |
151 | { | |
152 | if (cpu_is_ixp46x() && irq >= 32) | |
153 | *IXP4XX_ICMR2 &= ~(1 << (irq - 32)); | |
154 | else | |
155 | *IXP4XX_ICMR &= ~(1 << irq); | |
156 | } | |
157 | ||
158 | static void ixp4xx_irq_unmask(unsigned int irq) | |
159 | { | |
160 | if (cpu_is_ixp46x() && irq >= 32) | |
161 | *IXP4XX_ICMR2 |= (1 << (irq - 32)); | |
162 | else | |
163 | *IXP4XX_ICMR |= (1 << irq); | |
164 | } | |
165 | ||
166 | static void ixp4xx_irq_ack(unsigned int irq) | |
167 | { | |
1da177e4 LT |
168 | int line = (irq < 32) ? irq2gpio[irq] : -1; |
169 | ||
170 | if (line >= 0) | |
171 | gpio_line_isr_clear(line); | |
172 | } | |
173 | ||
174 | /* | |
175 | * Level triggered interrupts on GPIO lines can only be cleared when the | |
176 | * interrupt condition disappears. | |
177 | */ | |
178 | static void ixp4xx_irq_level_unmask(unsigned int irq) | |
179 | { | |
180 | ixp4xx_irq_ack(irq); | |
181 | ixp4xx_irq_unmask(irq); | |
182 | } | |
183 | ||
184 | static struct irqchip ixp4xx_irq_level_chip = { | |
2be863c9 RK |
185 | .ack = ixp4xx_irq_mask, |
186 | .mask = ixp4xx_irq_mask, | |
187 | .unmask = ixp4xx_irq_level_unmask, | |
188 | .set_type = ixp4xx_set_irq_type, | |
1da177e4 LT |
189 | }; |
190 | ||
191 | static struct irqchip ixp4xx_irq_edge_chip = { | |
2be863c9 RK |
192 | .ack = ixp4xx_irq_ack, |
193 | .mask = ixp4xx_irq_mask, | |
194 | .unmask = ixp4xx_irq_unmask, | |
195 | .set_type = ixp4xx_set_irq_type, | |
1da177e4 LT |
196 | }; |
197 | ||
198 | static void ixp4xx_config_irq(unsigned irq, enum ixp4xx_irq_type type) | |
199 | { | |
200 | switch (type) { | |
201 | case IXP4XX_IRQ_LEVEL: | |
202 | set_irq_chip(irq, &ixp4xx_irq_level_chip); | |
203 | set_irq_handler(irq, do_level_IRQ); | |
204 | break; | |
205 | case IXP4XX_IRQ_EDGE: | |
206 | set_irq_chip(irq, &ixp4xx_irq_edge_chip); | |
207 | set_irq_handler(irq, do_edge_IRQ); | |
208 | break; | |
209 | } | |
210 | set_irq_flags(irq, IRQF_VALID); | |
211 | } | |
212 | ||
213 | void __init ixp4xx_init_irq(void) | |
214 | { | |
215 | int i = 0; | |
216 | ||
217 | /* Route all sources to IRQ instead of FIQ */ | |
218 | *IXP4XX_ICLR = 0x0; | |
219 | ||
220 | /* Disable all interrupt */ | |
221 | *IXP4XX_ICMR = 0x0; | |
222 | ||
223 | if (cpu_is_ixp46x()) { | |
224 | /* Route upper 32 sources to IRQ instead of FIQ */ | |
225 | *IXP4XX_ICLR2 = 0x00; | |
226 | ||
227 | /* Disable upper 32 interrupts */ | |
228 | *IXP4XX_ICMR2 = 0x00; | |
229 | } | |
230 | ||
231 | /* Default to all level triggered */ | |
232 | for(i = 0; i < NR_IRQS; i++) | |
233 | ixp4xx_config_irq(i, IXP4XX_IRQ_LEVEL); | |
234 | } | |
235 | ||
236 | ||
237 | /************************************************************************* | |
238 | * IXP4xx timer tick | |
239 | * We use OS timer1 on the CPU for the timer tick and the timestamp | |
240 | * counter as a source of real clock ticks to account for missed jiffies. | |
241 | *************************************************************************/ | |
242 | ||
243 | static unsigned volatile last_jiffy_time; | |
244 | ||
245 | #define CLOCK_TICKS_PER_USEC ((CLOCK_TICK_RATE + USEC_PER_SEC/2) / USEC_PER_SEC) | |
246 | ||
247 | /* IRQs are disabled before entering here from do_gettimeofday() */ | |
248 | static unsigned long ixp4xx_gettimeoffset(void) | |
249 | { | |
250 | u32 elapsed; | |
251 | ||
252 | elapsed = *IXP4XX_OSTS - last_jiffy_time; | |
253 | ||
254 | return elapsed / CLOCK_TICKS_PER_USEC; | |
255 | } | |
256 | ||
257 | static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) | |
258 | { | |
259 | write_seqlock(&xtime_lock); | |
260 | ||
261 | /* Clear Pending Interrupt by writing '1' to it */ | |
262 | *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND; | |
263 | ||
264 | /* | |
265 | * Catch up with the real idea of time | |
266 | */ | |
267 | while ((*IXP4XX_OSTS - last_jiffy_time) > LATCH) { | |
268 | timer_tick(regs); | |
269 | last_jiffy_time += LATCH; | |
270 | } | |
271 | ||
272 | write_sequnlock(&xtime_lock); | |
273 | ||
274 | return IRQ_HANDLED; | |
275 | } | |
276 | ||
277 | static struct irqaction ixp4xx_timer_irq = { | |
278 | .name = "IXP4xx Timer Tick", | |
09b8b5f8 RK |
279 | .flags = SA_INTERRUPT | SA_TIMER, |
280 | .handler = ixp4xx_timer_interrupt, | |
1da177e4 LT |
281 | }; |
282 | ||
283 | static void __init ixp4xx_timer_init(void) | |
284 | { | |
285 | /* Clear Pending Interrupt by writing '1' to it */ | |
286 | *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND; | |
287 | ||
288 | /* Setup the Timer counter value */ | |
289 | *IXP4XX_OSRT1 = (LATCH & ~IXP4XX_OST_RELOAD_MASK) | IXP4XX_OST_ENABLE; | |
290 | ||
291 | /* Reset time-stamp counter */ | |
292 | *IXP4XX_OSTS = 0; | |
293 | last_jiffy_time = 0; | |
294 | ||
295 | /* Connect the interrupt handler and enable the interrupt */ | |
296 | setup_irq(IRQ_IXP4XX_TIMER1, &ixp4xx_timer_irq); | |
297 | } | |
298 | ||
299 | struct sys_timer ixp4xx_timer = { | |
300 | .init = ixp4xx_timer_init, | |
301 | .offset = ixp4xx_gettimeoffset, | |
302 | }; | |
303 | ||
304 | static struct resource ixp46x_i2c_resources[] = { | |
305 | [0] = { | |
306 | .start = 0xc8011000, | |
307 | .end = 0xc801101c, | |
308 | .flags = IORESOURCE_MEM, | |
309 | }, | |
310 | [1] = { | |
311 | .start = IRQ_IXP4XX_I2C, | |
312 | .end = IRQ_IXP4XX_I2C, | |
313 | .flags = IORESOURCE_IRQ | |
314 | } | |
315 | }; | |
316 | ||
317 | /* | |
318 | * I2C controller. The IXP46x uses the same block as the IOP3xx, so | |
319 | * we just use the same device name. | |
320 | */ | |
321 | static struct platform_device ixp46x_i2c_controller = { | |
322 | .name = "IOP3xx-I2C", | |
323 | .id = 0, | |
324 | .num_resources = 2, | |
325 | .resource = ixp46x_i2c_resources | |
326 | }; | |
327 | ||
328 | static struct platform_device *ixp46x_devices[] __initdata = { | |
329 | &ixp46x_i2c_controller | |
330 | }; | |
331 | ||
332 | void __init ixp4xx_sys_init(void) | |
333 | { | |
334 | if (cpu_is_ixp46x()) { | |
335 | platform_add_devices(ixp46x_devices, | |
336 | ARRAY_SIZE(ixp46x_devices)); | |
337 | } | |
338 | } | |
339 |