Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * arch/arm/mach-ixp4xx/common.c | |
3 | * | |
4 | * Generic code shared across all IXP4XX platforms | |
5 | * | |
6 | * Maintainer: Deepak Saxena <dsaxena@plexity.net> | |
7 | * | |
8 | * Copyright 2002 (c) Intel Corporation | |
9 | * Copyright 2003-2004 (c) MontaVista, Software, Inc. | |
10 | * | |
11 | * This file is licensed under the terms of the GNU General Public | |
12 | * License version 2. This program is licensed "as is" without any | |
13 | * warranty of any kind, whether express or implied. | |
14 | */ | |
15 | ||
1da177e4 LT |
16 | #include <linux/kernel.h> |
17 | #include <linux/mm.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/serial.h> | |
1da177e4 | 20 | #include <linux/tty.h> |
d052d1be | 21 | #include <linux/platform_device.h> |
1da177e4 | 22 | #include <linux/serial_core.h> |
1da177e4 LT |
23 | #include <linux/interrupt.h> |
24 | #include <linux/bitops.h> | |
25 | #include <linux/time.h> | |
26 | #include <linux/timex.h> | |
84904d0e | 27 | #include <linux/clocksource.h> |
e32f1502 | 28 | #include <linux/clockchips.h> |
fced80c7 | 29 | #include <linux/io.h> |
dc28094b | 30 | #include <linux/export.h> |
9dde0ae3 | 31 | #include <linux/gpio.h> |
1da177e4 | 32 | |
a09e64fb RK |
33 | #include <mach/udc.h> |
34 | #include <mach/hardware.h> | |
f449588c | 35 | #include <mach/io.h> |
1da177e4 | 36 | #include <asm/uaccess.h> |
1da177e4 LT |
37 | #include <asm/pgtable.h> |
38 | #include <asm/page.h> | |
39 | #include <asm/irq.h> | |
5b0d495c | 40 | #include <asm/sched_clock.h> |
86dfe446 | 41 | #include <asm/system_misc.h> |
1da177e4 LT |
42 | |
43 | #include <asm/mach/map.h> | |
44 | #include <asm/mach/irq.h> | |
45 | #include <asm/mach/time.h> | |
46 | ||
ceb69a89 MP |
47 | static void __init ixp4xx_clocksource_init(void); |
48 | static void __init ixp4xx_clockevent_init(void); | |
e32f1502 | 49 | static struct clock_event_device clockevent_ixp4xx; |
f9a8ca1c | 50 | |
1da177e4 LT |
51 | /************************************************************************* |
52 | * IXP4xx chipset I/O mapping | |
53 | *************************************************************************/ | |
54 | static struct map_desc ixp4xx_io_desc[] __initdata = { | |
55 | { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */ | |
13ec32f4 | 56 | .virtual = (unsigned long)IXP4XX_PERIPHERAL_BASE_VIRT, |
87fe04bd | 57 | .pfn = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS), |
1da177e4 LT |
58 | .length = IXP4XX_PERIPHERAL_REGION_SIZE, |
59 | .type = MT_DEVICE | |
60 | }, { /* Expansion Bus Config Registers */ | |
13ec32f4 | 61 | .virtual = (unsigned long)IXP4XX_EXP_CFG_BASE_VIRT, |
87fe04bd | 62 | .pfn = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS), |
1da177e4 LT |
63 | .length = IXP4XX_EXP_CFG_REGION_SIZE, |
64 | .type = MT_DEVICE | |
65 | }, { /* PCI Registers */ | |
13ec32f4 | 66 | .virtual = (unsigned long)IXP4XX_PCI_CFG_BASE_VIRT, |
87fe04bd | 67 | .pfn = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS), |
1da177e4 LT |
68 | .length = IXP4XX_PCI_CFG_REGION_SIZE, |
69 | .type = MT_DEVICE | |
f0cdb153 KH |
70 | }, { /* Queue Manager */ |
71 | .virtual = (unsigned long)IXP4XX_QMGR_BASE_VIRT, | |
72 | .pfn = __phys_to_pfn(IXP4XX_QMGR_BASE_PHYS), | |
73 | .length = IXP4XX_QMGR_REGION_SIZE, | |
74 | .type = MT_DEVICE | |
5932ae3f DS |
75 | }, |
76 | #ifdef CONFIG_DEBUG_LL | |
77 | { /* Debug UART mapping */ | |
13ec32f4 | 78 | .virtual = (unsigned long)IXP4XX_DEBUG_UART_BASE_VIRT, |
87fe04bd | 79 | .pfn = __phys_to_pfn(IXP4XX_DEBUG_UART_BASE_PHYS), |
5932ae3f DS |
80 | .length = IXP4XX_DEBUG_UART_REGION_SIZE, |
81 | .type = MT_DEVICE | |
1da177e4 | 82 | } |
5932ae3f | 83 | #endif |
1da177e4 LT |
84 | }; |
85 | ||
86 | void __init ixp4xx_map_io(void) | |
87 | { | |
88 | iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc)); | |
89 | } | |
90 | ||
91 | ||
92 | /************************************************************************* | |
93 | * IXP4xx chipset IRQ handling | |
94 | * | |
95 | * TODO: GPIO IRQs should be marked invalid until the user of the IRQ | |
96 | * (be it PCI or something else) configures that GPIO line | |
97 | * as an IRQ. | |
98 | **************************************************************************/ | |
bdf82b59 DS |
99 | enum ixp4xx_irq_type { |
100 | IXP4XX_IRQ_LEVEL, IXP4XX_IRQ_EDGE | |
101 | }; | |
102 | ||
984d115b KH |
103 | /* Each bit represents an IRQ: 1: edge-triggered, 0: level triggered */ |
104 | static unsigned long long ixp4xx_irq_edge = 0; | |
bdf82b59 DS |
105 | |
106 | /* | |
107 | * IRQ -> GPIO mapping table | |
108 | */ | |
6cc1b658 | 109 | static signed char irq2gpio[32] = { |
bdf82b59 DS |
110 | -1, -1, -1, -1, -1, -1, 0, 1, |
111 | -1, -1, -1, -1, -1, -1, -1, -1, | |
112 | -1, -1, -1, 2, 3, 4, 5, 6, | |
113 | 7, 8, 9, 10, 11, 12, -1, -1, | |
114 | }; | |
115 | ||
9dde0ae3 | 116 | static int ixp4xx_gpio_to_irq(struct gpio_chip *chip, unsigned gpio) |
25735d10 MS |
117 | { |
118 | int irq; | |
119 | ||
120 | for (irq = 0; irq < 32; irq++) { | |
121 | if (irq2gpio[irq] == gpio) | |
122 | return irq; | |
123 | } | |
124 | return -EINVAL; | |
125 | } | |
25735d10 | 126 | |
efec194f | 127 | int irq_to_gpio(unsigned int irq) |
25735d10 MS |
128 | { |
129 | int gpio = (irq < 32) ? irq2gpio[irq] : -EINVAL; | |
130 | ||
131 | if (gpio == -1) | |
132 | return -EINVAL; | |
133 | ||
134 | return gpio; | |
135 | } | |
136 | EXPORT_SYMBOL(irq_to_gpio); | |
137 | ||
ee04087a | 138 | static int ixp4xx_set_irq_type(struct irq_data *d, unsigned int type) |
bdf82b59 | 139 | { |
ee04087a | 140 | int line = irq2gpio[d->irq]; |
bdf82b59 DS |
141 | u32 int_style; |
142 | enum ixp4xx_irq_type irq_type; | |
143 | volatile u32 *int_reg; | |
144 | ||
145 | /* | |
146 | * Only for GPIO IRQs | |
147 | */ | |
148 | if (line < 0) | |
149 | return -EINVAL; | |
150 |